On Wed, Dec 10, 2014 at 02:44:01PM +0900, Magnus Damm wrote:
Hi Wolfram, Geert,
On Tue, Dec 9, 2014 at 11:09 PM, Wolfram Sang w...@the-dreams.de wrote:
On Tue, Dec 09, 2014 at 11:53:45AM +0100, Geert Uytterhoeven wrote:
Hi Wolfram,
On Fri, Nov 7, 2014 at 11:11 AM, Wolfram Sang
Hi Simon,
On Wed, Dec 10, 2014 at 1:33 AM, Simon Horman ho...@verge.net.au wrote:
On Tue, Dec 09, 2014 at 12:22:45PM +0100, Geert Uytterhoeven wrote:
This patch series add restart support for r8a7791/koelsch through the
watchdog
in the DA9063 PMIC. Restart can be triggered in two ways:
1.
Cadence I2C controller has the following bugs:
- completion indication is not given to the driver at the end of
a read/receive transfer with HOLD bit set.
- Invalid read transaction are generated on the bus when HW timeout
condition occurs with HOLD bit set.
As a result of the above, if a set of
From: Wolfram Sang wsa+rene...@sang-engineering.com
We don't need the mask since we obtain the channels via DT.
Signed-off-by: Wolfram Sang wsa+rene...@sang-engineering.com
---
drivers/i2c/busses/i2c-sh_mobile.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
From: Wolfram Sang wsa+rene...@sang-engineering.com
Refactor DMA setup to keep the errno so we can implement better
deferred probe support in the next step.
Signed-off-by: Wolfram Sang wsa+rene...@sang-engineering.com
---
drivers/i2c/busses/i2c-sh_mobile.c | 35
From: Wolfram Sang wsa+rene...@sang-engineering.com
DMA is opt-in for this driver. So, we can't use deferred probing in
probe, because our driver would get endlessly deferred if DMA support is
compiled in but only the DMA driver is missing. Because we can't know
when the DMA driver might show up,
Hi Wolfram,
On Wed, Dec 10, 2014 at 2:21 PM, Wolfram Sang w...@the-dreams.de wrote:
Okay, here is my take on solving the problem found by Geert. I still don't
like
it much but it is not as bad as I expected it to be ;) Let me know what you
think.
Thanks, it's indeed less ugly than I would
(CC'ing the dmaengine mailing list)
On Wednesday 10 December 2014 09:01:55 Wolfram Sang wrote:
On Wed, Dec 10, 2014 at 02:44:01PM +0900, Magnus Damm wrote:
On Tue, Dec 9, 2014 at 11:09 PM, Wolfram Sang w...@the-dreams.de wrote:
On Tue, Dec 09, 2014 at 11:53:45AM +0100, Geert Uytterhoeven
On Wed, Dec 10, 2014 at 2:21 PM, Wolfram Sang w...@the-dreams.de wrote:
Okay, here is my take on solving the problem found by Geert. I still don't
like
it much but it is not as bad as I expected it to be ;) Let me know what you
think.
Thanks, it's indeed less ugly than I would have
On Wed, Dec 10, 2014 at 04:19:36PM +0200, Laurent Pinchart wrote:
(CC'ing the dmaengine mailing list)
Thanks!
On Wednesday 10 December 2014 09:01:55 Wolfram Sang wrote:
On Wed, Dec 10, 2014 at 02:44:01PM +0900, Magnus Damm wrote:
On Tue, Dec 9, 2014 at 11:09 PM, Wolfram Sang
On Wed, 2014-12-10 at 05:14PM +0530, Harini Katakam wrote:
Cadence I2C controller has the following bugs:
- completion indication is not given to the driver at the end of
a read/receive transfer with HOLD bit set.
- Invalid read transaction are generated on the bus when HW timeout
condition
Hello.
On 12/10/2014 04:21 PM, Wolfram Sang wrote:
From: Wolfram Sang wsa+rene...@sang-engineering.com
Refactor DMA setup to keep the errno so we can implement better
deferred probe support in the next step.
Signed-off-by: Wolfram Sang wsa+rene...@sang-engineering.com
---
On Wed, Dec 10, 2014 at 11:06:25AM +0100, Geert Uytterhoeven wrote:
Hi Simon,
On Wed, Dec 10, 2014 at 1:33 AM, Simon Horman ho...@verge.net.au wrote:
On Tue, Dec 09, 2014 at 12:22:45PM +0100, Geert Uytterhoeven wrote:
This patch series add restart support for r8a7791/koelsch through the
readl/writel is too expensive especially on Cortex A9 w/ outer L2 cache.
This introduces i2c read/write errors on Marvell BG2/BG2Q SoCs when there
are heavy L2 cache maintenance operations at the same time.
The driver does not perform DMA, so it's safe to use the relaxed version.
From another
Hi Soren,
On Wed, Dec 10, 2014 at 11:15 PM, Sören Brinkmann
soren.brinkm...@xilinx.com wrote:
On Wed, 2014-12-10 at 05:14PM +0530, Harini Katakam wrote:
Cadence I2C controller has the following bugs:
- completion indication is not given to the driver at the end of
a read/receive transfer with
Hello,
I like it now. There are only a few small nitpicks, not sure its worth
to respin if noone else has concerns. See below.
On Thu, Dec 11, 2014 at 02:00:49PM +0800, Addy Ke wrote:
The number of clock cycles to be written into the CLKDIV register
that determines the I2C clk high phase
16 matches
Mail list logo
