On Wed, 2015-07-08 at 13:15 +0300, Andy Shevchenko wrote:
The mentioned flag fixes a warning on Intel Edison board since one of
the I2C
controller shares IRQ line with watchdog timer.
Wolfram, do you have any comments on this?
Signed-off-by: Andy Shevchenko
On 07/27/2015 06:38 AM, Matt Fleming wrote:
From: Mika Westerberg mika.westerb...@linux.intel.com
Starting from Intel Sunrisepoint (Skylake PCH) the iTCO watchdog resources
have been moved to reside under the i801 SMBus host controller whereas
previously they were under the LPC device.
In
This interrupt could have been useful for repeated start transfers
as the current transfer could be marked as complete while it's
processing the final byte of the transfer.
But having to use the transaction halt interrupt to safely control
repeated start transfers, means handling of the fifo
Following patches are required to enchance the existing driver to
support i2c on pistachio.
This patch series depends on the series of fixes posted earlier[1].
The features added in this series were tested with the earlier fixes
series.
Tested on Pistachio bub and on tz1090 using an Adafruit I2C
Stop Detected interrupt is triggered when a Stop bit is detected on
the bus, which indicates the end of the current transfer.
When the end of a transfer is indicated by the Stop bit interrupt,
drain the FIFO and signal completion for the transaction. But if the
interrupt was triggered before all
In version 3.3 of the IP when transaction halt is set, an interrupt
will be generated after each byte of a transfer instead of after
every transfer but before the stop bit.
Due to this behaviour we have to be careful that every time we
release the transaction halt we have to re-enable it straight
We can mark the transfer as complete without waiting for the stop
bit. This is important when handling repeated start transfers as
we have to start the next transfer without the stop bit being issued.
Signed-off-by: Sifan Naeem sifan.na...@imgtec.com
---
drivers/i2c/busses/i2c-img-scb.c |7
Master halt is issued after each byte of a transaction is processed in
IP version 3.3.
Master halt will stall the bus by holding the SCK line low until the
halt bit in the scb_general_control is cleared.
After the last byte of a transfer is processed we can use the Master
Halt interrupt to
We can mark the transfer as complete without waiting for the stop
bit. This is important when handling repeated start transfers as
we have to start the next transfer without the stop bit being issued.
This doesn't affect the older versions of the IP.
Signed-off-by: Sifan Naeem
This commit adds support for the I2C_M_IGNORE_NAK protocol
modification.
Such behaviour can only be implemented in atomic mode. So, if a
transaction contains a message with such flag the drivers
switches to atomic mode. The implementation consists simply in
treating NAKs as ACKs.
Signed-off-by:
The requested bit rate can be outside the range supported by the driver.
The maximum bit rate this driver supports at the moment is 400Khz.
Return -EINVAL if the bit rate is larger than 400khz.
Maximum speed supported by the driver can be increased to 1Mhz by
adding support for fast plus mode in
Clear line status and all interrupts when transaction is complete,
as not doing so might leave unserviced interrupts that might be
handled in the context of a new transfer. Soft reset if the the
transfer failed to bring back the i2c block to a reset state.
Fixes: 27bce4 (i2c: img-scb: Add
The code to read from the master read fifo, and write to the master
write fifo, checks a bit in an SCB register before every byte to
ensure that the fifo is not full (write fifo) or empty (read fifo).
Due to clock domain crossing inside the SCB block the updated value
of this bit is only visible
Reset interrupt enable register and clear any generated interrupts
to make sure of a clean slate after a soft reset. Not doing so might
leave unhandle line status or generated interrupts which can cause
issues when handling new transfers.
Fixes: 27bce4 (i2c: img-scb: Add Imagination Technologies
Using % can be slow depending on the architecture.
Using DIV_ROUND_UP is nicer and more efficient way to do it.
Fixes: 27bce4 (i2c: img-scb: Add Imagination Technologies I2C SCB driver)
Signed-off-by: Sifan Naeem sifan.na...@imgtec.com
Cc: Stable kernel (v3.19+) sta...@vger.kernel.org
---
Following patches are required to fix the existing driver to
support i2c on pistachio.
Tested on Pistachio bub using an Adafruit I2C Non-Volatile FRAM Breakout
(256Kbit / 32KByte) eeprom.
Used i2c buildroot tools to test the eeprom and the other i2c blocks.
Also used dd commands to copy data to
Remove start bit detected status after it is handled,
doing so will prevent this condition being hit for
every interrupt on a particular transfer.
Fixes: 27bce4 (i2c: img-scb: Add Imagination Technologies I2C SCB driver)
Signed-off-by: Sifan Naeem sifan.na...@imgtec.com
Cc: Stable kernel (v3.19+)
Move scb_wr_rd_fence to before reading from fifo and writing to
fifo to make sure the the first read/write is done after the required
number of cycles.
Fixes: 27bce4 (i2c: img-scb: Add Imagination Technologies I2C SCB driver)
Signed-off-by: Sifan Naeem sifan.na...@imgtec.com
Acked-by: James Hogan
After determining the minimum value for the High period (TCKH) the
remainder of the internal clock pulses is set as the Low period (TCKL).
This causes the i2c clock duty cycle to be much less than 50%.
The fix suggested here, start with TCKH and TCKL at 50% of the internal
clock pulses and
of_find_i2c_adapter_by_node() call requires quite often missing
put_device(), and i2c_put_adapter() releases a device locked by
i2c_get_adapter() only. In general module_put(adapter-owner) and
put_device(dev) are not interchangeable.
This is a common error reproduction scenario as a result of the
This change is needed to properly lock I2C parent bus driver.
Prior to this change i2c_put_adapter() is misused, which may lead
to an overflow over zero of I2C bus driver user counter.
By the way added a missing of_node_put() to eliminate memory leak,
if OF_DYNAMIC is enabled.
Signed-off-by:
The series fixes i2c bus device refcounting for clients of i2c_get_adapter(),
of_find_i2c_adapter_by_node() and of_find_i2c_device_by_node() interfaces.
The v2 3/4 change adds and exports new of_get_i2c_adapter_by_node()
interface of i2c core, v2 4/4 is an unchanged version of v1 10/10, which
If of_find_i2c_device_by_node() or of_find_i2c_adapter_by_node() find
a device by node, but its type does not match, a reference to that
device is still held. This change fixes the problem.
Signed-off-by: Vladimir Zapolskiy vladimir_zapols...@mentor.com
---
Changes from v1 to v2:
* none, new
A git bisect just pointed me at commit d32932d02e18 (x86/irq: Convert
IOAPIC to use hierarchical irqdomain interfaces) as the reason for why
the trackpad on my Dell XPS13 is no longer working with v4.2-rc1.
I'm now seeing the following errors when booting,
[1.615017] i2c_designware
On Tue, Jul 21, 2015 at 06:11:05PM +0530, Vaibhav Hiremath wrote:
With addition of PXA910 family of devices, the TWSI module supports
new feature which allows us to adjust SCLK. i2c-pxa driver takes input
configuration in nsec and converts it to respective bit-fields,
- i2c-sclk-low-time-ns
In addition to module_get()/module_put() add get_device()/put_device()
calls into i2c_get_adapter()/i2c_put_adapter() exported
interfaces. This is done to lock I2C bus device, if it is in use by a
client.
Signed-off-by: Vladimir Zapolskiy vladimir_zapols...@mentor.com
---
Changes from v1 to v2:
*
On 2015/7/27 23:21, Matt Fleming wrote:
A git bisect just pointed me at commit d32932d02e18 (x86/irq: Convert
IOAPIC to use hierarchical irqdomain interfaces) as the reason for why
the trackpad on my Dell XPS13 is no longer working with v4.2-rc1.
I'm now seeing the following errors when
From: Liguo Zhang liguo.zh...@mediatek.com
Reset i2c dma engine in hw init function.
When occur i2c ack error, mtk_i2c_irq may is twice,
first is the ack error interrupt, then the complete interrupt,
so i2c-irq_stat need keep the two interrupt value, and only
call complete() for the complete
For most of imx platforms, there have no DMA support for I2C bus.
So, by default, there is only cpu mode.
The current driver to check whether there have DMA channel config in
dts file to judge whether it support DMA mode or not, if doesn't config
it print out can't use DMA for each bus during
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