Currently, after determining the minimum value for the High period
(TCKH) the remainder of the internal clock pulses is set as the Low
period (TCKL). This causes the i2c clock duty cycle to be much less
than 50%.
Modify the starting position to TCKH and TCKL at 50% of the internal
clock, and
The code to read from the master read fifo, and write to the master
write fifo, checks a bit in an SCB register before every byte to
ensure that the fifo is not full (write fifo) or empty (read fifo).
Due to clock domain crossing inside the SCB block the updated value
of this bit is only visible
This commit adds support for the I2C_M_IGNORE_NAK protocol
modification.
Such behaviour can only be implemented in atomic mode. So, if a
transaction contains a message with such flag the drivers
switches to atomic mode. The implementation consists simply in
treating NAKs as ACKs.
Signed-off-by:
Move scb_wr_rd_fence to before reading from fifo and writing to
fifo to make sure the the first read/write is done after the required
number of cycles.
Fixes: commit 27bce457d588 (i2c: img-scb: Add Imagination Technologies I2C SCB
driver)
Signed-off-by: Sifan Naeem sifan.na...@imgtec.com
Remove start bit detected status after it is handled,
doing so will prevent this condition being hit for
every interrupt on a particular transfer.
Fixes: commit 27bce457d588 (i2c: img-scb: Add Imagination Technologies I2C SCB
driver)
Signed-off-by: Sifan Naeem sifan.na...@imgtec.com
Reviewed-by:
The following patches are required to enchance the existing driver to
support i2c on pistachio.
This patch series depends on the series of fixes posted earlier[1].
The features added in this series were tested with the earlier fixes
in place.
Tested on Pistachio bub and on tz1090 using an
Now that we are using the transaction halt interrupt to safely control
repeated start transfers, we no longer need to handle the fifo
emptying interrupts.
Handling this interrupt along with Transaction Halt interrupt can
cause erratic behaviour.
Signed-off-by: Sifan Naeem sifan.na...@imgtec.com
Stop Detected interrupt is triggered when a Stop bit is detected on
the bus, which indicates the end of the current transfer.
When the end of a transfer is indicated by the Stop Detected interrupt,
drain the FIFO and signal completion for the transaction. But if the
interrupt was triggered before
The following patches are required to fix the existing driver to
support i2c on pistachio.
Tested on Pistachio bub using an Adafruit I2C Non-Volatile FRAM Breakout
(256Kbit / 32KByte) eeprom.
Used i2c buildroot tools to test the eeprom and the other i2c blocks.
Also used dd commands to copy data
Based on i2c-mux-gpio driver, similarly the register-based mux
switch from one bus to another by setting a single register.
The register can be on PCIe bus, local bus, or any memory-mapped
address. The endianness of such register can be specified in device
tree if used, or in platform data.
70762ab from 11/2014 (i2c: Use stable dev_name for ACPI enumerated I2C
slaves) modified the sysfs-visible dev_name() for ACPI enumerated I2C
devices. With that change, /sys/bus/i2c/devices/i2c-0-004a, for
example, became /sys/bus/i2c/devices/i2c-PNP:xx
That causes problems for userspace code
Set an ACPI companion for I2C mux channels enumerated through ACPI and
ensure they are scanned for devices.
Signed-off-by: Dustin Byford dus...@cumulusnetworks.com
---
drivers/i2c/i2c-core.c | 10 ++
drivers/i2c/i2c-mux.c | 8
2 files changed, 18 insertions(+)
diff --git
(v2 corrects cc: list)
I would like to add support for scanning I2C devices connected to ACPI
OF compatible muxes described in ASL like this:
Device (MUX0)
{
Name (_ADR, 0x70)
Name (_HID, PRP0001)
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (0x70, ControllerInitiated,
On Wed, Aug 12, 2015 at 05:31:33PM +0300, Irina Tirdea wrote:
There are devices that need to handle block transactions
regardless of the capabilities exported by the adapter.
For performance reasons, they need to use i2c read blocks
if available, otherwise emulate the block transaction with
On Sat, Aug 08, 2015 at 10:33:17PM +0200, Wolfram Sang wrote:
Here is the updated RFC series ready for submission. This gives the i2c core
seperate address spaces for standard clients, 10 bit clients, and our own
slave
clients. So, you can now have a 7 bit slave at 0x50 and a 10 bit slave at
On Wed, Aug 12, 2015 at 05:31:34PM +0300, Irina Tirdea wrote:
For i2c busses that support only SMBUS extensions, the eeprom at24
driver reads data from the device using the SMBus block, word or byte
read protocols depending on availability.
Replace the block read emulation from the driver
Do I have to add myself to MAINTAINER file for this driver?
Do you want to maintain this driver?
I prefer not, if that is OK.
Not my most favourite answer, but yes, it is ok ;)
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On Sat, Jun 27, 2015 at 08:08:53PM -0400, David Kessler wrote:
The i2c-pnx driver implements the i2c specification incorrectly. The
specification allows for 'repeated start' transactions in which the i2c
master generates two start conditions without generating a stop condition in
between them.
On Thu, Aug 13, 2015 at 9:04 PM, Ian Lepore i...@freebsd.org wrote:
As the FreeBSD person who got our first SoC (imx6, only partially
supported) converted to use the Linux DT files rather than our own
homebrew mess we started with, I would say that my opinion of the
existing DT information is
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