On Tuesday 20 February 2007, Sergei Shtylyov wrote:
Hello.
Bartlomiej Zolnierkiewicz wrote:
The IDE core looks at the wrong bit when checking if the secondary channel
is
enabled on PCI0646 -- CFR bit 8 is read-ahead disable, bit 3 is the correct
one.
I guess that you meant CNTRL
Hello.
Bartlomiej Zolnierkiewicz wrote:
The IDE core looks at the wrong bit when checking if the secondary channel is
enabled on PCI0646 -- CFR bit 8 is read-ahead disable, bit 3 is the correct one.
I guess that you meant CNTRL here?
Yeah, and bit 7. :-
[ I corrected this in the
On Wednesday 14 February 2007 23:35, Sergei Shtylyov wrote:
The IDE core looks at the wrong bit when checking if the secondary channel is
enabled on PCI0646 -- CFR bit 8 is read-ahead disable, bit 3 is the correct
one.
I guess that you meant CNTRL here?
[ I corrected this in the applied
The IDE core looks at the wrong bit when checking if the secondary channel is
enabled on PCI0646 -- CFR bit 8 is read-ahead disable, bit 3 is the correct one.
Starting with PCI0646U chip, the primary channel can also be enbled/disabled --
so, add 'enablebits' initializers to each
