On Mon, Dec 17, 2012 at 12:06 PM, Chris Metcalf wrote:
> On 12/14/2012 11:34 PM, Simon Marchi wrote:
>> This is an implementation of user_regset for the tilegx architecture. It
>> reuses the basic blocks that were already there.
>
> Thanks, Simon! A couple of comments:
>
> I encourage you to
On Monday, December 17, 2012 10:08:52 AM H. Peter Anvin wrote:
> On 12/17/2012 01:28 AM, Borislav Petkov wrote:
> > Hi guys,
> >
> > this one sanitizes the Kconfig entry prompt so can we pick it up for
> > -rc1 or later, please?
>
> Hm... all these are actually cleanups or fixes for the stuff
On Mon, 17 Dec 2012, Greg KH wrote:
> You can't pick anything up for 3.9 until after 3.8-rc1 is out, according
> to the rules of linux-next
Well, you can accept a submission and store it in a private tree until
then. You just can't put it in any tree that feeds into linux-next.
Alan Stern
--
On Mon, 17 Dec 2012, Stephen Warren wrote:
> On 12/13/2012 11:59 PM, Venu Byravarasu wrote:
> > As Tegra USB host driver is using instance number for resetting
> > PORT0 twice, adding a new DT property for handling this.
>
> Alan, Greg, Felip,e
>
> This series looks fine to me.
>
> I'd like to
On 12/17/2012 02:58 PM, Mitch Bradley wrote:
> On 12/17/2012 11:36 AM, Stephen Warren wrote:
>> On 12/17/2012 05:10 AM, Laxman Dewangan wrote:
>>> Nvidia's Tegra has multiple uart controller which supports:
>>> - APB dma based controller fifo read/write.
>>> - End Of Data interrupt in incoming
On Mon, Dec 17, 2012 at 10:24:15AM -0800, Stephen Boyd wrote:
> On 12/04/12 02:10, Fabio Baltieri wrote:
> > static struct cpufreq_driver db8500_cpufreq_driver = {
> > - .flags = CPUFREQ_STICKY,
> > + .flags = CPUFREQ_STICKY | CPUFREQ_CONST_LOOPS,
>
> Wouldn't you want to fold this into
On Sun, Dec 16, 2012 at 7:29 PM, Michel Lespinasse wrote:
> On Sun, Dec 16, 2012 at 10:05 AM, Andy Lutomirski wrote:
>> On Sun, Dec 16, 2012 at 4:39 AM, Michel Lespinasse wrote:
>>> I think this could be done by extending the mlock work I did as part
>>> of v2.6.38-rc1. The commit message for
Em 17-12-2012 15:00, Borislav Petkov escreveu:
On Mon, Dec 17, 2012 at 07:35:44AM -0800, Joe Perches wrote:
Perhaps Cesar can use his script as a starting point to find those
pattern invalidating commits or maybe add the capability (or a
--strict check) to checkpatch.
Or that, I don't have a
On 12/17/2012 11:36 AM, Stephen Warren wrote:
> On 12/17/2012 05:10 AM, Laxman Dewangan wrote:
>> Nvidia's Tegra has multiple uart controller which supports:
>> - APB dma based controller fifo read/write.
>> - End Of Data interrupt in incoming data to know whether end
>> of frame achieve or not.
On 12/17/2012 08:36 PM, Russ Anderson wrote:
> The 3.7 kernel grinds to a halt on boot of a system with
> 2048 cpus. NMI showed most of the cpus in
> _raw_spin_lock in cpuidle_get_cpu_driver(). (backtrace below)
>
> A quick look at cpuidle_get_cpu_driver() shows the hot lock.
>
> In
On 12/17/2012 05:10 AM, Laxman Dewangan wrote:
> Nvidia's Tegra has multiple uart controller which supports:
> - APB dma based controller fifo read/write.
> - End Of Data interrupt in incoming data to know whether end
> of frame achieve or not.
> - Hw controlled RTS and CTS flow control to
On Mon, Dec 17, 2012 at 01:33:14PM -0800, Tejun Heo wrote:
> Hello,
>
> On Mon, Dec 17, 2012 at 04:27:36PM -0500, Vivek Goyal wrote:
> > What I do care about is atleast being able to read and understand the
> > code easily. Right now, it is hard to understand. I am still struggling
> > to wrap my
On 12/17/2012 05:08 AM, Laxman Dewangan wrote:
> Add OF_DEV_AUXDATA for high speed uart controller driver for
> Tegra20/Tegra30 board dt files.
> Set the parent clock of uart controller to PLLP.
> diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c
> b/arch/arm/mach-tegra/board-dt-tegra20.c
>
On Mon, Dec 17, 2012 at 08:56:27PM +, Seiji Aguchi wrote:
> Changelog v1 -> v2
> - Erase a logic checking the number of online cpus.
> - Create a patchset to fix deadlocking issue in both pstore filesystem and
>efi_pstore driver.
>- Introduce a function, is_non_blocking_path(), to
[ sorry, resend. My lbdb autocompleted with an extra r in kernel.org ]
Hi everyone,
My for-linus branch has a big set of fixes and features:
git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux-btrfs.git for-linus
This was against 3.7, and it has two easy conflicts against Linus'
current
On 12/17/2012 05:08 AM, Laxman Dewangan wrote:
> Add connection name "uart-clk" for the uart clock information.
Does the UART receive more than one clock, so that it actually cares
what the clock connection name is? If not, can we just drop this patch?
--
To unsubscribe from this list: send the
On 12/17/2012 05:08 AM, Laxman Dewangan wrote:
> Tegra20 uart clock source have the 15.1 clock divider in place of
That says Tegra20, but ...
> 7.1. Add support for 15.1 clock divider and change the uart clock divider
> flag to DIV_U151.
> arch/arm/mach-tegra/clock.h |3 +-
>
On Mon, Dec 17, 2012 at 09:20:57PM +0100, "Bernd Krumböck" wrote:
> > If you think it's useful for USB controller, just tell me or modify the
> > driver by yourself! As you see the patch is really easy.
>
> At least it is useful for the usb_8dev driver. I'll write a patch.
>
> Photo of the
Hi Dongjin,
On Tuesday 18 of December 2012 04:55:07 Dongjin Kim wrote:
> Adding the device node to support eMMC storage on SDCARD4 ports,
> controlled by Mobile Storage Host Controller.
>
> Signed-off-by: Dongjin Kim
> ---
> arch/arm/boot/dts/exynos4412-odroidx.dts | 21 +
w1_therm includes some obsolete code to detect bad_roms, this is no
longer relevant.
The retry code is only used for this bad_rom test, however there is a
CRC check that detects a bad read, but does not trigger a retry. This
patch removes all the bad_rom code and uses the CRC check to trigger
Monday, December 17, 2012, 10:12:40 PM, you wrote:
> On Mon, Dec 17, 2012 at 03:46:34PM -0500, Konrad Rzeszutek Wilk wrote:
>> On Mon, Dec 17, 2012 at 09:32:17PM +0100, Sander Eikelenboom wrote:
>> >
>> > Sunday, December 16, 2012, 6:38:24 PM, you wrote:
>> >
>> > > On Fri, Dec 14, 2012 at
On 12/17/2012 05:10 AM, Laxman Dewangan wrote:
> Nvidia's Tegra has multiple uart controller which supports:
> - APB dma based controller fifo read/write.
> - End Of Data interrupt in incoming data to know whether end
> of frame achieve or not.
> - Hw controlled RTS and CTS flow control to
On 17/12/12 20:47, Wolfgang Grandegger wrote:
> On 12/17/2012 07:02 PM, Roland Stigge wrote:
>> On 12/17/2012 06:37 PM, Wolfgang Grandegger wrote:
>>> /* Do synchronous data output with a single write access */
>>> __raw_writel(~mask, pio + PIO_OWDR);
>>> __raw_writel(mask, pio +
Hello,
On Mon, Dec 17, 2012 at 04:27:36PM -0500, Vivek Goyal wrote:
> What I do care about is atleast being able to read and understand the
> code easily. Right now, it is hard to understand. I am still struggling
> to wrap my head around it.
Hmm... I thought it was really simple. Maybe I'm
On 12/17/2012 10:10 AM, Grant Likely wrote:
> On Mon, 17 Dec 2012 17:40:49 +0530, Laxman Dewangan
> wrote:
>> Nvidia's Tegra has multiple uart controller which supports:
>> - APB dma based controller fifo read/write.
>> - End Of Data interrupt in incoming data to know whether end
>> of frame
On an (outdated) laptop the radeon driver (almost always) prints, during
the first resume of each session:
[drm] crtc 1 is connected to a TV
This message is a bit puzzling as, as far as I know, no TV has ever
been connected to this laptop. Anyhow, before v3.5, if that happened the
radeon
The purpose of this option is to allow ARM/etc systems that rely on the
class RTC subsystem to have the same kind of automatic NTP based
synchronization that we have on PC platforms. Today ARM does not
implement update_persistent_clock and makes extensive use of the class
RTC system.
When enabled
On 12/17/2012 08:24 AM, Rob Herring wrote:
> On 12/17/2012 06:10 AM, Laxman Dewangan wrote:
>> Nvidia's Tegra has multiple uart controller which supports:
>> - APB dma based controller fifo read/write.
>> - End Of Data interrupt in incoming data to know whether end
>> of frame achieve or not.
>>
On Mon, Dec 17, 2012 at 01:17:38PM -0800, Tejun Heo wrote:
> Hello,
>
> On Mon, Dec 17, 2012 at 03:53:18PM -0500, Vivek Goyal wrote:
> > On Fri, Dec 14, 2012 at 02:41:20PM -0800, Tejun Heo wrote:
> > > Currently, cfqg charges are scaled directly according to cfqg->weight.
> > > Regardless of the
On Mon, Dec 17, 2012 at 04:18:43PM -0500, Vivek Goyal wrote:
> > > I think confusion happens because we are overloading the definition of
> > > cfqg. It is competing with its siblings at the same time it is competing
> > > against its child groups (on behalf of its children tasks).
> >
> > While
On Mon, Dec 17, 2012 at 01:15:17PM -0800, Tejun Heo wrote:
> Hello, Vivek.
>
> On Mon, Dec 17, 2012 at 03:46:09PM -0500, Vivek Goyal wrote:
> > On Fri, Dec 14, 2012 at 02:41:19PM -0800, Tejun Heo wrote:
> > > To prepare for blkcg hierarchy support, add cfqg->nr_active and
> > > ->level_weight.
On Mon, Dec 17, 2012 at 02:07:59PM -0700, Stephen Warren wrote:
> On 12/13/2012 11:59 PM, Venu Byravarasu wrote:
> > As Tegra USB host driver is using instance number for resetting
> > PORT0 twice, adding a new DT property for handling this.
>
> Alan, Greg, Felip,e
>
> This series looks fine to
On 16 December 2012 16:29, Alan Stern wrote:
> On Sun, 16 Dec 2012, Rafael J. Wysocki wrote:
>
>> On Saturday, December 15, 2012 10:16:29 PM Jiri Kosina wrote:
>> > On Sat, 15 Dec 2012, Rafael J. Wysocki wrote:
>> >
>> > > From: Rafael J. Wysocki
>> > >
>> > > Currently, the PM core disables
Hello,
On Mon, Dec 17, 2012 at 03:53:18PM -0500, Vivek Goyal wrote:
> On Fri, Dec 14, 2012 at 02:41:20PM -0800, Tejun Heo wrote:
> > Currently, cfqg charges are scaled directly according to cfqg->weight.
> > Regardless of the number of active cfqgs or the amount of active
> > weights, a given
Hello, Vivek.
On Mon, Dec 17, 2012 at 03:46:09PM -0500, Vivek Goyal wrote:
> On Fri, Dec 14, 2012 at 02:41:19PM -0800, Tejun Heo wrote:
> > To prepare for blkcg hierarchy support, add cfqg->nr_active and
> > ->level_weight. cfqg->nr_active counts the number of active cfqgs at
> > the cfqg's
On 12/14/2012 12:02 PM, Corey Minyard wrote:
>On 12/14/2012 10:25 AM, Evans, Robert wrote:
>> Corey,
>>
>> Thanks for the thoughtful reply. Below I respond in detail to
>> these three points.
>>
>> 1) Why building a variant kernel with ipmi_si as a module is not
>> feasible.
>>
>> 2) User
On Mon, Dec 17, 2012 at 03:46:34PM -0500, Konrad Rzeszutek Wilk wrote:
> On Mon, Dec 17, 2012 at 09:32:17PM +0100, Sander Eikelenboom wrote:
> >
> > Sunday, December 16, 2012, 6:38:24 PM, you wrote:
> >
> > > On Fri, Dec 14, 2012 at 04:55:57PM +0100, Sander Eikelenboom wrote:
> > >> Hi Konrad,
>
On Mon, Dec 17, 2012 at 10:08:02PM +0100, Borislav Petkov wrote:
> On Mon, Dec 17, 2012 at 12:59:00PM -0800, Joe Perches wrote:
> > The new pr_emerg is effectively a termination of the
> > previous one. There's no need for 2 consecutive uses
> > of pr_emerg(HW_ERR ...) here.
>
> Actually, in
On Mon, Dec 17, 2012 at 12:59:00PM -0800, Joe Perches wrote:
> On Mon, 2012-12-17 at 14:43 -0600, Jacob Shin wrote:
> > On Mon, Dec 17, 2012 at 09:40:11PM +0100, Borislav Petkov wrote:
> > > On Mon, Dec 17, 2012 at 12:34:35PM -0800, Joe Perches wrote:
> > > > decode_mc2_mce does
> > > >
> > > >
Hi Linus,
Now that the core bits are in, here are the driver bits for 3.8. The
branch contains:
- A huge pile of drbd bits that were dumped from the 3.7 merge window.
Following that, it was both made perfectly clear that there is going to be
no more over-the-wall pulls and how the situation
On Mon, Dec 17, 2012 at 12:59:00PM -0800, Joe Perches wrote:
> The new pr_emerg is effectively a termination of the
> previous one. There's no need for 2 consecutive uses
> of pr_emerg(HW_ERR ...) here.
Actually, in decode_mc5_mce(), the second pr_emerg needs to stay like
what it is now.
So
On 12/13/2012 11:59 PM, Venu Byravarasu wrote:
> As Tegra USB host driver is using instance number for resetting
> PORT0 twice, adding a new DT property for handling this.
Alan, Greg, Felip,e
This series looks fine to me.
I'd like to take all the Tegra-related USB patches through the Tegra
tree
-Original Message-
From: devendra.aaru [mailto:devendra.a...@gmail.com]
Sent: Monday, December 17, 2012 1:39 PM
To: Justin Piszcz
Cc: linux-kernel@vger.kernel.org; net...@vger.kernel.org
Subject: Re: 3.6.10: Intel: ixgbe :01:00.0 eth4: Detected Tx Unit Hang
Ccing netdev
On Sat, Dec
fix these errors reported by checkpatch.pl
- drivers/i2c/busses/i2c-nforce2.c:191
- drivers/i2c/busses/i2c-nforce2.c:193
ERROR: "foo * bar" should be "foo *bar"
- drivers/i2c/busses/i2c-nforce2.c:302:
ERROR: "(foo*)" should be "(foo *)"
Signed-off-by: Laurent Navet
---
On Mon, 17 Dec 2012, Benoit Cousson wrote:
> It was done for legacy reason but should disappear once the modulemode
> will be be removed from the clock nodes.
Here's a start at taking care of the low-hanging fruit:
http://marc.info/?l=linux-omap=135577685007813=2
Only lightly tested, so tests
Reduce lines of code and simplify this driver by using the
generic clock binding parsing function.
Signed-off-by: Stephen Boyd
Cc: Tony Prisk
---
drivers/clk/clk-vt8500.c | 39 +++
1 file changed, 15 insertions(+), 24 deletions(-)
diff --git
Consolidate DT parsing for the common bits of a clock binding in
one place to simplify clock drivers. This also has the added
benefit of standardizing how the clock names used by the common
clock framework are generated from the DT bindings. We always use
the first clock-output-names string if it
I see the same pattern repeated a few times to parse the common clock
bindings for a particular clock. Instead of wrting this code another
time, let's consolidate the logic in one place and standardize how
clocks will be named from their bindings.
After this series there are no more users of
Reduce lines of code and simplify this driver by using the
generic clock binding parsing function.
Signed-off-by: Stephen Boyd
Cc: Rob Herring
---
drivers/clk/clk-highbank.c | 21 -
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/clk-highbank.c
Reduce lines of code and simplify this driver by using the
generic clock binding parsing function. This also fixes a bug
where the 'flags' member of the init struct is not initialized.
Signed-off-by: Stephen Boyd
Cc: Josh Cartwright
Cc: Soren Brinkmann
---
drivers/clk/clk-zynq.c | 28
Andy Lutomirski writes:
> On Fri, Dec 14, 2012 at 2:01 PM, Eric W. Biederman
> wrote:
>>
>> These are fixes from Andys review of my user namespace tree.
>>
>> The first two patches are critical must fix fixes.
>>
>> The third patch fixing commit_creds is a nice to have but fixing it
>> would be
Wang, All,
On Monday 17 December 2012 Wang YanQing wrote:
> Now we have Load/Save buttons to do the Load/Save
> in the convenient place, so we can drop the
> top-level entries.
>
> Signed-off-by: Wang YanQing
Reviewed-by: "Yann E. MORIN"
Tested-by: "Yann E. MORIN"
Regards,
Yann E. MORIN.
On Mon, 17 Dec 2012 14:34:15 +1100
Stephen Rothwell wrote:
> Hi all,
>
> On Mon, 17 Dec 2012 14:22:38 +1100 Stephen Rothwell
> wrote:
> >
> > After merging the final tree, today's linux-next build (powerpc allnoconfig)
> > produced this warning:
> >
> > warning: (PPC) selects SPARSE_IRQ
On Mon, 2012-12-17 at 14:43 -0600, Jacob Shin wrote:
> On Mon, Dec 17, 2012 at 09:40:11PM +0100, Borislav Petkov wrote:
> > On Mon, Dec 17, 2012 at 12:34:35PM -0800, Joe Perches wrote:
> > > decode_mc2_mce does
> > >
> > > pr_emerg(HW_ERR "MC2 Error: ");
> > > calls
> > > fam_ops->mc2_mce()
>
[Issue]
There is a scenario which efi_pstore may hang up:
- cpuA grabs efivars->lock
- cpuB panics and calls smp_send_stop
- smp_send_stop sends IRQ to cpuA
- after 1 second, cpuB gives up on cpuA and sends an NMI instead
- cpuA is now in an NMI handler while still holding efivars->lock
-
[Issue]
When pstore is in panic and emergency-restart paths, it may be blocked
in those paths because it simply takes spin_lock.
This is an example scenario which pstore may hang up in a panic path:
- cpuA grabs psinfo->buf_lock
- cpuB panics and calls smp_send_stop
- smp_send_stop sends IRQ
Changelog v1 -> v2
- Erase a logic checking the number of online cpus.
- Create a patchset to fix deadlocking issue in both pstore filesystem and
efi_pstore driver.
- Introduce a function, is_non_blocking_path(), to check if pstore
is in panic and emergency-restart paths (PATCH 1/2)
On 12/16/2012 09:37 AM, Terje Bergström wrote:
...
> ... Sure we could tell DC to ask its parent
> (host1x), and call host1x driver with platform_device pointer found that
> way, and host1x would return a pointer to tegradrm's data. Hanging the
> data onto host1x driver is just a more complicated
On Fri, Dec 14, 2012 at 02:41:20PM -0800, Tejun Heo wrote:
> Currently, cfqg charges are scaled directly according to cfqg->weight.
> Regardless of the number of active cfqgs or the amount of active
> weights, a given weight value always scales charge the same way. This
> works fine as long as
Hi
On Mon, 17 Dec 2012, Ivan Khoronzhuk wrote:
> In the map for reset sources register we use defines intended for
> using with PRM_RSTCTRL register. So fix it.
your changes look good, but they are missing Signed-off-by: lines. Could
you please either resend with those, or confirm that you
On Mon, 17 Dec 2012 11:49:17 +
Mel Gorman wrote:
> The kbuild test robot reported the following after the merge of Automatic
> NUMA Balancing when cross-compiling for avr32.
>
> mm/memory.c: In function 'do_pmd_numa_page':
> mm/memory.c:3593: warning: no return statement in function
On Mon, Dec 17, 2012 at 09:32:17PM +0100, Sander Eikelenboom wrote:
>
> Sunday, December 16, 2012, 6:38:24 PM, you wrote:
>
> > On Fri, Dec 14, 2012 at 04:55:57PM +0100, Sander Eikelenboom wrote:
> >> Hi Konrad,
> >>
> >> I just tried to boot a 3.8.0-rc0 kernel (last commit:
> >>
On Fri, Dec 14, 2012 at 02:41:19PM -0800, Tejun Heo wrote:
> To prepare for blkcg hierarchy support, add cfqg->nr_active and
> ->level_weight. cfqg->nr_active counts the number of active cfqgs at
> the cfqg's level and ->level_weight is sum of weights of those cfqgs.
> The level covers itself
On Mon, Dec 17, 2012 at 09:40:11PM +0100, Borislav Petkov wrote:
> On Mon, Dec 17, 2012 at 12:34:35PM -0800, Joe Perches wrote:
> > decode_mc2_mce does
> >
> > pr_emerg(HW_ERR "MC2 Error: ");
> > calls
> > fam_ops->mc2_mce()
> > which may not emit anything
> > and if it doesn't, does
> >
On Mon, Dec 17, 2012 at 12:34:35PM -0800, Joe Perches wrote:
> decode_mc2_mce does
>
> pr_emerg(HW_ERR "MC2 Error: ");
> calls
> fam_ops->mc2_mce()
> which may not emit anything
> and if it doesn't, does
> pr_emerg(HW_ERR "Corrupted ...");
> on another line leaving a trailing
In the map for reset sources register we use defines intended for
using with PRM_RSTCTRL register. So fix it.
---
arch/arm/mach-omap2/prm44xx.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index
Wang, All,
On Monday 17 December 2012 Wang YanQing wrote:
> If menuconfig have Save/Load button like alternative
> .config editors, xconfig, nconfig, etc.We will have
> a obvious benefit when use menuconfig just like
> when we use others, we can Save/Load our .config quickly
> and conveniently.
>
On Mon, 2012-12-17 at 21:22 +0100, Borislav Petkov wrote:
> On Mon, Dec 17, 2012 at 12:16:16PM -0800, Joe Perches wrote:
> > You also have paths where you start a pr_emerg and do not terminate it
> > when there is no apparent error at all.
>
> For example?
>
decode_mc2_mce does
Sunday, December 16, 2012, 6:38:24 PM, you wrote:
> On Fri, Dec 14, 2012 at 04:55:57PM +0100, Sander Eikelenboom wrote:
>> Hi Konrad,
>>
>> I just tried to boot a 3.8.0-rc0 kernel (last commit:
>> 7313264b899bbf3988841296265a6e0e8a7b6521) as dom0 on my machine with current
>> xen-unstable.
>
On Mon, Dec 17, 2012 at 12:16:16PM -0800, Joe Perches wrote:
> You also have paths where you start a pr_emerg and do not terminate it
> when there is no apparent error at all.
For example?
--
Regards/Gruss,
Boris.
Sent from a fat crate under my desk. Formatting is fine.
--
--
To
> Hi Bernd,
>
> On Mon, Dec 17, 2012 at 08:28:48AM +0100, Bernd Krumboeck wrote:
>> Why there is no patch for any usb can device?
>
> Because USB canbus interfaces usually already has some dedicated
> activity LED on the device itself, while this patch is meant to give an
> equivalent
On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote:
> hi
> When develop the clk drivers for SOCs based on common clock framework.
> I met a issue.
> For example there is a uart device, it's function clock comes from a
> divider, and the divider's parent is a mux. It means
>
> MUX --> DIV
On Mon, 2012-12-17 at 21:05 +0100, Borislav Petkov wrote:
> On Mon, Dec 17, 2012 at 11:57:01AM -0800, Joe Perches wrote:
> > It'd be better to change the pr_cont uses to pr_emerg
> >
> > []
> >
> > > +static void decode_mc2_mce(struct mce *m)
> > > +{
> > > + u16 ec = EC(m->status);
> > > + u8
On Mon 17-12-12 13:12:33, Johannes Weiner wrote:
> A swappiness of 0 has a slightly different meaning for global reclaim
> (may swap if file cache really low) and memory cgroup reclaim (never
> swap, ever).
>
> In addition, global reclaim at highest priority will scan all LRU
> lists equal to
On Mon, Dec 17, 2012 at 11:57:01AM -0800, Joe Perches wrote:
> It'd be better to change the pr_cont uses to pr_emerg
>
> []
>
> > +static void decode_mc2_mce(struct mce *m)
> > +{
> > + u16 ec = EC(m->status);
> > + u8 xec = XEC(m->status, xec_mask);
> > +
> > + pr_emerg(HW_ERR "MC2 Error:
On Fri, Dec 14, 2012 at 02:41:17PM -0800, Tejun Heo wrote:
> Currently a child blkg (blkcg_gq) can be created even if its parent
> doesn't exist. ie. Given a blkg, it's not guaranteed that its
> ancestors will exist. This makes it difficult to implement proper
> hierarchy support for blkcg
On Mon 17-12-12 12:54:15, Johannes Weiner wrote:
> On Mon, Dec 17, 2012 at 05:37:35PM +0100, Michal Hocko wrote:
> > On Fri 14-12-12 19:18:51, Johannes Weiner wrote:
> > > On Fri, Dec 14, 2012 at 05:13:45PM +0100, Michal Hocko wrote:
> > > > On Fri 14-12-12 10:43:55, Rik van Riel wrote:
> > > > >
On Mon, 2012-12-17 at 13:39 -0600, Jacob Shin wrote:
> Currently only AMD Family 15h processors have special handling for MC2
> errors, since upcoming Family 16h will also need unique handling,
> let's make MC2 handling part of amd_decoder_ops.
[]
> diff --git a/drivers/edac/mce_amd.c
Adding the device node to support eMMC storage on SDCARD4 ports, controlled by
Mobile Storage Host Controller.
Signed-off-by: Dongjin Kim
---
arch/arm/boot/dts/exynos4412-odroidx.dts | 21 +
1 file changed, 21 insertions(+)
diff --git
This patch adds the node to support fixed voltage for peripherals like LED,
ethernet controller.
Signed-off-by: Dongjin Kim
---
arch/arm/boot/dts/exynos4412-odroidx.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
This patch adds GPIO connected LEDS on ODROID-X board, and describe its
properties.
Signed-off-by: Dongjin Kim
---
arch/arm/boot/dts/exynos4412-odroidx.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
Add initial dtb file for Hardkernel's ODROID-X board based on EXYNOS4412 SoC.
Signed-off-by: Dongjin Kim
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/exynos4412-odroidx.dts | 52 ++
2 files changed, 53 insertions(+)
create mode 100644
On Mon 17-12-12 19:23:01, azurIt wrote:
> >[Ohh, I am really an idiot. I screwed the first patch]
> >- bool oom = true;
> >+ bool oom = !(gfp_mask | GFP_MEMCG_NO_OOM);
> >
> >Which obviously doesn't work. It should read !(gfp_mask _MEMCG_NO_OOM).
> > No idea how I could have missed
To read reset sources registers we have to use PRM_DEVICE_INST
---
arch/arm/mach-omap2/prm44xx.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 7498bc7..0b61b8d 100644
--- a/arch/arm/mach-omap2/prm44xx.c
According to TRMs the assigned shifts are wrong, so correct them.
---
arch/arm/mach-omap2/prm44xx.h |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 22b0979..8ee1fbd 100644
---
On 12/17/2012 07:02 PM, Roland Stigge wrote:
> On 12/17/2012 06:37 PM, Wolfgang Grandegger wrote:
>> /* Do synchronous data output with a single write access */
>> __raw_writel(~mask, pio + PIO_OWDR);
>> __raw_writel(mask, pio + PIO_OWER);
>> __raw_writel(val, pio + PIO_ODSR);
On Sat, Dec 15, 2012 at 06:34:37AM -0500, Nickolai Zeldovich wrote:
> The kvm i8254 emulation for counter 0 (but not for counters 1 and 2)
> has at least two bugs in mode 0:
>
> 1. The OUT bit, computed by pit_get_out(), is never set high.
>
> 2. The counter value, computed by pit_get_count(),
On Mon, 17 Dec 2012, Mike Galbraith wrote:
> On Mon, 2012-12-17 at 16:35 +0100, Thomas Gleixner wrote:
> > Bah. This reverse user/kernel priority nonsense really should go away!
>
> Snort, I looked right at it too, looked perfectly fine :)
The real bad news is, that I talked to someone about
According to TRMs the assigned shifts are wrong, so correct them.
---
arch/arm/mach-omap2/prm44xx.h |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 22b0979..8ee1fbd 100644
---
Add MCE decoding logic for AMD Family 16h processors.
Signed-off-by: Jacob Shin
---
drivers/edac/mce_amd.c | 120 ++--
drivers/edac/mce_amd.h |6 +++
2 files changed, 122 insertions(+), 4 deletions(-)
diff --git a/drivers/edac/mce_amd.c
Currently only AMD Family 15h processors have special handling for MC2
errors, since upcoming Family 16h will also need unique handling,
let's make MC2 handling part of amd_decoder_ops.
Signed-off-by: Jacob Shin
---
drivers/edac/mce_amd.c | 58 ++--
On Mon, Dec 17, 2012 at 11:28 AM, Jens Axboe wrote:
> On 2012-12-17 20:27, Linus Torvalds wrote:
>> On Mon, Dec 17, 2012 at 11:06 AM, Jens Axboe wrote:
>>>
>>> Sigh, in that case, yes lets just revert it.
>>
>> So just to check - we're talking about commit 8fa72d234da9 ("bdi: add
>> a
On Fri, Dec 14, 2012 at 02:41:16PM -0800, Tejun Heo wrote:
> * Rename out_* labels to err_*.
>
> * Do ERR_PTR() conversion once in the error return path.
>
> This patch is cosmetic and to prepare for the hierarchy support.
>
> Signed-off-by: Tejun Heo
Acked-by: Vivek Goyal
Vivek
> ---
>
diff --git a/Makefile b/Makefile
index 540f7b2..fbf84a4 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
VERSION = 3
PATCHLEVEL = 7
-SUBLEVEL = 0
+SUBLEVEL = 1
EXTRAVERSION =
NAME = Terrified Chipmunk
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 1460a5d..e28670f
I'm announcing the release of the 3.7.1 kernel.
All users of the 3.7 kernel series must upgrade.
The updated 3.7.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
linux-3.7.y
and can be browsed at the normal kernel.org git web browser:
I'm announcing the release of the 3.6.11 kernel.
Note, this is the LAST kernel in the 3.6.y series, it is now
end-of-life. Please move to the 3.7.y kernel series at this time.
The updated 3.6.y git tree can be found at:
The 3.7 kernel grinds to a halt on boot of a system with
2048 cpus. NMI showed most of the cpus in
_raw_spin_lock in cpuidle_get_cpu_driver(). (backtrace below)
A quick look at cpuidle_get_cpu_driver() shows the hot lock.
In drivers/cpuidle/driver.c:
diff --git a/Makefile b/Makefile
index bf1df55..a3e12e6 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
VERSION = 3
PATCHLEVEL = 4
-SUBLEVEL = 23
+SUBLEVEL = 24
EXTRAVERSION =
NAME = Saber-toothed Squirrel
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index
I'm announcing the release of the 3.4.24 kernel.
All users of the 3.4 kernel series must upgrade.
The updated 3.4.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
linux-3.4.y
and can be browsed at the normal kernel.org git web browser:
diff --git a/Makefile b/Makefile
index b639af3..cc6805f 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
VERSION = 3
PATCHLEVEL = 0
-SUBLEVEL = 56
+SUBLEVEL = 57
EXTRAVERSION =
NAME = Sneaky Weasel
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index
201 - 300 of 1206 matches
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