On Fri, Feb 28, 2014 at 10:29:32AM +, Morten Rasmussen wrote:
If I understand your proposal correctly, you are proposing to have a
pluggable scheduler where it is possible to have many different
load-balance (bottom half) implementations.
Yeah, that's not _ever_ going to happen. We've had
On Wed, Feb 26, 2014 at 03:13:33PM -0500, Johannes Weiner wrote:
On Wed, Feb 26, 2014 at 12:12:06PM -0500, Johannes Weiner wrote:
On Wed, Feb 26, 2014 at 09:54:22AM +, Mel Gorman wrote:
How about special casing the (alloc_flags ALLOC_WMARK_LOW) check in
get_page_from_freelist to also
The sdio func device is added to the driver model after the card
device.
This means the sdio func device will be suspend before the card device
and thus resumed after. The consequence are the mmc core don't
explicity need to protect itself from receiving sdio requests in
suspended state. Instead
On Thu, 2014-02-27 at 14:34 -0800, Dave Hansen wrote:
The question is really whether or not we ever access the mapping that we
faulted around, though. If we never access it, then the cost (however
small it was) is a loss. That's the mechanism that I'd expect causes
Kirill's numbers to go
On 27/02/14 18:23, Alex Thorlton wrote:
As Christian pointed out, the recent 'Revert thp: make MADV_HUGEPAGE
check for mm-def_flags' breaks qemu, it does QEMU_MADV_HUGEPAGE for
all kvm pages but this doesn't work after s390_enable_sie/thp_split_mm.
Paolo suggested that instead of failing on
This patch series addresses two issues with global clock updates.
The first fixes a bug found on hosts that have a tsc marked as
unstable. As global clock updates get triggered on every vcpu load
in these cases, guests with a large number of vcpus have their
progress nearly halted. The fix for
commit 0061d53daf26f introduced a mechanism to execute a global clock
update for a vm. We can apply this periodically in order to propagate
host NTP corrections. Also, if all vcpus of a vm are pinned, then
without an additional trigger, no guest NTP corrections can propagate
either, as the current
When we update a vcpu's local clock it may pick up an NTP correction.
We can't wait an indeterminate amount of time for other vcpus to pick
up that correction, so commit 0061d53daf26f introduced a global clock
update. However, we can't request a global clock update on every vcpu
load either (which
Why is this sent to fbdev list? Is this related to the hyperv-fb patches?
Yes, the hyperv-fb patches depend on this one.
Greg has picked it up meanwhile, that's why v4 + v5 of the patch series
don't include it any more.
cheers,
Gerd
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From: Pratyush Anand pratyush.an...@st.com
SPEAr1310/40 uses miphy for PCIe and SATA phy. This driver adds
support for the same.
AHCI phy hookups from arch specific code has been cleaned up.
Signed-off-by: Pratyush Anand pratyush.an...@st.com
Tested-by: Mohit Kumar mohit.ku...@st.com
Cc: Arnd
On Fri, Feb 28, 2014 at 12:44:59PM +0100, Peter Zijlstra wrote:
On Fri, Feb 28, 2014 at 10:29:32AM +, Morten Rasmussen wrote:
If I understand your proposal correctly, you are proposing to have a
pluggable scheduler where it is possible to have many different
load-balance (bottom half)
On Friday, February 28, 2014 at 12:36:01 PM, Yao Yuan wrote:
Hi Marek,
On Friday, February 28, 2014 at 06:19:18 AM, Yao Yuan wrote:
[...]
@@ -213,6 +238,7 @@ static struct imx_i2c_hwdata vf610_i2c_hwdata
= {
.ndivs =
On Friday, February 28, 2014 at 11:59:25 AM, Lothar Waßmann wrote:
Hi,
Marek Vasut wrote:
On Friday, February 28, 2014 at 06:19:18 AM, Yao Yuan wrote:
[...]
Yes, here have two dma channels, one for RX and the other one for TX.
When we request the channel we should determine it
Hi Paul,
I have a question regarding two lines of code in the functions
__update_cfs_rq_tg_load_contrib and __update_tg_runnable_avg. AFAICS
these functions update a load-tracking signal for the local RQ and an
aggregated signal in the TG for all RQs that belong to this TG. The
update is
On 02/25/2014 01:38 PM, Daniel Lezcano wrote:
In order to allow better integration between the cpuidle framework and the
scheduler, reducing the distance between these two sub-components will
facilitate this integration by moving part of the cpuidle code in the idle
task file and, because
On Thu, Feb 27, 2014 at 05:28:24AM +, Davidlohr Bueso wrote:
On Fri, 2014-02-21 at 17:22 +, Will Deacon wrote:
The asm-generic rwsem implementation directly acceses sem-cnt when
performing a __down_read_trylock operation. Whilst this is probably safe
on all architectures, we should
B2120 HDK is the reference board for STiH407 SoC.
It has the following characteristics:
- 1GB DDR3
- 8GB eMMC / SD-Card slot
- 32MB NOR Flash
- 1 x Gbit Ethernet
- 1 x USB 3.0 port
- 1 x Mini-PCIe
- 1 x SATA
- 1 x HDMI output
- 1 x HDMI input
- 1 x SPDIF
This patch only introduces basic
From: Giuseppe Cavallaro peppe.cavall...@st.com
This patch adds a new logic inside the st pinctrl to manage
an unsupported scenario: some sysconfig are not available!
This is the case of STiH407 where, although documented, the
following registers from SYSCFG_FLASH have been removed from the SoC.
This series adds basic support to the STMicroelectronics STiH407 SoC and its
B2120 reference board. The STiH407 is a dual-core ARM Cortex-A9 CPU aimed at
STB market.
Giuseppe Cavallaro (2):
ARM: STi: add pinctrl support for the STiH407 SoC
pinctrl: st: Enhance the controller to manage
From: Giuseppe Cavallaro peppe.cavall...@st.com
This patch adds the initial support for pinctrl based on H407 SoC.
Signed-off-by: Maxime Coquelin maxime.coque...@st.com
Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com
---
drivers/pinctrl/pinctrl-st.c | 4
1 file changed, 4
The STiH407 is advanced multi-HD AVC processor with 3D graphics acceleration
and 1.5-GHz ARM Cortex-A9 SMP CPU.
Signed-off-by: Maxime Coquelin maxime.coque...@st.com
Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com
---
arch/arm/boot/dts/stih407-clock.dtsi | 41 +++
This patch adds support to STiH407 SoC.
Signed-off-by: Maxime Coquelin maxime.coque...@st.com
Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com
---
Documentation/arm/sti/stih407-overview.txt| 18 ++
Documentation/devicetree/bindings/arm/sti.txt | 15 +++
On Wed, Dec 04, 2013 at 08:46:27AM -0800, Christoph Hellwig wrote:
While doing my recent work on the generic smp function calls I noticed
that smp_call_function_single without the wait flag can't work, as
it allocates struct call_single_data on stack, and without the wait
flag will happily
On Fri, Feb 28, 2014 at 12:04:19PM +, Matthew Leach wrote:
Hi Paul,
I have a question regarding two lines of code in the functions
__update_cfs_rq_tg_load_contrib and __update_tg_runnable_avg. AFAICS
these functions update a load-tracking signal for the local RQ and an
aggregated signal
On Fri, 2014-02-28 at 08:26 +0100, Yegor Yefremov wrote:
On Tue, Jul 30, 2013 at 3:04 PM, Luciano Coelho coe...@ti.com wrote:
Hi,
This patch series adds device tree support to the wlcore_sdio driver,
which is used by WiLink6, WiLink7 and WiLink8.
The first patches do some clean-up to
On Fri, Feb 28, 2014 at 01:26:24PM +0100, Peter Zijlstra wrote:
On Wed, Dec 04, 2013 at 08:46:27AM -0800, Christoph Hellwig wrote:
kernel/stop_machine.c:stop_two_cpus()
That site should work with .wait=1 just fine, but given the above, the
.wait=0 doesn't appear problematic at all.
Hi Marc,
-Original Message-
From: Marc Kleine-Budde [mailto:m...@pengutronix.de]
Sent: Friday, February 28, 2014 2:02 PM
To: Appana Durga Kedareswara Rao; w...@grandegger.com; Michal Simek;
grant.lik...@linaro.org; robh...@kernel.org; linux-...@vger.kernel.org
Cc:
On 02/28/2014 07:49 PM, Ulf Hansson wrote:
The sdio func device is added to the driver model after the card
device.
This means the sdio func device will be suspend before the card device
and thus resumed after. The consequence are the mmc core don't
explicity need to protect itself from
Daniel; can you rebase these patches on top of tip/master.
Ingo is going to create tip/sched/idle := tip/sched/core +
tip/timer/core and then we can stick these patches in there.
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On 02/28/2014 01:44 PM, Appana Durga Kedareswara Rao wrote:
Hi Marc,
-Original Message-
From: Marc Kleine-Budde [mailto:m...@pengutronix.de]
Sent: Friday, February 28, 2014 2:02 PM
To: Appana Durga Kedareswara Rao; w...@grandegger.com; Michal Simek;
grant.lik...@linaro.org;
On Thu, Feb 27, 2014 at 2:11 PM, Josh Boyer jwbo...@fedoraproject.org wrote:
On Thu, Feb 27, 2014 at 2:07 PM, Greg KH gre...@linuxfoundation.org wrote:
On Thu, Feb 27, 2014 at 01:04:34PM -0500, Josh Boyer wrote:
On Wed, Feb 26, 2014 at 3:11 PM, Matthew Garrett
matthew.garr...@nebula.com wrote:
On Thu, Feb 27, 2014 at 08:22:12PM +, Arnd Bergmann wrote:
On Thursday 27 February 2014 13:07:29 Jason Gunthorpe wrote:
On Thu, Feb 27, 2014 at 08:48:08PM +0100, Arnd Bergmann wrote:
It also looks correct for architectures that use the CPU MMIO address
as the IO address directly
This patch fixes the error returned to the i2c_transfer function
to -EAGAIN in case of arbitratin lost, so that the retry mechanism
can be used.
Signed-off-by: Maxime Coquelin maxime.coque...@st.com
---
drivers/i2c/busses/i2c-st.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
This is v3 of my attempt to add support for a generic pci_host_bridge
controller created
from a description passed in the device tree.
Changes from v2:
- Use range-cpu_addr when calling pci_address_to_pio()
- Introduce pci_register_io_range() helper function in order to register
io
Hi,
This patch adds support for PCI to AArch64. It is based on my v3 patch
that adds support for creating generic host bridge structure from
device tree. With that in place, I was able to boot a platform that
has PCIe host bridge support and use a PCIe network card.
Changes from v2:
-
Hi Marc,
-Original Message-
From: Marc Kleine-Budde [mailto:m...@pengutronix.de]
Sent: Friday, February 28, 2014 6:27 PM
To: Appana Durga Kedareswara Rao; w...@grandegger.com; Michal Simek;
grant.lik...@linaro.org; robh...@kernel.org; linux-...@vger.kernel.org
Cc:
The ranges property for a host bridge controller in DT describes
the mapping between the PCI bus address and the CPU physical address.
The resources framework however expects that the IO resources start
at a pseudo port address 0 (zero) and have a maximum size of IO_SPACE_LIMIT.
The conversion
Some architectures do not share x86 simple view of the I/O space and
instead use a range of addresses that map to external devices. For PCI,
these ranges can be expressed by OF bindings in a device tree file.
Introduce a pci_register_io_range() helper function that can be used
by the architecture
Make it easier to discover the domain number of a bus by storing
the number in pci_host_bridge for the root bus. Several architectures
have their own way of storing this information, so it makes sense
to try to unify the code. While at this, add a new function that
creates a root bus in a given
Hi Alexei,
[also cc'ing Hagen and Jesse]
Just some minor comments below ... let me know what you think.
On 02/27/2014 03:38 AM, Alexei Starovoitov wrote:
Extended BPF (or 64-bit BPF) is an instruction set to
create safe dynamically loadable filters that can call fixed set
of kernel functions
Before commit 7b5436635800 the pci_host_bridge was created before the root bus.
As that commit has added a needless dependency on the bus for
pci_alloc_host_bridge()
the creation order has been changed for no good reason. Revert the order of
creation as we are going to depend on the
The inline version of ioport_map() that gets used when !CONFIG_GENERIC_IOMAP
is wrong. It returns a mapped (i.e. virtual) address that can start from
zero and completely ignores the PCI_IOBASE and IO_SPACE_LIMIT that most
architectures that use !CONFIG_GENERIC_MAP define.
Signed-off-by: Liviu
On 02/28/2014 02:07 PM, Appana Durga Kedareswara Rao wrote:
What happens if the interrupt handler is delayed? For example in a RT
enabled system the interrupt handler runs as a thread. There might be
other threads with higher priority. The hardware will probably send
all CAN frames in the
Hi, Ralf,
Could these two patches be merged in 3.14 (there is an updated
version: http://patchwork.linux-mips.org/patch/6550/ and
http://patchwork.linux-mips.org/patch/6551/)?
And by the way, is the V19 of Loongson-3's patchset good enough to be
merged in 3.15?
Huacai
On Tue, Feb 25, 2014 at
Use the generic host bridge functions to provide support for
PCI Express on arm64. There is no support for ISA memory.
Signed-off-by: Liviu Dudau liviu.du...@arm.com
create mode 100644 arch/arm64/include/asm/pci.h
create mode 100644 arch/arm64/kernel/pci.c
diff --git a/arch/arm64/Kconfig
From: Catalin Marinas catalin.mari...@arm.com
The patch moves the PCI I/O space (currently at 64K) before the
earlyprintk mapping and extends it to 16MB.
Signed-off-by: Catalin Marinas catalin.mari...@arm.com
diff --git a/Documentation/arm64/memory.txt b/Documentation/arm64/memory.txt
index
Set the time needed for updating alarm and time registers to 0.45 ms.
The default is 7.32 ms which is too long and leads to warnings when
setting alarm or time:
s5m-rtc: waiting for UDR update, reached max number of retries
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
On Tue, Feb 25, 2014 at 01:14:17PM +0530, Rashika Kheria wrote:
Move prototype declaration of function to header file
include/linux/swiotlb.h from arch/ia64/hp/common/hwsw_iommu.c,
arch/ia64/hp/common/sba_iommu.c and arch/x86/pci/sta2x11-fixup.c because
it is used by more than one file.
On 02/28/2014 02:27 PM, Appana Durga Kedareswara Rao wrote:
-Original Message-
From: Marc Kleine-Budde [mailto:m...@pengutronix.de]
Sent: Friday, February 28, 2014 6:45 PM
To: Appana Durga Kedareswara Rao; w...@grandegger.com; Michal Simek;
grant.lik...@linaro.org;
3.10.32-rt31-rc1 stable review patch.
If anyone has any objections, please let me know.
--
From: Sebastian Andrzej Siewior bige...@linutronix.de
as it triggers:
|CPU: 0 PID: 0 Comm: swapper Not tainted 3.12.8-rt10 #141
|[c0014aa4] (unwind_backtrace+0x0/0xf8) from [c0012788]
Dear RT Folks,
This is the RT stable review cycle of patch 3.10.32-rt31-rc1.
Please scream at me if I messed something up. Please test the patches too.
The -rc release will be uploaded to kernel.org and will be deleted when
the final release is out. This is just a review release (or release
Several platforms use a rather generic version of parsing
the device tree to find the host bridge ranges. Move the common code
into the generic PCI code and use it to create a pci_host_bridge
structure that can be used by arch code.
Based on early attempts by Andrew Murray to unify the code.
Used
3.10.32-rt31-rc1 stable review patch.
If anyone has any objections, please let me know.
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From: Sebastian Andrzej Siewior bige...@linutronix.de
where do I start. Let me explain what is going on here. The code
sequence
| pushf
| pop%edx
| or $0x1,%dh
| push %edx
| mov
On Thu 2014-02-27 17:13:53, Rashika Kheria wrote:
Move prototype declaration of function to header file
kernel/power/power.h
because it is used by more than one file.
This eliminates the following warning in kernel/power/snapshot.c:
kernel/power/snapshot.c:1588:16: warning: no previous
On Fri, 28 Feb 2014 12:11:11 +0100
Peter Zijlstra pet...@infradead.org wrote:
On Thu, Feb 27, 2014 at 09:57:26PM -0500, Steven Rostedt wrote:
@@ -512,8 +508,21 @@ static inline void nmi_nesting_postprocess(void)
dotraplinkage notrace __kprobes void
do_nmi(struct pt_regs *regs, long
3.10.32-rt31-rc1 stable review patch.
If anyone has any objections, please let me know.
--
From: Sebastian Andrzej Siewior bige...@linutronix.de
Mostly unwind is done with irqs enabled however SLUB may call it with
irqs disabled while creating a new SLUB cache.
I had system
3.10.32-rt31-rc1 stable review patch.
If anyone has any objections, please let me know.
--
From: Sebastian Andrzej Siewior bige...@linutronix.de
Since we replaced msleep() by hrtimer I see now and then (rarely) this:
| [] Waiting for /dev to be fully populated...
|
3.10.32-rt31-rc1 stable review patch.
If anyone has any objections, please let me know.
--
From: Steven Rostedt rost...@goodmis.org
[ Talking with Sebastian on IRC, it seems that doing the irq_work_run()
from the interrupt in -rt is a bad thing. Here we simply raise the
From: Geert Uytterhoeven geert+rene...@linux-m68k.org
If the serial port being removed is used as a console, it must also be
unregistered from the console subsystem using unregister_console().
uart_ops.release_port() will release resources (e.g. iounmap() the serial
port registers), causing a
From: Geert Uytterhoeven geert+rene...@linux-m68k.org
If cpufreq_register_notifier() fails, we have to remove the port added by
sci_probe_single(), which is not done by sci_cleanup_single().
Else the serial port stays active from the point of view of the serial
subsystem, and it may crash when
3.10.32-rt31-rc1 stable review patch.
If anyone has any objections, please let me know.
--
From: Nicholas Mc Guire der.h...@hofr.at
in response to the oops in ip_output.c:ip_send_unicast_reply under high
network load with CONFIG_PREEMPT_RT_FULL=y, reported by Sami Pietikainen
Add support for custom reserved memory drivers. Call their init() function
for each reserved region and prepare for using operations provided by them
with by the reserved_mem-ops array.
Based on previous code provided by Josh Cartwright jo...@codeaurora.org
Signed-off-by: Marek Szyprowski
This patch adds code for automated assignment of reserved memory regions
to struct device. reserved_mem-ops-device_init()/device_cleanup()
callbacks are called to perform reserved memory driver specific
initialization and cleanup
Based on previous code provided by Josh Cartwright
This patch adds support for static (defined by 'reg' property) reserved
memory regions declared in device tree.
Memory blocks can be reliably reserved only during early boot. This must
happen before the whole memory management subsystem is initialized,
because we need to ensure that the given
Enable reserved memory initialization from device tree.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm64/Kconfig |1 +
arch/arm64/mm/init.c |1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index
Enable reserved memory initialization from device tree.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/Kconfig |1 +
arch/arm/mm/init.c |2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e25419817791..d0262bea8020
Enable reserved memory initialization from device tree.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/powerpc/Kconfig |1 +
arch/powerpc/kernel/prom.c |3 +++
2 files changed, 4 insertions(+)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index
Refactor internal dma_contiguous_init_reserved_mem() function, which
creates CMA area from previously reserved memory region and add support
for handling 'shared-dma-pool' reserved-memory device tree nodes.
Based on previous code provided by Josh Cartwright jo...@codeaurora.org
Signed-off-by:
FROM MRS.SUSAN SHABANGU.docx
Description: application/vnd.openxmlformats-officedocument.wordprocessingml.document
From: Grant Likely grant.lik...@linaro.org
Reserved memory nodes allow for the reservation of static (fixed
address) regions, or dynamically allocated regions for a specific
purpose.
Signed-off-by: Grant Likely grant.lik...@linaro.org
[joshc: Based on binding document proposed (in non-patch
Hi Marc,
-Original Message-
From: Marc Kleine-Budde [mailto:m...@pengutronix.de]
Sent: Friday, February 28, 2014 6:45 PM
To: Appana Durga Kedareswara Rao; w...@grandegger.com; Michal Simek;
grant.lik...@linaro.org; robh...@kernel.org; linux-...@vger.kernel.org
Cc:
3.10.32-rt31-rc1 stable review patch.
If anyone has any objections, please let me know.
--
From: Steven Rostedt rost...@goodmis.org
Ulrich Obergfell pointed out that cpu_chill() calls msleep() which is woken
up by the ksoftirqd running the TIMER softirq. But as the cpu_chill()
On 02/28/2014 01:39 AM, Peter Ujfalusi wrote:
On 02/27/2014 05:00 PM, Nishanth Menon wrote:
The other option might be to blindly configure 6040 to max speed -
but then you do have an issue with that single register write
operation to configure the speed?
Yes, exactly. It is unfortunate that
3.10.32-rt31-rc1 stable review patch.
If anyone has any objections, please let me know.
--
From: Steven Rostedt rost...@goodmis.org
It was previously discovered that some systems would hang on boot up
with a previous version of 3.12-rt. This was due to RCU using irq_work,
and RT
3.10.32-rt31-rc1 stable review patch.
If anyone has any objections, please let me know.
--
From: Tiejun Chen tiejun.c...@windriver.com
Any callers to the function rcu_preempt_qs() must disable irqs in
order to protect the assignment to -rcu_read_unlock_special. In
RT case,
3.10.32-rt31-rc1 stable review patch.
If anyone has any objections, please let me know.
--
From: Thomas Gleixner t...@linutronix.de
Mike,
On Thu, 7 Nov 2013, Mike Galbraith wrote:
On Thu, 2013-11-07 at 04:26 +0100, Mike Galbraith wrote:
On Wed, 2013-11-06 at 18:49 +0100,
Hello again!
Here is another update of the support for reserved memory regions in
device tree. I've fixes a few more minor issues pointed by Grant. See
changelog for more details.
The initial code for this feature were posted here [1], merged as commit
9d8eab7af79cb4ce2de5de39f82c455b1f796963
Use recently introduced of_reserved_mem_device_init() function to
automatically assign respective reserved memory region to the newly created
platform and amba device.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
drivers/of/platform.c |7 +++
1 file changed, 7
This patch adds support for dynamically allocated reserved memory regions
declared in device tree. Such regions are defined by 'size', 'alignment'
and 'alloc-ranges' properties.
Based on previous code provided by Josh Cartwright jo...@codeaurora.org
Signed-off-by: Marek Szyprowski
The Broadcom 281xx clock code uses a #define for the compatible
string for it's clock control units (CCUs). Rather than defining
those in the C source file, define them in the header file that's
shared by both the code and the device tree source file (along with
all the clock ids).
Replace the fake fixed-rate clocks used previously for the
bcm21664 family with real ones.
Signed-off-by: Alex Elder el...@linaro.org
---
arch/arm/boot/dts/bcm21664.dtsi | 190 ---
1 file changed, 118 insertions(+), 72 deletions(-)
diff --git
3.10.32-rt31-rc1 stable review patch.
If anyone has any objections, please let me know.
--
From: Steven Rostedt (Red Hat) rost...@goodmis.org
---
localversion-rt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/localversion-rt b/localversion-rt
index
The next patch defines a binding for a new Broadcom SoC that uses
Kona style CCUs for its clocks. Update the generic Kona clock
binding document so it's more natural to accomodate the definitions
of additional SoC families.
Specifically:
- Define the compatible string values generically,
Document the device tree binding for Broadcom BCM28164 clock control
units and clocks. This SoC uses Kona CCUs, similar to the BCM281XX
SoC family.
Signed-off-by: Alex Elder el...@linaro.org
---
.../devicetree/bindings/clock/bcm-kona-clock.txt | 39
1 file changed, 39
This is series has two parts. The first two patches are changes
to the existing Broadcom Kona family clock code to prepare for the
addition of support for another SoC bcm21664.
The remaining three define the binding and code for bcm21664, and
replace the use of fake clocks in the device tree
Define the set of CCUs and provided clocks sufficient to satisfy the
needs of all the existing clock references for BCM21664. Replace
the fake fixed-rate clocks used previously with real ones.
Note that only the minimal set of these clocks and CCUs is defined
here. More clock definitions will
This patch prepares for adding support for S2MPS14 RTC device to the
rtc-s5m driver:
1. Adds a map of registers used by the driver which differ between
the chipsets (S5M876X and S2MPS14).
2. Moves code of checking for alarm pending to separate function.
Signed-off-by: Krzysztof Kozlowski
Add support for handling 'shared-dma-pool' reserved-memory device tree
nodes.
Based on previous code provided by Josh Cartwright jo...@codeaurora.org
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
drivers/base/dma-coherent.c | 40
1 file
On 27/02/2014 06:00, Jingoo Han :
Use devm_clk_get() to make cleanup paths simpler.
Signed-off-by: Jingoo Han jg1@samsung.com
Acked-by: Nicolas Ferre nicolas.fe...@atmel.com
Thanks a lot.
---
drivers/char/hw_random/atmel-rng.c |8 ++--
1 file changed, 2 insertions(+), 6
On Thu, 06 Feb 2014 09:41:27 -0500
Steven Rostedt rost...@goodmis.org wrote:
HPA, Ping?
-- Steve
Peter,
Back in August 2011, I had a pull request to make the irq stack of
i386 more like the x86_64 code. There seemed to be acceptance back
then and you said you would even pull it after
On Fri, 28 Feb 2014 15:19:20 +0900, Mark Brown broo...@kernel.org wrote:
I don't object to the whole patch. Validating in spi core is good of
course, and xfer-len % w_size part looks no problem.
I just want to keep ways to handle an odd device, for example, which
requires long delay between
On Thu, Feb 27, 2014 at 05:55:18PM -0800, Stephen Boyd wrote:
Document the keypad device found on PM8921 and PM8058 PMICs.
[..]
+++ b/Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
@@ -0,0 +1,72 @@
+Qualcomm PM8xxx PMIC Keypad
+
+PROPERTIES
+
+- compatible:
+ Usage:
On Fri, Feb 28, 2014 at 03:27:50PM +0300, Dennis Mungai wrote:
Hello people,
Note that revisions of the Dothan core were released in the first quarter
of 2005 with the *Sonoma* chipsets and supported a 533 MT/s FSB and NX-bit
(and PAE support required for it was enabled, unlike earlier
This patch prepares for adding support for S2MPS14 RTC device to the
rtc-s5m driver:
1. Renames SEC* symbols to S5M.
2. Adds S5M prefix to some of defines which are different between S5M876X
and S2MPS14.
This is only a rename-like patch, new code is not added.
Signed-off-by: Krzysztof Kozlowski
Add support for S2MPS14 to the rtc-s5m driver. Differences in S2MPS14
(in comparison to S5M8767):
- Layout of registers;
- Lack of century support for time and alarms (7 registers used for
storing time/alarm);
- Two buffer control registers: WUDR and RUDR;
- No register for enabling writing
Hi,
Few days ago I sent patches adding support for S2MPS14 device to the
sec-core/s2mps11 drivers. These patches were rather large as they covered
multiple subsystems so I decided to split everything into smaller, separate
patches.
The original patchset (version 3) can be found here:
This patch removes the code for initializing time if this is first boot.
The code for detecting first boot uses undocumented field RTC_TCON in
RTC_UDR_CON register. According to S5M8767's datasheet this field is
reserved. On S2MPS14 it is not documented at all. On device first boot
the registers
From: Andi Kleen a...@linux.intel.com
Clarify in the documentation that perf mem report reports
use-latency, not load/store-latency on Intel systems.
This often causes confusion with users.
Cc: eran...@google.com
Signed-off-by: Andi Kleen a...@linux.intel.com
---
This clarifies two common problems in the perf man pages.
No code changes.
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From: Andi Kleen a...@linux.intel.com
Clarify how to specify x86 registers in perf probe. I recently
ran into this problem and had to figure it out from the source.
Cc: masami.hiramatsu...@hitachi.com
Signed-off-by: Andi Kleen a...@linux.intel.com
---
tools/perf/Documentation/perf-probe.txt | 2
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