The VDSO temporary file is unlinked when a session is
deleted. That precludes the possibilities that there
is no session or there is more than one session.
Correctly the vdso belongs to the machine so put the
information on 'struct machine' and get rid of the global
variables.
Signed-off-by: Adri
On Tue, Jul 22, 2014 at 03:47:49PM -0400, Matthew Wilcox wrote:
> Pagecache faults recheck i_size after taking the page lock to ensure that
> the fault didn't race against a truncate. We don't have a page to lock
> in the XIP case, so use the i_mmap_mutex instead. It is locked in the
> truncate p
From: Nicolin Chen
TE/RE bit of T/RCSR will remain set untill the current frame is physically
finished. The FIFO reset operation should wait this bit's totally cleared
rather than ignoring its status which might cause TE/RE disabling failed.
This patch adds delay and timeout to wait for its comp
The series of patches focus on issue fix inside fsl_sai_trigger().
Nicolin Chen (3):
ASoC: fsl_sai: Reduce race condition during TE/RE enabling
ASoC: fsl_sai: Don't reset FIFO until TE/RE bit is unset
ASoC: fsl_sai: Improve enable flow in fsl_sai_trigger()
sound/soc/fsl/fsl_sai.c | 40
From: Nicolin Chen
For trigger start, we don't need to check if it's the first time to
enable TE/RE or second time. It doesn't hurt to enable them any way,
which in the meantime can reduce race condition for TE/RE enabling.
For trigger stop, we will definitely clear FRDE of current direction.
Th
From: Nicolin Chen
The previous enable flow:
1, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO)
2, Mask IRQ of Tx/Rx to enable its interrupt.
3, Enable DMA request of Tx/Rx.
As this flow would enable DMA request later than TERE, the Tx FIFO
would be easily emptied into underrun whi
On Wednesday, July 23, 2014 01:56:36 PM Arjun wrote:
> ACPI 5.0 resource types like FixedDMA will fail pnpacpi_allocated_resource().
> pnpacpi_add_device() has to return error in that case.
Why?
> On 23 July 2014 03:42, Rafael J. Wysocki wrote:
> > On Wednesday, July 23, 2014 12:43:39 AM Arjun S
On Wed, Jul 23, 2014 at 02:35:06AM +0100, Laura Abbott wrote:
> +void dma_common_free_remap(void *cpu_addr, size_t size, unsigned long
> vm_flags)
> +{
> + struct vm_struct *area = find_vm_area(cpu_addr);
> +
> + if (!area || (area->flags & vm_flags) != vm_flags) {
> + WARN(1,
On 07/23/2014 04:41 PM, Yao Yuan wrote:
Hi,
Thanks for your review.
Lothar Waßmann wrote:
Yuan Yao wrote:
Add dma support for i2c. This function depend on DMA driver.
You can turn on it by write both the dmas and dma-name properties in dts node.
Signed-off-by: Yuan Yao
---
drivers/i2c/bus
On Tuesday 22 July 2014 22:03:52 Catalin Marinas wrote:
> On Tue, Jul 22, 2014 at 07:06:44PM +0100, Arnd Bergmann wrote:
> > On Wednesday 02 July 2014, Laura Abbott wrote:
> > > + pgprot_t prot = __pgprot(PROT_NORMAL_NC);
> > > + unsigned long nr_pages = atomic_pool_size >> PAGE_SHIFT;
Hi,
Thanks for your review.
Lothar Waßmann wrote:
> Yuan Yao wrote:
> > Add dma support for i2c. This function depend on DMA driver.
> > You can turn on it by write both the dmas and dma-name properties in dts
> > node.
> >
> > Signed-off-by: Yuan Yao
> > ---
> > drivers/i2c/busses/i2c-imx.c |
On Wed, Jul 23, 2014 at 10:45:46AM +0100, Dietmar Eggemann wrote:
> Doesn't the picture showing the captured panic reveal more information.
> Haven't seen it myself, I just saw Peter's reply to your email
Its a general protection fault from somewhere in load_balance(), I send
you the picture.
It
On 07/17/2014 05:19 PM, Chen Gang wrote:
>
>
> On 07/17/2014 05:16 PM, Dan Carpenter wrote:
>> On Thu, Jul 17, 2014 at 04:59:09PM +0800, Chen Gang wrote:
> + return (__force void __iomem *)ERR_PTR(-ENXIO);
There's apparently an IOMEM_ERR_PTR() for this nowadays...
>>>
>>> IOM
On Tue, Jul 15, 2014 at 04:39:14PM +0200, Antoine Ténart wrote:
> This patch modify the generic code handling PHYs to allow them to be
> supplied from the drivers. This adds checks to ensure no PHY was already
> there when looking for one in the generic code. This also makes sure we
> do not modify
Add a function to change which event is used
to track mmap, comm and task events.
This is needed with Instruction Tracing
because the Instruction Tracing event
must come first but cannot be used for
tracking because it will be disabled
under some circumstances.
Signed-off-by: Adrian Hunter
---
From: Laurent Pinchart
Now that all platforms have switched to the new-style platform data,
drop support for the legacy version.
Signed-off-by: Laurent Pinchart
Tested-by: Simon Horman
---
drivers/clocksource/sh_cmt.c | 172 ++
1 file changed, 40 inser
From: Laurent Pinchart
The global spinlock is used to protect the shared start/stop register.
Now that all MTU2 channels are handled by a single device instance, use
a per-device spinlock.
Signed-off-by: Laurent Pinchart
Tested-by: Wolfram Sang
---
drivers/clocksource/sh_mtu2.c | 10 ++-
From: Laurent Pinchart
The name, channel_offset, timer_bit, clockevent_rating and
clocksource_rating members are unused. Remove them.
Signed-off-by: Laurent Pinchart
Tested-by: Simon Horman
---
include/linux/sh_timer.h |5 -
1 file changed, 5 deletions(-)
diff --git a/include/linux/s
From: Laurent Pinchart
Document DT bindings and parse them in the CMT driver.
Signed-off-by: Laurent Pinchart
Tested-by: Simon Horman
---
.../devicetree/bindings/timer/renesas,cmt.txt | 47 ++
drivers/clocksource/sh_cmt.c | 66 ++--
2
From: Laurent Pinchart
Now that all platforms have switched to the new-style platform data,
drop support for the legacy version.
Signed-off-by: Laurent Pinchart
Tested-by: Simon Horman
---
drivers/clocksource/sh_tmu.c | 82 --
1 file changed, 15 inser
From: Laurent Pinchart
The global spinlock is used to protect the shared start/stop register.
Now that all TMU channels are handled by a single device instance, use a
per-device spinlock.
Signed-off-by: Laurent Pinchart
Tested-by: Simon Horman
---
drivers/clocksource/sh_tmu.c | 10 ++---
From: Laurent Pinchart
Document DT bindings and parse them in the TMU driver.
Signed-off-by: Laurent Pinchart
Tested-by: Simon Horman
---
.../devicetree/bindings/timer/renesas,tmu.txt | 39 +++
drivers/clocksource/sh_tmu.c | 51
From: Laurent Pinchart
Document DT bindings and parse them in the MTU2 driver.
Signed-off-by: Laurent Pinchart
Tested-by: Wolfram Sang
---
.../devicetree/bindings/timer/renesas,mtu2.txt | 39
drivers/clocksource/sh_mtu2.c |8
2 files ch
From: Matthias Brugger
Signed-off-by: Matthias Brugger
Acked-by: Rob Herring
Signed-off-by: Daniel Lezcano
---
.../devicetree/bindings/vendor-prefixes.txt|1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devic
On Tue 2014-07-22 14:10:22, Joerg Roedel wrote:
> On Tue, Jul 22, 2014 at 12:58:12PM +0200, Pavel Machek wrote:
> > On Tue 2014-07-22 12:34:44, Joerg Roedel wrote:
> > > On Tue, Jul 22, 2014 at 02:41:29AM +0200, Rafael J. Wysocki wrote:
> > > > It looks like some specific need motivated the Joerg's
From: Kuninori Morimoto
It should be "MTU2" instead of "TMU2"
Signed-off-by: Kuninori Morimoto
Acked-by: Wolfram Sang
Acked-by: Simon Horman
Signed-off-by: Daniel Lezcano
---
drivers/clocksource/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksour
From: Chen Gang
In 'em_sti.c', it will call devm_ioremap_resource() which need
HAS_IOMEM. So need let EM_TIMER_STI depend on HAS_IOMEM, too.
The related error (with allmodconfig under score):
LD init/built-in.o
em_sti.c:(.text.em_sti_probe+0x84): undefined reference to
`devm_ioremap_res
From: Alexander Shiyan
This adds the clocksource driver for Cirrus Logic CLPS711X series SoCs.
Designed primarily for migration CLPS711X subarch for multiplatform & DT,
for this as the "OF" and "non-OF" calls implemented.
Signed-off-by: Alexander Shiyan
Acked-by: Arnd Bergmann
Signed-off-by: D
From: Alexander Shiyan
This patch adds DT binding documentation for the Cirrus Logic
CLPS711X-based CPUs clocksource subsystem.
Signed-off-by: Alexander Shiyan
Acked-by: Arnd Bergmann
Signed-off-by: Daniel Lezcano
---
.../bindings/timer/cirrus,clps711x-timer.txt | 29
From: Matthias Brugger
Add binding documentation for the General Purpose Timer driver of
the Mediatek SoCs.
Signed-off-by: Matthias Brugger
Acked-by: Sören Brinkmann
Acked-by: Rob Herring
Signed-off-by: Daniel Lezcano
---
.../bindings/timer/mediatek,mtk-timer.txt | 17 +++
From: Zhiwu Song
In the clocksource driver, we didn't explicitly enable the clock. it makes the
clk reference counter wrong. We didn't encounter any hang issue because the
tick's clock input has been open and is shared by some other hardware
components, but if we don't enable those components in
From: Matthias Brugger
A call to of_iomap does not request the memory region. This patch adds the
function of_io_request_and_map which requests the memory region before
mapping it.
Signed-off-by: Matthias Brugger
Suggested-by: Thomas Gleixner
Suggested-by: Rob Herring
Acked-by: Rob Herring
S
From: Robert Jarzmik
As clocksource pxa_timer was moved to clocksource framework, the
pxa_timer initialization needs to be a bit amended, to pass the
necessary informations to clocksource, ie :
- the timer interrupt (mach specific)
- the timer registers base (ditto)
- the timer clockrate
Sign
From: Robert Jarzmik
Add device-tree support to PXA platforms.
The driver still needs to maintain backward non device-tree
compatibility as well, which implies :
- a non device-tree init function
- a static registers base address in the driver
Signed-off-by: Robert Jarzmik
Signed-off-by: Dani
From: Robert Jarzmik
Move time.c from arch/arm/mach-pxa/time.c to
drivers/clocksource/pxa_timer.c.
Signed-off-by: Robert Jarzmik
Signed-off-by: Daniel Lezcano
---
arch/arm/mach-pxa/Makefile |2 +-
arch/arm/mach-pxa/time.c| 162 ---
drivers
From: Doug Anderson
Using the __raw functions is discouraged. Update the file to
consistently use the proper functions.
Signed-off-by: Doug Anderson
Signed-off-by: Kukjin Kim
Signed-off-by: Daniel Lezcano
---
drivers/clocksource/exynos_mct.c | 24
1 file changed,
From: Doug Anderson
The MCT has a nice 64-bit counter. That means that we _can_ register
as a 64-bit clocksource and sched_clock. ...but that doesn't mean we
should.
The 64-bit counter is read by reading two 32-bit registers. That
means reading needs to be something like:
- Read upper half
-
From: Robert Jarzmik
Select CLKSRC_OF for PXA architectures.
Signed-off-by: Robert Jarzmik
Signed-off-by: Daniel Lezcano
---
arch/arm/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 245058b..05a7151 100644
--- a/arch/arm/Kconfig
+++ b/a
From: Laurent Pinchart
The global spinlock is used to protect the shared start/stop register.
Now that all CMT channels are handled by a single device instance, use a
per-device spinlock.
Signed-off-by: Laurent Pinchart
Tested-by: Simon Horman
---
drivers/clocksource/sh_cmt.c |9 +
From: Laurent Pinchart
Now that all platforms have switched to the new-style platform data,
drop support for the legacy version.
Signed-off-by: Laurent Pinchart
Tested-by: Wolfram Sang
---
drivers/clocksource/sh_mtu2.c | 130 ++---
1 file changed, 31 inser
From: Matthias Brugger
This patch adds a clock source and clock event for the timer found
on the Mediatek SoCs.
The Mediatek General Purpose Timer block provides five 32 bit timers and
one 64 bit timer.
Two 32 bit timers are used by this driver:
TIMER1: clock events supporting periodic and ones
On Wed, Jul 23, 2014 at 12:13 PM, Christian König
wrote:
>
>> And the dma-buf would still have fences belonging to both drivers, and it
>> would still call from outside the driver.
>
>
> Calling from outside the driver is fine as long as the driver can do
> everything necessary to complete it's wo
Hi!
> In the current world, all nonboot cpus are enabled serially during system
> resume. System resume sequence is that boot cpu enables nonboot cpu one by
> one and then resume devices. Before resuming devices, there are few tasks
> assigned to nonboot cpus after they are brought up. This waste
On Mon, Jul 21, 2014 at 03:47:10PM +0400, Vladimir Davydov wrote:
> This patch set makes memcg release memcg_cache_id on css offline. This
> way the memcg_caches arrays size will be limited by the number of alive
> kmem-active memory cgroups, which is much better.
Hi Andrew,
While preparing the p
On Wed, Jul 23, 2014 at 06:31:26PM +0900, Michel Dänzer wrote:
> On 23.07.2014 18:25, Peter Zijlstra wrote:
> > On Wed, Jul 23, 2014 at 10:28:19AM +0200, Peter Zijlstra wrote:
> >
> >> Of course, the other thing that patch did is clear sgp->power (now
> >> sgc->capacity).
> >
> > Hmm, re-reading
Hi Thomas,
here is the new material for the clockevents for 3.17. This time things
have been a bit fuzzy with the patches submission. I assume it is
resulting from different factors: vacation period and two kernel
versions very near. Anyway, I double checked it and I thing everything
is ok.
On Tue, Jul 22, 2014 at 06:33:02PM -0700, Andy Lutomirski wrote:
> Of course, this does nothing at all to protect us from #MC after sti
> on return from #MC to userspace, but I think we're screwed regardless
> -- we could just as easily get a second #MC before the sti. Machine
> check broadcast was
The issue was reported by static analysis.
The value holding flags was &-ed with 0x02, being compared to 0x01
(TRUE) after that. Such comparsion is always false.
Resolution: drop the comparsion to TRUE in the condition.
&-ing with 0x02 is right, according to result variable name
(reporting_mode)
On Wed, Jul 23, 2014 at 02:35:06AM +0100, Laura Abbott wrote:
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -298,37 +298,19 @@ static void *
> __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
> const void *caller)
> {
> - struct vm_s
On Mon, Jul 21, 2014 at 04:49:29PM +0100, Alexei Starovoitov wrote:
> On Mon, Jul 21, 2014 at 2:16 AM, Will Deacon wrote:
> > On Fri, Jul 18, 2014 at 07:28:06PM +0100, Zi Shen Lim wrote:
> >> This series implements eBPF JIT compiler for arm64.
> >> Please see [14/14] for change log.
> >>
> >> Patc
Make of_device_id array const, because all OF functions handle it as const.
Signed-off-by: Kiran Padwal
---
drivers/tty/serial/msm_serial.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 6baf2ad..f4a8
On 07/08/14 10:40, Jean-Francois Moine wrote:
> This patch adds a CODEC function to the NXP TDA998x HDMI transmitter.
>
> The CODEC handles both I2S and S/PDIF input and does dynamic input
> switch in the TDA998x I2C driver on start/stop audio streaming.
>
> Signed-off-by: Jean-Francois Moine
>
At Tue, 22 Jul 2014 11:28:59 -0700,
Kees Cook wrote:
n>
> This adds an LSM hook to the existing firmware loading logic so that
> the LSM can reason about the origin and contents of a firmware coming
> from userspace.
>
> Thanks,
>
> -Kees
>
> v3:
> - correctly return LSM error to userspace (min
Am 23.07.2014 11:55, schrieb Maarten Lankhorst:
op 23-07-14 11:47, Christian König schreef:
Am 23.07.2014 11:44, schrieb Daniel Vetter:
On Wed, Jul 23, 2014 at 11:39 AM, Daniel Vetter wrote:
The scheduler needs to keep track of a lot of fences, so I think we'll
have to register callbacks, not
On Wed, Jul 23, 2014 at 11:07:46AM +0100, Mark Brown wrote:
> On Wed, Jul 23, 2014 at 05:52:32PM +0800, Nicolin Chen wrote:
>
> > I found this two patches are merged into for-next branch, although I haven't
> > got the 'applied' email.
>
> > Is that possible for you to drop this one? If not, I'l
At Tue, 22 Jul 2014 10:39:00 -0700,
Kees Cook wrote:
>
> On Mon, Jul 21, 2014 at 11:55 PM, Takashi Iwai wrote:
> > At Mon, 21 Jul 2014 12:06:41 -0700,
> > Kees Cook wrote:
> >>
> >> This attaches LSM hooks to the existing firmware loading interfaces:
> >> filesystem-found firmware and demand-load
Thanks, so this is also available in next kernel release version.
Regards
Sanjeev Sharma
-Original Message-
From: Greg KH [mailto:gre...@linuxfoundation.org]
Sent: Saturday, July 19, 2014 4:46 AM
To: Sharma, Sanjeev
Cc: de...@driverdev.osuosl.org; way...@gmail.com; swetl...@google.com;
On Wed, Jul 23, 2014 at 05:52:32PM +0800, Nicolin Chen wrote:
> I found this two patches are merged into for-next branch, although I haven't
> got the 'applied' email.
> Is that possible for you to drop this one? If not, I'll send another patch
> to fix this.
Please send a patch, I'd already ap
On Mon, Jul 21, 2014 at 04:06:01PM -0700, K. Y. Srinivasan wrote:
> Add blist flags to permit the reading of the VPD pages even when
> the target may claim SPC-2 compliance. MSFT targets currently
> claim SPC-2 compliance while they implement post SPC-2 features.
> With this patch we can correctly
Sir,
I found this two patches are merged into for-next branch, although I haven't
got the 'applied' email.
Is that possible for you to drop this one? If not, I'll send another patch
to fix this.
Thank you,
Nicolin
On Fri, Jul 18, 2014 at 06:18:12PM +0800, Nicolin Chen wrote:
> Mark,
>
>
op 23-07-14 11:47, Christian König schreef:
> Am 23.07.2014 11:44, schrieb Daniel Vetter:
>> On Wed, Jul 23, 2014 at 11:39 AM, Daniel Vetter
>> wrote:
>>> The scheduler needs to keep track of a lot of fences, so I think we'll
>>> have to register callbacks, not a simple wait function. We must kee
On Sun, Jul 20, 2014 at 09:22:52PM -0700, Linus Torvalds wrote:
> So go get the latest rc and kick the tires, to see that nothing has
> fallen through the cracks, ok?
Well, it looks like we f*cked up something after -rc5 since I'm starting
to see lockdep splats all over the place which I didn't se
On Wed, Jul 23, 2014 at 11:47 AM, Christian König
wrote:
> Am 23.07.2014 11:44, schrieb Daniel Vetter:
>> On Wed, Jul 23, 2014 at 11:39 AM, Daniel Vetter
>> wrote:
>>>
>>> The scheduler needs to keep track of a lot of fences, so I think we'll
>>> have to register callbacks, not a simple wait func
On 2014年07月23日 17:21, Peter Zijlstra wrote:
> On Wed, Jul 23, 2014 at 05:11:34PM +0800, Lan Tianyu wrote:
>> In the current world, all nonboot cpus are enabled serially during system
>> resume. System resume sequence is that boot cpu enables nonboot cpu one by
>> one and then resume devices. Before
Hi,
Yuan Yao wrote:
> Add dma support for i2c. This function depend on DMA driver.
> You can turn on it by write both the dmas and dma-name properties in dts node.
>
> Signed-off-by: Yuan Yao
> ---
> drivers/i2c/busses/i2c-imx.c | 377
> +--
> 1 file cha
Am 23.07.2014 11:44, schrieb Daniel Vetter:
On Wed, Jul 23, 2014 at 11:39 AM, Daniel Vetter wrote:
The scheduler needs to keep track of a lot of fences, so I think we'll
have to register callbacks, not a simple wait function. We must keep
track of all the non-i915 fences for all oustanding batc
Hi,
On Wed, Jul 23, 2014, at 00:59, Theodore Ts'o wrote:
> But why would you need to use GRND_RANDOM in your scenario, and accept
> your application potentially getting stalled and stuck in amber for
> perhaps hours? If you are going to accept your application stalling
> like that, you can do the
On Tue, Jul 22, 2014 at 9:14 PM, Jesse Barnes wrote:
>> We don't have the code yet ready, but that's the direction i915 will
>> move towards for the near future. Jesse is working on some patches
>> already.
>
> Yeah I'd like to get some feedback from Maarten on my bits so I can get
> them ready fo
On 23/07/14 10:31, Michel Dänzer wrote:
> On 23.07.2014 18:25, Peter Zijlstra wrote:
>> On Wed, Jul 23, 2014 at 10:28:19AM +0200, Peter Zijlstra wrote:
>>
>>> Of course, the other thing that patch did is clear sgp->power (now
>>> sgc->capacity).
>>
>> Hmm, re-reading the thread there isn't a clear
On Wed, Jul 23, 2014 at 11:39 AM, Daniel Vetter wrote:
> The scheduler needs to keep track of a lot of fences, so I think we'll
> have to register callbacks, not a simple wait function. We must keep
> track of all the non-i915 fences for all oustanding batches. Also, the
> scheduler doesn't elimin
Add a function to return the total number of digital I/O, digital input,
and digital output ports on the board. Each port has 8 channels (bits).
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/ni_65xx.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --gi
Refactor the code that updates the rising and falling edge detection
registers into new function `ni_65xx_update_edge_detection()`. This
updates the rising and falling edge detection registers for up to 32
channels starting at an arbitrary channel. Call it from the code that
handles the `INSN_CON
On Wed, Jul 23, 2014 at 2:48 PM, Jingoo Han wrote:
> On Wednesday, July 23, 2014 4:38 PM, Kiran Padwal wrote:
>>
>> Make of_device_id array const, because all OF functions handle it as const.
>
> Hi Kiran Padwal,
>
> The same patch was already submitted and merged to USB tree.
> Thank you.
Thanks
Add partial support for INSN_CONFIG_DIGITAL_TRIG as an alternative to
INSN_CONFIG_CHANGE_NOTIFY (with the advantage that more than the first 32
channels are supported), and initialize the edge detection registers.
1) staging: comedi: ni_65xx: add ni_65xx_num_ports()
2) staging: comedi: ni_65xx: re
As part of the migration we introduce DEBUG_UART_PHYS/DEBUG_UART_VIRT
which default to UART1 but allow a user to configure UART2 or UART3.
We also introduce symbolic names for the registers and flags.
Signed-off-by: Daniel Thompson
Cc: Russell King
Cc: Arnd Bergmann
Cc: linux-arm-ker...@lists.i
The "edge detection interrupt" subdevice supports the
`INSN_CONFIG_CHANGE_NOTIFY` comedi instruction which is only supported
by one other driver. It is limited to the first 32 channels, but boards
supported by this driver support edge detection on all digital I/O,
digital input and digital output
When the hardware is being initialized, the edge detection interrupts
are cleared and disabled. Also disable edge detection for all channels
at this time so they start off in a known state.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/ni_65xx.c | 1 +
1 file changed, 1 insertion
On Tue, Jul 22, 2014 at 06:03:35PM -0700, Linus Torvalds wrote:
> So I'm afraid that "sti; lret" is not guaranteed to be architecturally
> NMI-safe. But it *might* be safe on certain micro-architectures, and
> maybe somebody inside Intel or AMD can give us a hint about when it is
> safe and when it
Am 23.07.2014 11:38, schrieb Maarten Lankhorst:
op 23-07-14 11:36, Christian König schreef:
Am 23.07.2014 11:30, schrieb Daniel Vetter:
On Wed, Jul 23, 2014 at 11:27 AM, Christian König
wrote:
You submit a job to the hardware and then block the job to wait for radeon
to be finished? Well than
This code corrects endianness and avoids a sparse error.
Tested with Lattice ECP3-35 with Freescale i.MX6.
It also sends uevent in order to load it.
Signed-off-by: Jean-Michel Hautbois
---
drivers/misc/lattice-ecp3-config.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
On Wed, Jul 23, 2014 at 11:36 AM, Christian König
wrote:
> Am 23.07.2014 11:30, schrieb Daniel Vetter:
>
>> On Wed, Jul 23, 2014 at 11:27 AM, Christian König
>> wrote:
>>>
>>> You submit a job to the hardware and then block the job to wait for
>>> radeon
>>> to be finished? Well than this would i
op 23-07-14 11:36, Christian König schreef:
> Am 23.07.2014 11:30, schrieb Daniel Vetter:
>> On Wed, Jul 23, 2014 at 11:27 AM, Christian König
>> wrote:
>>> You submit a job to the hardware and then block the job to wait for radeon
>>> to be finished? Well than this would indeed require a hardware
Am 23.07.2014 11:30, schrieb Daniel Vetter:
On Wed, Jul 23, 2014 at 11:27 AM, Christian König
wrote:
You submit a job to the hardware and then block the job to wait for radeon
to be finished? Well than this would indeed require a hardware reset, but
wouldn't that make the whole problem even wor
On Wed, Jul 23, 2014 at 09:24:49AM +0300, Adrian Hunter wrote:
> On 07/22/2014 10:09 PM, Jiri Olsa wrote:
> > On Tue, Jul 22, 2014 at 04:17:22PM +0300, Adrian Hunter wrote:
> >
> > SNIP
> >
> >> +
> >> +static FILE *perf_pmu__open_file(struct perf_pmu *pmu, const char *name)
> >> +{
> >> + struc
On 23.07.2014 18:25, Peter Zijlstra wrote:
> On Wed, Jul 23, 2014 at 10:28:19AM +0200, Peter Zijlstra wrote:
>
>> Of course, the other thing that patch did is clear sgp->power (now
>> sgc->capacity).
>
> Hmm, re-reading the thread there isn't a clear confirmation its this
> patch at all. Could y
On Wed, Jul 23, 2014 at 11:27 AM, Christian König
wrote:
> You submit a job to the hardware and then block the job to wait for radeon
> to be finished? Well than this would indeed require a hardware reset, but
> wouldn't that make the whole problem even worse?
>
> I mean currently we block one use
Am 23.07.2014 10:54, schrieb Daniel Vetter:
On Wed, Jul 23, 2014 at 10:46 AM, Christian König
wrote:
Am 23.07.2014 10:42, schrieb Daniel Vetter:
On Wed, Jul 23, 2014 at 10:25 AM, Maarten Lankhorst
wrote:
In this case if the sync was to i915 the i915 lockup procedure would take
care of itsel
* Nishanth Menon [140528 14:48]:
> TWL4030's Battery Charger seems to be designed for non-hotpluggable
> batteries.
>
> If battery is not present in the system, BATSTS is always set with the
> expectation that software will take actions to move to a required safe
> state (could be power down or d
PowerNV platform is capable of capturing host memory region when system
crashes (because of host/firmware). We have new OPAL API to register
memory region to be capture when system crashes.
This patch adds support for new API and also registers kernel log buffer.
Signed-off-by: Vasant Hegde
---
On Wed, Jul 23, 2014 at 10:28:19AM +0200, Peter Zijlstra wrote:
> Of course, the other thing that patch did is clear sgp->power (now
> sgc->capacity).
Hmm, re-reading the thread there isn't a clear confirmation its this
patch at all. Could you perhaps bisect this to either verify it is
indeed th
Platforms like IBM Power Systems supports service processor
assisted dump. It provides interface to add memory region to
be captured when system is crashed.
During initialization/running we can add kernel memory region
to be collected.
Presently we don't have a way to get the log buffer base addr
On Wed, Jul 23, 2014 at 05:11:34PM +0800, Lan Tianyu wrote:
> In the current world, all nonboot cpus are enabled serially during system
> resume. System resume sequence is that boot cpu enables nonboot cpu one by
> one and then resume devices. Before resuming devices, there are few tasks
> assigned
于 2014年07月23日 00:40, Peter Hurley 写道:
> On 07/22/2014 07:52 AM, xinhui.pan wrote:
>>
>> 于 2014年07月21日 23:38, Greg KH 写道:
>>> On Mon, Jul 21, 2014 at 08:47:16PM +0800, pp wrote:
As reuse the cdev may cause panic. After we unregister the tty device, we
may use tty_hangup() o
other s
On Wednesday, July 23, 2014 4:38 PM, Kiran Padwal wrote:
>
> Make of_device_id array const, because all OF functions handle it as const.
Hi Kiran Padwal,
The same patch was already submitted and merged to USB tree.
Thank you.
Best regards,
Jingoo Han
>
> Signed-off-by: Kiran Padwal
> ---
>
Add i2c dts node properties for eDMA support, them depend on the eDMA driver.
Signed-off-by: Yuan Yao
---
Documentation/devicetree/bindings/i2c/i2c-imx.txt | 11 +++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx.txt
b/Documentation/devicetr
KSM thread to scan pages is getting schedule on definite timeout.
That wakes up CPU from idle state and hence may affect the power
consumption. Provide an optional support to use deferred timer
which suites low-power use-cases.
To enable deferred timers,
$ echo 1 > /sys/kernel/mm/ksm/deferred_time
Add dma support for i2c. This function depend on DMA driver.
You can turn on it by write both the dmas and dma-name properties in dts node.
Signed-off-by: Yuan Yao
---
drivers/i2c/busses/i2c-imx.c | 377 +--
1 file changed, 324 insertions(+), 53 deletions(
Changed in v5:
- add "*chan_dev = dma->chan_using->device->dev" for reduce the call time.
- add the test logs.
Changed in v4:
- cancelled "i2c_imx->use_dma".
- changed "Dma" to "DMA".
- add Timeout handling for Transfer complete.
Changed in v3:
- fix a bug when request the dma faild.
- some mi
On Tue 22-07-14 15:47:53, Matthew Wilcox wrote:
> From: Matthew Wilcox
>
> vm_insert_mixed() will fail if there is already a valid PTE at that
> location. The DAX code would rather replace the previous value with
> the new PTE.
>
> Signed-off-by: Matthew Wilcox
This looks good to me although
In the current world, all nonboot cpus are enabled serially during system
resume. System resume sequence is that boot cpu enables nonboot cpu one by
one and then resume devices. Before resuming devices, there are few tasks
assigned to nonboot cpus after they are brought up. This waste cpu usage.
T
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