This patch attempts to remove the hardcoded i2s port number in lpass
driver. Now the the port number comes from the dai id field.
This will allow other SOCs to use different port numbers on the lpass
driver.
Signed-off-by: Srinivas Kandagatla
---
sound/soc/qcom/lpass-cpu.c | 17
This patch removes unnecessary header files in lpass cpu and platform
code.
Signed-off-by: Srinivas Kandagatla
---
sound/soc/qcom/lpass-cpu.c | 6 +-
sound/soc/qcom/lpass-platform.c | 6 --
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/sound/soc/qcom/lpass-cpu.c
Hi All,
This patchset adds apq8016 audio support into lpass driver. Existing Lpass
driver can not be used as-it-is for apq8016 as it contains code specific to
ipq806x. Also the driver only supports single i2s port, single dma channel and
single bitclk control.
APQ8016 has 4 MI2S( Primary,
This patch remove redundant check after request_resource as ioremap would
do the check anyway.
Signed-off-by: Srinivas Kandagatla
---
sound/soc/qcom/lpass-cpu.c | 4
1 file changed, 4 deletions(-)
diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c
index 6698d05..1e284c6
On Thu, Apr 30, 2015 at 10:03:18AM -0700, Andy Lutomirski wrote:
> On Thu, Apr 30, 2015 at 9:52 AM, Luis R. Rodriguez wrote:
> > On Thu, Apr 30, 2015 at 10:59:17AM -0500, Bjorn Helgaas wrote:
> >> [+cc linux-pci]
> >>
> >> Hi Luis,
> >>
> >> On Wed, Apr 29, 2015 at 02:36:08PM -0700, Luis R.
On 04/30/2015 11:10 AM, Daniel J Blueman wrote:
On Wed, Apr 29, 2015 at 2:38 AM, nzimmer wrote:
On 04/28/2015 11:06 AM, Pekka Enberg wrote:
On Tue, Apr 28, 2015 at 5:36 PM, Mel Gorman wrote:
Struct page initialisation had been identified as one of the
reasons why
large machines take a long
28.04.2015 15:58, Jacek Anaszewski пишет:
>>> I tried it with Samsung M0 board and
>>> my leds-aat1290 driver. It didn't work well. And for small delay
>>> intervals it will not have a chance to work reliably with all drivers,
>>> especially the ones which use mutex in their brightness_set op,
>>>
On Thu, Apr 30, 2015 at 9:25 AM, Bastien Nocera wrote:
> On Tue, 2014-10-21 at 10:04 -0700, John Stultz wrote:
>> On Tue, Oct 21, 2014 at 1:49 AM, Bastien Nocera
>> wrote:
>> > Hey,
>> >
>> > GNOME has had discussions with kernel developers in the past, and,
>> > fortunately, in some cases we
From: Xunlei Pang
We may suffer from extra rt overload rq due to the affinity,
so when the affinity of any runnable rt task is changed, we
should check to trigger balancing, otherwise it will cause
some unnecessary delayed real-time response. Unfortunately,
current RT global scheduler does
At Thu, 30 Apr 2015 16:01:31 +0100,
Jonathan McDowell wrote:
>
> On Wed, Apr 29, 2015 at 01:54:57PM +0200, Takashi Iwai wrote:
> > At Wed, 29 Apr 2015 12:28:59 +0100,
> > Jonathan McDowell wrote:
> > >
> > > On Tue, Apr 28, 2015 at 04:43:00PM +0200, Takashi Iwai wrote:
> > > > At Tue, 28 Apr
On Fri, 1 May 2015 00:33:17 +0800
Xunlei Pang wrote:
> From: Xunlei Pang
>
> We may suffer from extra rt overload rq due to the affinity,
> so when the affinity of any runnable rt task is changed, we
> should check to trigger balancing, otherwise it will cause
> some unnecessary delayed
LKML is a very high volume list, if you're seeing problems that were
introduced by a particular patch, it's a good idea to CC the author of
that patch.
/me adds CC, and tags (again) to take a peek.
On Tue, 2015-03-17 at 21:10 +0100, Ronny Meeus wrote:
> I'm using a patched kernel I get from
From: Xunlei Pang
- Remove "has_pushable_tasks(rq)" condition, because for queued p,
"!task_running(rq, p)" and "p->nr_cpus_allowed > 1" implies true
"has_pushable_tasks(rq)".
- Remove "!test_tsk_need_resched(rq->curr)" condition, because
the flag might be set right before the waking up, but we
On Thu, Apr 30, 2015 at 9:52 AM, Luis R. Rodriguez wrote:
> On Thu, Apr 30, 2015 at 10:59:17AM -0500, Bjorn Helgaas wrote:
>> [+cc linux-pci]
>>
>> Hi Luis,
>>
>> On Wed, Apr 29, 2015 at 02:36:08PM -0700, Luis R. Rodriguez wrote:
>> > From: "Luis R. Rodriguez"
>> >
>> > This allows drivers to
On Fri, 1 May 2015 00:33:18 +0800
Xunlei Pang wrote:
> From: Xunlei Pang
>
> - Remove "has_pushable_tasks(rq)" condition, because for queued p,
> "!task_running(rq, p)" and "p->nr_cpus_allowed > 1" implies true
> "has_pushable_tasks(rq)".
This makes sense.
>
> - Remove
Set .irq_set_wake callback to prevent possible issues on wake-up.
This patch was inspired by this commit:
b80eef95beb04760629822fa130aeed54cdfafca
Signed-off-by: Semen Protsenko
---
drivers/gpio/gpio-max732x.c |9 +
1 file changed, 9 insertions(+)
diff --git
MAX732X clears all pending interrupts on I2C read (when interrupts
register is being read). Driver doesn't need to send any ACKs when
interrupt was handled. So replace handle_edge_irq() with
handle_simple_irq().
Using handle_edge_irq() (w/o .irq_ack callback set) may lead to NULL
pointer
It's possible that multiple MAX732X can be hooked up to the same
interrupt line with the processor. So add IRQF_SHARED in requesting irq.
Signed-off-by: Semen Protsenko
---
drivers/gpio/gpio-max732x.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git
struct timeval tv is used to get current time.
32-bit systems using 'struct timeval' will break in the year 2038, so
we have to replace that code with more appropriate types.
Signed-off-by: Ksenija Stanojevic
Reviewed-by: Arnd Bergmann
---
drivers/staging/rts5208/rtsx.h | 25
Ming Lei writes:
> On Wed, Apr 29, 2015 at 12:36 AM, Jeff Moyer wrote:
>> Ming Lei writes:
>>
>>> If there are too many pending per work I/O, too many
>>> high priority work thread can be generated so that
>>> system performance can be effected.
>>>
>>> This patch limits the max pending per
On 30 April 2015 at 18:30, wrote:
> Hello Michal:
>
>> I tried to connect a SPI NOR flash to my sunxi board and due to the
> current
>> sunxi SPI driver limitations it does not work.
>>
>> The SPI driver returns an error when more than 64 bytes are
>> transferred at once
>> due to lack of DMA
Shaohua Li writes:
>> I like the general approach. I do wonder whether we should hold back a
>> single I/O at all times, or whether we should do something similar to
>> what Mike Snitzer did in the dm-mpath driver, where he keeps track of
>> the end position of the last I/O (without holding the
Hi,
On Friday, April 24, 2015 12:02:11 AM Anand Moon wrote:
> Hi Bartlomiej/Kevin,
>
> I have being testing github branch on OdroidXU3 board,
>
> Would you consider testing by applying patch.
>
> https://lkml.org/lkml/2015/1/30/423
>
> On my board it stuck after booting. Below is the console
On Thu, Apr 30, 2015 at 10:59:17AM -0500, Bjorn Helgaas wrote:
> [+cc linux-pci]
>
> Hi Luis,
>
> On Wed, Apr 29, 2015 at 02:36:08PM -0700, Luis R. Rodriguez wrote:
> > From: "Luis R. Rodriguez"
> >
> > This allows drivers to take advantage of write-combining
> > when possible. Ideally we'd
On Thu, Apr 30, 2015 at 9:40 AM, Javier Martinez Canillas
wrote:
> Hello Olof,
>
> On 04/30/2015 05:57 PM, Olof Johansson wrote:
>> On Thu, Apr 30, 2015 at 8:44 AM, Kevin Hilman wrote:
>>> Krzysztof Kozlowski writes:
>>
>> This should fix issue reported by Javier [1][2].
>>
>>
On 04/30/2015 03:53 AM, Juergen Gross wrote:
> Paravirtualized spinlocks produce some overhead even if the kernel is
> running on bare metal. The main reason are the more complex locking
> and unlocking functions. Especially unlocking is no longer just one
> instruction but so complex that it is
On Thu, Apr 30, 2015 at 5:46 AM, Mason wrote:
> Hello,
>
> I wanted to enable high-resolution timers on this Cortex A9 system,
> but it seems there is more to it than just enabling
>
> CONFIG_HIGH_RES_TIMERS=y
>
> (The system is limited to jiffy resolution.)
You might make sure you've got a
Building with the attached random configuration file,
sound/built-in.o: In function `snd_jack_new':
/home/jim/linux/sound/core/jack.c:229: undefined reference to
`input_allocate_device'
/home/jim/linux/sound/core/jack.c:241: undefined reference to
`input_set_capability'
"Aneesh Kumar K.V" writes:
> "Kirill A. Shutemov" writes:
>
>>> @@ -184,3 +185,13 @@ void pmdp_invalidate(struct vm_area_struct *vma,
>>> unsigned long address,
>>> }
>>> #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
>>> #endif
>>> +
>>> +#ifndef __HAVE_ARCH_PMDP_SPLITTING_FLUSH_NOTIFY
>>>
Hello Michal:
> I tried to connect a SPI NOR flash to my sunxi board and due to the
current
> sunxi SPI driver limitations it does not work.
>
> The SPI driver returns an error when more than 64 bytes are
> transferred at once
> due to lack of DMA support.
Wouldn't it be easier to fix the SPI
On 04/30/2015 12:17 PM, Kirill A. Shutemov wrote:
> On Tue, Apr 14, 2015 at 04:56:24PM -0400, Sasha Levin wrote:
>> > This teaches our printing functions about a new family of MM pointer that
>> > it
>> > could now print.
>> >
>> > I've picked %pZ because %pm and %pM were already taken, so I
Hello Olof,
On 04/30/2015 05:57 PM, Olof Johansson wrote:
> On Thu, Apr 30, 2015 at 8:44 AM, Kevin Hilman wrote:
>> Krzysztof Kozlowski writes:
>
> This should fix issue reported by Javier [1][2].
>
> Tested on Chromebook Snow (Exynos 5250). More testing would be great,
>
On Wed, Apr 29, 2015 at 9:27 PM, Trevor Cordes wrote:
> Sorry for the top-posting; Josh Boyer suggested I re-mail this mail
> from last month which didn't get any replies. I'm still having this
> weird kernel bug affecting me and I've bisected it down to like 2-4
> lines of code. (I've thought
On 30 April 2015 at 19:44, gre...@linuxfoundation.org
wrote:
> On Thu, Apr 23, 2015 at 04:09:28PM +0100, Alan Cox wrote:
>> On Thu, 2015-04-23 at 13:43 +, Gujulan Elango, Hari Prasath (H.)
>> wrote:
>> > This patch removes unwanted semicolon around close braces of code blocks
>>
>>
>> The i2o
On Tue, Mar 17, 2015 at 9:10 PM, Ronny Meeus wrote:
> I'm using a patched kernel I get from Monta-Vista, it is based on the
> 3.10 kernel with some RT patches.
> We ported an application from pSOS RTOS to Linux using the
> Xenomai-Mercury (=library to map pSOS task to POSIX threads).
>
> One of
Running a test on a large CPU count box with xfs, I hit a live lock
with the following backtraces on several CPUs:
Call Trace:
[] __const_udelay+0x28/0x30
[] xfs_icsb_lock_cntr+0x2a/0x40 [xfs]
[] xfs_icsb_modify_counters+0x71/0x280 [xfs]
[] xfs_trans_reserve+0x171/0x210
On Thu, Apr 30, 2015 at 12:04:53AM +0900, Ethan Zhao wrote:
> while testing CPU hotplug and MCE with following two scripts,
>
> script 1:
>
> for i in {1..30}; do while :; do ((a=$RANDOM%160)); echo 0 >>
> /sys/devices/system/cpu/cpu${i}/online; echo 1 >>
>
On Thu, Apr 30, 2015 at 3:06 AM, Lee Jones wrote:
> On Wed, 29 Apr 2015, Andrew Bresticker wrote:
>
>> On Wed, Apr 29, 2015 at 11:34 AM, Lee Jones wrote:
>> > On Wed, 29 Apr 2015, Andrew Bresticker wrote:
>> >
>> >> Lee,
>> >>
>> >> On Wed, Apr 29, 2015 at 2:25 AM, Lee Jones wrote:
>> >> > On
[+cc linux-pci]
Hi Luis,
On Wed, Apr 29, 2015 at 02:36:09PM -0700, Luis R. Rodriguez wrote:
> From: "Luis R. Rodriguez"
>
> Now that we have pci_iomap_wc() add the respective devres helpers.
I guess I'm still confused about the relationship between pci_iomap_wc()
and arch_phys_wc_add().
Do
This adds documentation of device tree bindings for the
STM32 reset controller.
Tested-by: Chanwoo Choi
Acked-by: Philipp Zabel
Acked-by: Rob Herring
Signed-off-by: Maxime Coquelin
---
.../devicetree/bindings/reset/st,stm32-rcc.txt | 107 +
1 file changed, 107
This adds documentation of device tree bindings for the
ARM System timer.
Tested-by: Chanwoo Choi
Acked-by: Rob Herring
Signed-off-by: Maxime Coquelin
---
.../devicetree/bindings/arm/armv7m_systick.txt | 26 ++
1 file changed, 26 insertions(+)
create mode 100644
In this seventh round, the series has been rebased on top of 4.1-rc1.
The series also fixes sysrq support in serial driver.
STM32 MCUs are Cortex-M CPU, used in various applications (consumer
electronics, industrial applications, hobbyists...).
Datasheets, user and programming manuals are
The STM32 MCUs family IPs can be reset by accessing some registers
from the RCC block.
The list of available reset lines is documented in the DT bindings.
Tested-by: Chanwoo Choi
Acked-by: Philipp Zabel
Signed-off-by: Maxime Coquelin
---
drivers/reset/Makefile | 1 +
STM32 MCUs feature 16 and 32 bits general purpose timers with prescalers.
The drivers detects whether the time is 16 or 32 bits, and applies a
1024 prescaler value if it is 16 bits.
Reviewed-by: Linus Walleij
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
On Tue, 2014-10-21 at 10:04 -0700, John Stultz wrote:
> On Tue, Oct 21, 2014 at 1:49 AM, Bastien Nocera
> wrote:
> > Hey,
> >
> > GNOME has had discussions with kernel developers in the past, and,
> > fortunately, in some cases we were able to make headway.
> >
> > There are however a number
This drivers adds support to the STM32 USART controller, which is a
standard serial driver.
Tested-by: Chanwoo Choi
Reviewed-by: Peter Hurley
Reviewed-by: Vladimir Zapolskiy
Signed-off-by: Maxime Coquelin
---
drivers/tty/serial/Kconfig | 17 +
drivers/tty/serial/Makefile | 1 +
This adds documentation of device tree bindings for the
STM32 timer.
Tested-by: Chanwoo Choi
Acked-by: Rob Herring
Signed-off-by: Maxime Coquelin
---
.../devicetree/bindings/timer/st,stm32-timer.txt | 22 ++
1 file changed, 22 insertions(+)
create mode 100644
>From Cortex-M reference manuals, the nvic supports up to 240 interrupts.
So the number of entries in vectors table is up to 256.
This patch adds a new config flag to specify the number of external interrupts.
Some ifdeferies are added in order to respect the natural alignment without
wasting too
On Tue, Apr 14, 2015 at 04:56:29PM -0400, Sasha Levin wrote:
> VM_BUG() complements VM_BUG_ON() just like with WARN() and WARN_ON().
>
> This lets us format custom strings to output when a VM_BUG() is hit.
>
> Signed-off-by: Sasha Levin
> ---
> include/linux/mmdebug.h | 10 +-
> 1
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
arch/arm/boot/dts/armv7-m.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/armv7-m.dtsi b/arch/arm/boot/dts/armv7-m.dtsi
index 5a660d0..b1ad7cf 100644
--- a/arch/arm/boot/dts/armv7-m.dtsi
+++
The STMicrolectornics's STM32F429 MCU has the following main features:
- Cortex-M4 core running up to @180MHz
- 2MB internal flash, 256KBytes internal RAM
- FMC controller to connect SDRAM, NOR and NAND memories
- SD/MMC/SDIO support
- Ethernet controller
- USB OTFG FS & HS controllers
-
This patch adds a new config for STM32 MCUs.
STM32F429 Discovery board boots successfully with this config applied.
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
arch/arm/configs/stm32_defconfig | 69
1 file changed, 69 insertions(+)
Add a MAINTAINER entry covering all STM32 machine and drivers files.
Signed-off-by: Maxime Coquelin
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2e5bbc0..858d821 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1479,6 +1479,14 @@ F:
STMicrolectronics's STM32 series is a family of Cortex-M
microcontrollers. It is used in various applications, and
proposes a wide range of peripherals.
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
Documentation/arm/stm32/overview.txt | 32 ++
This adds documentation of device tree bindings for the
STM32 USART
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
.../devicetree/bindings/serial/st,stm32-usart.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
This patch adds clocksource support for ARMv7-M's System timer,
also known as SysTick.
Tested-by: Chanwoo Choi
Acked-by: Daniel Lezcano
Signed-off-by: Maxime Coquelin
---
drivers/clocksource/Kconfig | 7
drivers/clocksource/Makefile | 1 +
When Kernel is executed in place from ROM, the symbol addresses can be
lower than the page offset.
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
scripts/link-vmlinux.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/link-vmlinux.sh
On Tue, Apr 14, 2015 at 04:56:25PM -0400, Sasha Levin wrote:
> This lets us use regular string formatting code to dump VMAs, use it
> in VM_BUG_ON_VMA instead of just printing it to screen as well.
>
> Signed-off-by: Sasha Levin
> ---
> include/linux/mmdebug.h |8 ++--
> lib/vsprintf.c
On Tue, Apr 14, 2015 at 04:56:24PM -0400, Sasha Levin wrote:
> This teaches our printing functions about a new family of MM pointer that it
> could now print.
>
> I've picked %pZ because %pm and %pM were already taken, so I figured it
> doesn't really matter what we go with. We also have the
The "cpus" clock is the clock for the embedded processor in the A80.
It is also part of the PRCM clock tree.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/Makefile| 2 +-
drivers/clk/sunxi/clk-sun9i-cpus.c
On 30 April 2015 at 16:23, Jean Delvare wrote:
> A 32-bit entry point to a DMI table says how many structures the table
> contains. The SMBIOS specification explicitly says that end-of-table
> markers should be ignored if they are not actually at the end of the
> DMI table. So only honor the
On Wed, Apr 29, 2015 at 2:38 AM, nzimmer wrote:
On 04/28/2015 11:06 AM, Pekka Enberg wrote:
On Tue, Apr 28, 2015 at 5:36 PM, Mel Gorman wrote:
Struct page initialisation had been identified as one of the
reasons why
large machines take a long time to boot. Patches were posted a long
time
This adds the PRCM clocks and reset controls to the A80 dtsi.
The list of apbs clock gates is incomplete. Tests show that bits 0~20
are mutable. We will need documents from Allwinner to complete the
support.
Also update clock and reset phandles for r_uart.
Signed-off-by: Chen-Yu Tsai
---
The main (24MHz) clock on the A80 is configurable via the PRCM address
space. The low power/speed (32kHz) clock is from an external chip, the
AC100.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git
This patch adds support for the PRCM on the A80 SoC. There is little
to no document for this at the moment. Only register offsets are
available. However with some testing, the clock and reset controls
seem to be the similar to the ones on the A31.
One thing that needs verifying is whether the
This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 5 +
2 files changed, 6 insertions(+)
diff --git
Hi everyone,
This is v2 of the Allwinner A80 PRCM support series. Thanks to
Allwinner updating their documents, we can now support the essential
parts of the PRCM.
This series adds support for the Power Reset and Clock Management
module on Allwinner's A80 SoC. The PRCM manages clocks and resets
On Tuesday, April 28, 2015 05:23:56 PM Yingjoe Chen wrote:
> From: Hongzhou Yang
>
>
> Matthias,
>
> Since mt8135 pinctrl node patch is not in v4.1-rc1, I'd like to make some
> minor change to follow dts convention.
>
> Let me know what you think.
> Thanks.
>
> Joe.C
>
>
On 04/29/2015 06:26 PM, Andrew Morton wrote:
On Fri, 17 Apr 2015 14:37:16 -0400 Chris Metcalf wrote:
This change allows some cores to be excluded from running the
smp_hotplug_thread tasks. The following commit to update
kernel/watchdog.c to use this functionality is the motivating
example,
This patch series addresses limitations in strncpy() and strlcpy();
both the old APIs are unpleasant, as Linus nicely summarized here
a couple of days ago:
https://lkml.org/lkml/2015/4/28/570
and of course as other folks (Greg K-H and Linus again) said last year:
The strscpy() API is intended to be used instead of strlcpy(),
and instead of most uses of strncpy().
- The API provides an easy way to check for destination buffer overflow:
a -E2BIG error return value.
- By default, truncation causes the destination buffer to be the
empty string, so users
Now that strscpy() is a standard API, remove the local copy.
Signed-off-by: Chris Metcalf
---
arch/tile/gxio/mpipe.c | 33 -
1 file changed, 4 insertions(+), 29 deletions(-)
diff --git a/arch/tile/gxio/mpipe.c b/arch/tile/gxio/mpipe.c
index
Added the x86 implementation of word-at-a-time to the
generic version, which previously only supported big-endian.
Omitted the x86-specific load_unaligned_zeropad(), which in
any case is also not present for the existing BE-only
implementation of a word-at-a-time, and is only used under
On Wed, Apr 29, 2015 at 02:44:21PM -0700, Luis R. Rodriguez wrote:
> From: "Luis R. Rodriguez"
So this one is missing a commit message too but we need to talk about
this. Why are we adding __read_mostly in the macro? This would put every
param declared this way into
Daniel Phillips wrote:
On 04/30/2015 07:28 AM, Howard Chu wrote:
You're reading into it what isn't there. Spreading over the disk isn't (just)
about avoiding
fragmentation - it's about delivering consistent and predictable latency. It is
undeniable that if
you start by only allocating from
"Kirill A. Shutemov" writes:
>> @@ -184,3 +185,13 @@ void pmdp_invalidate(struct vm_area_struct *vma,
>> unsigned long address,
>> }
>> #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
>> #endif
>> +
>> +#ifndef __HAVE_ARCH_PMDP_SPLITTING_FLUSH_NOTIFY
>> +#ifdef CONFIG_TRANSPARENT_HUGEPAGE
>> +void
[+cc linux-pci]
Hi Luis,
On Wed, Apr 29, 2015 at 02:36:08PM -0700, Luis R. Rodriguez wrote:
> From: "Luis R. Rodriguez"
>
> This allows drivers to take advantage of write-combining
> when possible. Ideally we'd have pci_read_bases() just
> peg an IORESOURCE_WC flag for us
This makes it sound
Hi Ted,
On 04/30/2015 07:57 AM, Theodore Ts'o wrote:
> This is one of the reasons why I find head-to-head "competitions"
> between file systems to be not very helpful for anything other than
> benchmarketing. It's almost certain that the benchmark won't be
> "fair" in some way, and it doesn't
Hi Krzystof,
Krzysztof Kozlowski writes:
> 2015-04-02 23:36 GMT+09:00 Krzysztof Kozlowski :
>> On Arndale Octa the S2MPS11 RTC alarm interrupt was not handled at all
>> because of wrong configuration of interrupt and gpx3-2.
>> 1. Interrupt is signaled by falling edge.
>> 2. This GPIO line is
On Thu, Apr 30, 2015 at 8:44 AM, Kevin Hilman wrote:
> Krzysztof Kozlowski writes:
>
>> 2015-04-30 2:31 GMT+09:00 Kevin Hilman :
>>> Krzysztof Kozlowski writes:
>>>
After adding display power domain for Exynos5250 in commit
2d2c9a8d0a4f ("ARM: dts: add display power domain for
Hi,
On Tue, Apr 28, 2015 at 10:23:06PM +0200, Marek Belisko wrote:
> Without MODULE_ALIAS bq27x00_battery module won't get loaded
> automatically.
>
> Signed-off-by: Marek Belisko
> ---
> drivers/power/bq27x00_battery.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git
On Thu, Apr 30, 2015 at 03:52:17PM +0200, Arnd Bergmann wrote:
> On Thursday 30 April 2015 14:13:45 Will Deacon wrote:
> > On Thu, Apr 30, 2015 at 02:03:00PM +0100, Arnd Bergmann wrote:
> > > On Thursday 30 April 2015 12:46:15 Will Deacon wrote:
> > > > Cache sync doesn't exist in the
Am 30.04.2015 um 14:40 schrieb Paolo Bonzini:
> Signed-off-by: Paolo Bonzini
Reviewed-by: Christian Borntraeger
but no way to test it
> ---
> arch/powerpc/kvm/booke.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/kvm/booke.c
Hi,
On Tue, Apr 14, 2015 at 09:09:20PM -, Thomas Gleixner wrote:
> The return value of hrtimer_start() tells whether the timer was
> inactive or active already when hrtimer_start() was called.
>
> The code emits a bogus warning if the timer was active already
> claiming that the timer could
Thanks you. I will add linux-pm also in CC list going forward.
> On Wed, Apr 29, 2015 at 06:09:29AM +, Pallala, Ramakrishna wrote:
> > It's been almost 45 days since I submitted this patch and I did not
> > receive any feedback from you.
> > Can you take a look at this patch now?
>
> Right,
Krzysztof Kozlowski writes:
> 2015-04-30 2:31 GMT+09:00 Kevin Hilman :
>> Krzysztof Kozlowski writes:
>>
>>> After adding display power domain for Exynos5250 in commit
>>> 2d2c9a8d0a4f ("ARM: dts: add display power domain for exynos5250") the
>>> display on Chromebook Snow and others stopped
Kukjin Kim writes:
> Javier Martinez Canillas wrote:
>>
>> Hello Kukjin,
>>
> Hi,
>
>> On 04/16/2015 09:40 AM, Javier Martinez Canillas wrote:
>> >
>> > On 04/12/2015 10:30 PM, Javier Martinez Canillas wrote:
>> >> Commit ea08de16eb1b ("ARM: dts: Add DISP1 power domain for exynos5420")
>> >>
On Tue, Apr 14, 2015 at 04:56:23PM -0400, Sasha Levin wrote:
> Format various flags to a string buffer rather than printing them. This is
> a helper for later.
>
> Signed-off-by: Sasha Levin
> ---
> mm/debug.c | 35 +++
> 1 file changed, 35 insertions(+)
>
>
On 4/11/2015 5:32 PM, Bjorn Andersson wrote:
Add device tree binding documentation for the Qualcom Shared Memory
manager.
Signed-off-by: Bjorn Andersson
---
Changes since v1:
- None
.../devicetree/bindings/soc/qcom/qcom,smem.txt | 49 ++
1 file changed, 49
v2 of this patch was sent (rebased on top of recent sources).
On Thu, Apr 30, 2015 at 6:28 PM, Semen Protsenko
wrote:
> There is pm_qos_add_request() being executed on serial_omap_probe(),
> which stores ">pm_qos_request" from omap-serial driver to
>
There is pm_qos_add_request() being executed on serial_omap_probe(),
which stores ">pm_qos_request" from omap-serial driver to
"pm_qos_array[PM_QOS_CPU_DMA_LATENCY]->constraints". If
serial_omap_probe() fails after pm_qos_add_request() (e.g. on
uart_add_one_port() call), pm_qos_array still keeping
Clock rates are stored in an unsigned long field, but ->determine_rate()
(which returns a rounded rate from a requested one) returns a long
value (errors are reported using negative error codes), which can lead
to long overflow if the clock rate exceed 2Ghz.
Change ->determine_rate() prototype to
On 4/30/2015 6:12 AM, Peter De Schrijver wrote:
> On Wed, Apr 29, 2015 at 01:21:46PM -0400, Rhyland Klein wrote:
>> From: Bill Huang
>>
>> Add logic which (if specified for a pll) can verify that a PLL is set
>> to the proper default value and if not can set it. This can be
>> specified per PLL
Clock rates are stored in an unsigned long field, but ->round_rate()
(which returns a rounded rate from a requested one) returns a long
value (errors are reported using negative error codes), which can lead
to long overflow if the clock rate exceed 2Ghz.
Change ->round_rate() prototype to return
Hello,
As previously discussed in this thread [1], this series is changing
clk_ops' ->round_rate()/->determine_rate() prototypes to avoid long
overflows when the returned rate is exceeding 2Ghz.
Most of those changes have been compile-tested, but none of them have
been tested on real hardware
There is pm_qos_add_request() being executed on serial_omap_probe(),
which stores ">pm_qos_request" from omap-serial driver to
"pm_qos_array[PM_QOS_CPU_DMA_LATENCY]->constraints". If
serial_omap_probe() fails after pm_qos_add_request() (e.g. on
uart_add_one_port() call), pm_qos_array still keeping
Hi,
On Tue, Apr 21, 2015 at 11:51:32AM -0700, Florian Fainelli wrote:
> On 24/03/15 17:17, Florian Fainelli wrote:
> > Hi all,
> >
> > This patch series adds support for the BCM6328-style software reset hardware
> > block commonly found on Broadcom BCM63xx DSL SoCs.
>
> Looks like we can
Hello,
I am hoping we can have a scaling track this year. The purpose of this
email is to 1) confirm some of the key participants, 2) suggestions for
other key participants and 3) more topics so that we can have a big
enough pool to screen correctly for what's really worth discussing.
I have
On 04/30/2015 07:33 AM, Mike Galbraith wrote:
> Well ok, let's forget bad blood, straw men... and answering my question
> too I suppose. Not having any sexy IO gizmos in my little desktop box,
> I don't care deeply which stomps the other flat on beastly boxen.
I'm with you, especially the
Hello Kevin,
On 04/30/2015 04:59 PM, Kevin Hilman wrote:
> Javier Martinez Canillas writes:
>>
>> The regression on Exynos5420/5422/5800 that has been for a while is fixed
>> by "ARM: dts: Make DP a consumer of DISP1 power domain on Exynos5420" [0]
>> which has been posted many weeks ago.
>
>
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