The watchdog, the reset controller, the RTC, the shutdown controller, the
timer counters and the LCD PWM need the slow clock, add it to the currently
defined nodes.
Signed-off-by: Alexandre Belloni
---
arch/arm/boot/dts/sama5d2.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
On Wed, Feb 25, 2015 at 10:02:50PM +0100, Sebastian Andrzej Siewior wrote:
> >+static inline int swait_active(struct swait_queue_head *q)
> >+{
> >+return !list_empty(>task_list);
>
> In RT there was a smp_mb() which you dropped and I assume you had
> reasons for it.
Yeah, RT didn't have a
Signed-off-by: Yakir Yang
---
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h| 16
3 files
On Thu, Aug 06, 2015 at 03:44:54PM -0400, kan.li...@intel.com wrote:
> From: Kan Liang
>
> Add tests in tests/parse-events.c to check call-graph and time option
>
> Signed-off-by: Kan Liang
Acked-by: Jiri Olsa
thanks,
jirka
--
To unsubscribe from this list: send the line "unsubscribe
The recent BlackHat 2015 presentation "The Memory Sinkhole"
mentions that the IDT limit is zeroed on entry to SMM.
This is not documented, and must have changed some time after 2010
(see http://www.ssi.gouv.fr/uploads/IMG/pdf/IT_Defense_2010_final.pdf).
KVM was not doing it, but the fix is easy.
On Fri, Aug 07, 2015 at 10:41:57AM +0200, Sebastian Andrzej Siewior wrote:
> This DMA driver is used by 8250-omap on DRA7-evm. There is one
> requirement that is to pause a transfer. This is currently used on the RX
> side. It is possible that the UART HW aborted the RX (UART's RX-timeout)
> but
On Thu, Aug 06, 2015 at 03:44:53PM -0400, kan.li...@intel.com wrote:
SNIP
> |
> ---f3
>|
>|--0.53%-- f2
>| f1
>| main
>| __libc_start_main
>|
>
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works prefectly on my
rk3288 sdk board.
Signed-off-by: Yakir Yang
---
Changes in v2: None
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
Besides TRM indicate that if HPD_STATUS(RO) is 0, AUX CH will not
work, so we need to give a force hpd action to set HPD_STATUS manually.
Signed-off-by: Yakir Yang
---
Changes in v2: None
On Thu, Aug 06, 2015 at 03:44:52PM -0400, kan.li...@intel.com wrote:
> From: Kan Liang
>
> Move callchain option parse related code to util.c
little nore about the reason would be nice ;-)
looks ok, but the python test is still failing,
the reason is the perf_counts struct objects and
On Wed, 2015-08-05 at 23:31 +0100, Russell King - ARM Linux wrote:
> On Wed, Aug 05, 2015 at 08:44:11PM +0200, Matthias Brugger wrote:
> > On Tuesday, July 14, 2015 01:18:26 PM Yingjoe Chen wrote:
> > > This series add SMP brinup support for MediaTek SoCs. This is based
> > > on v4.2-rc1 and
This function clears the reset the AUART unit is in after system start
to make it work.
Signed-off-by: Juergen Borleis
---
drivers/tty/serial/mxs-auart.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index
Whenever the UART device driver gets closed from userland, the driver
disables the UART unit and then stops the clocks to save power.
The bit which disabled the UART unit is described as:
"UART Enable. If this bit is set to 1, the UART is enabled. Data
transmission and reception occurs for
On Fri, Aug 07, 2015 at 12:03:24PM +0200, Tomasz Nowicki wrote:
> >@@ -670,6 +671,8 @@ static struct irq_domain
> >*pci_host_bridge_msi_domain(struct pci_bus *bus)
> > * should be called from here.
> > */
> > d = pci_host_bridge_of_msi_domain(bus);
> >+if (!d)
> >+d
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v2: None
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v2:
- Take Jingoo Han suggest, cause I jsut
On 07.08.15 10:09:04, Tomasz Nowicki wrote:
> On 07.08.2015 02:33, David Daney wrote:
...
> >+#else
> >+
> >+static int bgx_init_acpi_phy(struct bgx *bgx)
> >+{
> >+return -ENODEV;
> >+}
> >+
> >+#endif /* CONFIG_ACPI */
> >+
> > #if IS_ENABLED(CONFIG_OF_MDIO)
> >
> > static int
Previously, we use radix tree to index all registered page entries for
atomic file, but now we only use radix tree to see whether current page
is indexed or not, since the other user of radix tree is gone in commit
042b7816aaeb ("f2fs: remove unnecessary call to invalidate inmemory pages").
So in
In recover_orphan_inode, if f2fs_iget failed, we change to report the
error number to its caller instead of bug_on.
Signed-off-by: Chao Yu
---
fs/f2fs/checkpoint.c | 25 ++---
fs/f2fs/f2fs.h | 2 +-
fs/f2fs/super.c | 4 +++-
3 files changed, 22 insertions(+), 9
On 07-08-15, 12:34, Bartlomiej Zolnierkiewicz wrote:
> > I would suggest you sending such patches as reply to the earlier
> > threads only, instead of a new chain. This will save your time.
>
> Please explain it more. This patch needs to be first for cpufreq-dt
> switch to be complete.
Hi all
This patch is submitted by Yunlei He originally, but it's not complete one,
so I modified it and add some description, then resubmit it.
>From 3f8de7fe93354215b9b12293302a0a999cf3888a Mon Sep 17 00:00:00 2001
From: Yunlei He
Date: Wed, 29 Jul 2015 15:10:24 +0800
Subject: [PATCH 2/4]
After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
Signed-off-by: Yakir Yang
---
Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
avoid using some uncommon style like
An exit label which does nothing except return, is not worth having. So
remove it.
Signed-off-by: Sudip Mukherjee
---
drivers/staging/rtl8188eu/core/rtw_recv.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/rtl8188eu/core/rtw_recv.c
Re-arrange the code to directly return success or failure, thus removing
the variable used in the function.
Signed-off-by: Sudip Mukherjee
---
drivers/staging/rtl8188eu/os_dep/recv_linux.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git
The function rtw_init_recvframe() was not being used.
Signed-off-by: Sudip Mukherjee
---
drivers/staging/rtl8188eu/core/rtw_recv.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/staging/rtl8188eu/core/rtw_recv.c
b/drivers/staging/rtl8188eu/core/rtw_recv.c
index
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
The return value of rtw_os_recv_resource_alloc() is never checked, so
make it as void. Moreover as of now the function can not fail.
Signed-off-by: Sudip Mukherjee
---
drivers/staging/rtl8188eu/core/rtw_recv.c | 2 +-
drivers/staging/rtl8188eu/include/recv_osdep.h | 2 +-
_RECV_OSDEP_C_ was only defined here but never checked anywhere.
Signed-off-by: Sudip Mukherjee
---
drivers/staging/rtl8188eu/os_dep/recv_linux.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/staging/rtl8188eu/os_dep/recv_linux.c
b/drivers/staging/rtl8188eu/os_dep/recv_linux.c
Multiple blank lines is against the kernel coding style and checkpatch
complains for that.
Signed-off-by: Sudip Mukherjee
---
drivers/staging/rtl8188eu/core/rtw_recv.c | 26 --
1 file changed, 26 deletions(-)
diff --git a/drivers/staging/rtl8188eu/core/rtw_recv.c
The function rtw_os_recv_resource_alloc() only uses the argument
struct recv_frame *. So remove the other unused argument.
Signed-off-by: Sudip Mukherjee
---
drivers/staging/rtl8188eu/core/rtw_recv.c | 2 +-
drivers/staging/rtl8188eu/include/recv_osdep.h | 3 +--
fill_zero can fail due to a lot of reason, but previously we do not handle
its return value, so its callers such as punch_hole/f2fs_zero_range may
report success, but actually can fail because of error occurs inside
fill_zero.
This patch fixes to report correct return value of fill_zero.
On 08/07/2015 11:44 AM, Peter Ujfalusi wrote:
> On 08/07/2015 11:41 AM, Sebastian Andrzej Siewior wrote:
>> This DMA driver is used by 8250-omap on DRA7-evm. There is one
>> requirement that is to pause a transfer. This is currently used on the RX
>> side. It is possible that the UART HW aborted
On 08/07/2015 09:59 AM, Andrzej Hajda wrote:
The patch was generated using fixed coccinelle semantic patch
scripts/coccinelle/api/memdup.cocci [1].
[1]: http://permalink.gmane.org/gmane.linux.kernel/2014320
Signed-off-by: Andrzej Hajda
Acked-by: Daniel Borkmann
Not sure where the rest of
Hi,
On Friday, August 07, 2015 09:11:28 AM Viresh Kumar wrote:
> Hi,
>
> I would suggest you sending such patches as reply to the earlier
> threads only, instead of a new chain. This will save your time.
Please explain it more. This patch needs to be first for cpufreq-dt
switch to be
On Thu, 06 Aug 2015, Vlastimil Babka wrote:
...
> >
> >diff --git a/fs/proc/task_mmu.c b/fs/proc/task_mmu.c
> >index ca1e091..38d69fc 100644
> >--- a/fs/proc/task_mmu.c
> >+++ b/fs/proc/task_mmu.c
> >@@ -579,6 +579,7 @@ static void show_smap_vma_flags(struct seq_file *m,
> >struct vm_area_struct
On Fri, Aug 07, 2015 at 08:09:39AM +0100, Chung-Yih Wang (王崇懿) wrote:
> As there could be more thermal zones on a system and
> more variety in thermal governors provided in kernel,
> this patch provides flexibility of governor selection
> for a thermal zone declared in device tree.
>
> Change-Id:
Hi,
this PowerBook G4 was running 3.16 for a while but now I wanted to upgrade
to latest mainline. However, during bootup the following happens:
===
[2.237102] ata1: PATA max UDMA/100 irq 39
[2.401708] ata1.00: ATA-8: SAMSUNG HM061GC, LR100-10, max UDMA/100
[
> -Original Message-
> From: KY Srinivasan
> Sent: Friday, August 7, 2015 2:28
> To: Dexuan Cui ; David Miller
> Cc: o...@aepfle.de; gre...@linuxfoundation.org; jasow...@redhat.com;
> driverdev-de...@linuxdriverproject.org; linux-kernel@vger.kernel.org;
> step...@networkplumber.org;
On 08/06/2015 01:22 PM, Govindraj Raja wrote:
From: Ezequiel Garcia
The Pistachio SoC provides four general purpose timers, and allow
to implement a clocksource driver.
This driver can be used as a replacement for the MIPS GIC and MIPS R4K
clocksources and sched clocks, which are clocked from
This patch increments privatecnt value and set DMA_PRIVATE in device
caps in dma_request_slave_channel() function. This is needed to keep
privatecnt increment/decrement balance.
As function dma_release_channel() decrements privatecnt counter, we need
to increment it when channel is requested.
> From: KY Srinivasan
> Sent: Friday, August 7, 2015 1:50
> To: Dexuan Cui ; David Miller
> Cc: o...@aepfle.de; gre...@linuxfoundation.org; jasow...@redhat.com;
> driverdev-de...@linuxdriverproject.org; linux-kernel@vger.kernel.org;
> step...@networkplumber.org; stefa...@redhat.com;
Add Freescale LS1021A initial defconfig file.
The LS1021A SoC is a dual-core Cortex-A7 based processor.
LS1021A has some special configure options against common V7 SOCs,
such as CONFIG_THUMB2_KERNEL, CONFIG_VMSPLIT_2G, CONFIG_VFP...
Enable I2C, LPUART, eDMA, WDT, GIANFAR, Sound, DSPI at
On Fri, Aug 7, 2015 at 9:59 AM, Andrzej Hajda wrote:
> The patch was generated using fixed coccinelle semantic patch
> scripts/coccinelle/api/memdup.cocci [1].
>
> [1]: http://permalink.gmane.org/gmane.linux.kernel/2014320
>
> Signed-off-by: Andrzej Hajda
Thanks, will apply and queue for v4.3.
On 06/08/2015 19:13, Nicholas Krause wrote:
> diff --git a/arch/powerpc/kvm/mpic.c b/arch/powerpc/kvm/mpic.c
> index 6249cdc..5a18859 100644
> --- a/arch/powerpc/kvm/mpic.c
> +++ b/arch/powerpc/kvm/mpic.c
> @@ -1641,13 +1641,16 @@ static void mpic_destroy(struct kvm_device *dev)
> static int
Hugetlbfs pages will get a refcount in get_any_page() or madvise_hwpoison()
if soft offline through madvise. The refcount which held by soft offline
path should be released if fail to isolate hugetlbfs pages. This patch fix
it by reducing a refcount for both isolate successfully and failure.
On 7 August 2015 at 10:25, Martin Sperl wrote:
> On 8/6/2015 23:33, Russell King - ARM Linux wrote:
>>
>> On Thu, Aug 06, 2015 at 06:14:00PM +0200, Geert Uytterhoeven wrote:
>>>
>>>
>>> Irrespective of the dummy bytes.
>>> What if the spi device is not a FLASH ROM, but some other device,
>>>
After try to drain pages from pagevec/pageset, we try to get reference
count of the page again, however, the reference count of the page is
not reduced if the page is still not on LRU list. This patch fix it by
adding the put_page() to drop the page reference which is from
__get_any_page().
On 07/08/2015 09:46, Wu, Feng wrote:
> If I understand it correctly, here you reserve the low part of the routing
> table, and insert entries with KVM_IRQ_ROUTING_MSI type in them,
> then you use this as a hint to KVM to set the EOI bit map. I have two
> concerns:
>
> - Currently, GSI 2 is used
From: Maoguang Meng
This patch implement irq_set_wake and add suspend resume feature.
Signed-off-by: Maoguang Meng
---
drivers/pinctrl/mediatek/pinctrl-mt8173.c | 1 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 78 +--
On (08/07/15 18:37), Sergey Senozhatsky wrote:
[..]
> > Signed-off-by: Joonsoo Kim
>
> Acked-by: Sergey Senozhatsky
Andrew, my apologies, can we hold on a bit with my Acked-by. I
need more time to think about the issue -- do we actually have
one or we don't.
It seems that to be on a safe side
On Fri 2015-08-07 11:58 +0200, Ulrich Obergfell wrote:
>
> Signed-off-by: Ulrich Obergfell
> ---
> arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c
> b/arch/x86/kernel/cpu/perf_event_intel.c
On Fri 2015-08-07 11:58 +0200, Ulrich Obergfell wrote:
> Rename watchdog_suspend() to lockup_detector_suspend() and
> watchdog_resume() to lockup_detector_resume() to avoid
> confusion with the watchdog subsystem and to be consistent
> with the existing name lockup_detector_init().
>
> Also
This patch adds platform notifier for dma-coherent requirement.
Structure arm_coherent_dma_ops is used instead of arm_dma_ops.
Signed-off-by: Alison Wang
---
arch/arm/mach-imx/mach-ls1021a.c | 30 ++
1 file changed, 30 insertions(+)
diff --git
On 29.07.2015 12:08, Hanjun Guo wrote:
From: Suravee Suthikulpanit
This patch introduces pci_host_bridge_acpi_msi_domain(), which queries
a GIC MSI irq-domain token and use it to retrieve an irq_domain with
DOMAIN_BUS_PCI_MSI bus type, and bind it to PCI host-bridge.
Signed-off-by: Suravee
On (08/07/15 18:14), Sergey Senozhatsky wrote:
> hm... I need to think about it more.
>
> we do wake_up every time we put stream back to the list
>
> zcomp_strm_multi_release():
>
> spin_lock(>strm_lock);
> if (zs->avail_strm <= zs->max_strm) {
> list_add(>list,
Signed-off-by: Ulrich Obergfell
---
arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c
b/arch/x86/kernel/cpu/perf_event_intel.c
index 0357bf7..abb25c3 100644
---
This small series follows up to patch discussion related
to $subject patch series which is now in linux-next at:
- introduce watchdog_park_threads() and watchdog_unpark_threads()
Rename watchdog_suspend() to lockup_detector_suspend() and
watchdog_resume() to lockup_detector_resume() to avoid
confusion with the watchdog subsystem and to be consistent
with the existing name lockup_detector_init().
Also provide comment blocks to explain the watchdog_running
and
Hi Heiko,
pclk_pd_pmu needs to keep running and with the upcoming gpio clock
handling this is not always the case anymore. So add it to the list
of critical clocks for now.
From: Heiko Stuebner
Signed-off-by: Lin Huang
is it the right way? if it still can not meet the requirement,
On 7 August 2015 at 11:37, Matt Fleming wrote:
> On Fri, 07 Aug, at 11:00:17AM, Ard Biesheuvel wrote:
>>
>> The EFI memory types are not exclusive, and so many regions will have
>> all of the above set. The UEFI spec does not define how to interpret
>> these superimposed attributes, it is up to
On Fri, 07 Aug, at 09:37:00AM, Matt Fleming wrote:
> From: "Jonathan (Zhixiong) Zhang"
>
> Table 8 of UEFI 2.5 section 2.3.6.1 defines mappings from EFI
> memory types to MAIR attribute encodings for arm64.
>
> If the physical address has memory attributes defined by EFI
> memmap as
On 08/07/2015 11:41 AM, Sebastian Andrzej Siewior wrote:
> This DMA driver is used by 8250-omap on DRA7-evm. There is one
> requirement that is to pause a transfer. This is currently used on the RX
> side. It is possible that the UART HW aborted the RX (UART's RX-timeout)
> but the DMA controller
Tomer Barletz writes:
> This fixes the following warning seen with GCC v5.1:
> warning: logical not is only applied to the left hand side of
> comparison [-Wlogical-not-parentheses].
>
> Signed-off-by: Tomer Barletz
> ---
> drivers/scsi/be2iscsi/be_main.c | 2 +-
> 1 file changed, 1
On Thu, 6 Aug 2015, Boris Ostrovsky wrote:
> On 08/06/2015 01:04 PM, Robert Richter wrote:
> > Boris,
> >
> > we are working on acpi pci support for arm64. For this we are enabling
> > PCI_MMCONFIG on arm64 which breaks compiling drivers/xen/pci.c.
> >
> > Looking into it there is x86 code in
On 29/07/15 23:46, Stephen Boyd wrote:
On 07/28/2015 05:54 AM, Srinivas Kandagatla wrote:
+
+panel_3p3v: panel_3p3v {
+compatible = "regulator-fixed";
+pinctrl-0 = <_en_gpios>;
+pinctrl-names = "default";
+regulator-min-microvolt =
It is no need to check the packet[0] for sanity check when doing
elantech_packet_check_v4() function for fw_version = 0x470f01 touchpad.
Signed-off by: Duson Lin
---
drivers/input/mouse/elantech.c | 20
drivers/input/mouse/elantech.h |1 +
2 files changed, 21
On Fri, 07 Aug, at 11:00:17AM, Ard Biesheuvel wrote:
>
> The EFI memory types are not exclusive, and so many regions will have
> all of the above set. The UEFI spec does not define how to interpret
> these superimposed attributes, it is up to the OS to decide on a
> consistent approach.
>
> For
On 08/05/2015 03:01 PM, Vlastimil Babka wrote:
> Reposting due to lack of feedback in May. I hope at least patches 1 and 2
> could be merged as they are IMHO bugfixes. 3 and 4 is optional but IMHO
> useful.
>
> Changes since v2:
> o Rebase on next-20150805.
> o This means that /proc/pid/maps has
On (08/07/15 18:19), Sergey Senozhatsky wrote:
> [..]
> > hm... we also can simply forbid downgrading a multi stream backend
> > to a single stream (in terms of performance it is much slower
> > than a real single steam anyway). will this do the trick? if we
> > have more than 1 stream and idle
On (08/07/15 17:03), Joonsoo Kim wrote:
> Currently, when we enter the wait state due to lack of idle stream,
> we check idle_strm list without holding the lock in expanding of
> wait_event define. In this case, some one can see stale value and
> process could fall into wait state without any
On 08/07/2015, 11:29 AM, Haibo Chen wrote:
> Currently one mrq->data maybe execute dma_map_sg() twice
> when mmc subsystem prepare over one new request, and the
> following log show up:
> sdhci[sdhci_pre_dma_transfer] invalid cookie: 24, next-cookie 25
Thanks, I will test it shortly.
> @@
By combining PMU, kprobe and eBPF program together, many interesting things
can be done. For example, by probing at sched:sched_switch we can
measure IPC changing between different processes by watching 'cycle' PMU
counter; by probing at entry and exit points of a kernel function we are
able to
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Lin Huang
Reviewed-by: Heiko Stuebner
---
Changes in v4:
-delete some unrelated new blank line
drivers/pinctrl/pinctrl-rockchip.c | 55
On 29/07/15 23:55, Stephen Boyd wrote:
On 07/28/2015 05:53 AM, Srinivas Kandagatla wrote:
+
+sdcc4_pwrseq:pwrseq {
Missing space here between label and node name.
I will fix this in next version.
+compatible = "mmc-pwrseq-simple";
+reset-gpios = <_gpio 43
pclk_pd_pmu needs to keep running and with the upcoming gpio clock
handling this is not always the case anymore. So add it to the list
of critical clocks for now.
From: Heiko Stuebner
Signed-off-by: Lin Huang
---
Changes in v4:
- Add From: Heiko Stuebner
drivers/clk/rockchip/clk-rk3288.c | 1
Am Donnerstag, den 06.08.2015, 19:33 +0100 schrieb Mark Brown:
> On Thu, Aug 06, 2015 at 06:38:24PM +0200, Philipp Zabel wrote:
> > This allows to set the regulator-ramp-delay in the device tree.
>
> > @@ -433,6 +433,7 @@ static struct regulator_ops da9063_buck_ops = {
> > .is_enabled
Currently one mrq->data maybe execute dma_map_sg() twice
when mmc subsystem prepare over one new request, and the
following log show up:
sdhci[sdhci_pre_dma_transfer] invalid cookie: 24, next-cookie 25
In this condition, mrq->date map a dma-memory(1) in sdhci_pre_req
for the first time,
On 8/7/15 3:46 PM, Naoya Horiguchi wrote:
> On Thu, Aug 06, 2015 at 04:09:37PM +0800, Wanpeng Li wrote:
>> After try to drain pages from pagevec/pageset, we try to get reference
>> count of the page again, however, the reference count of the page is
>> not reduced if the page is still not on
On Thu, Aug 06, 2015 at 06:14:12PM -0400, Steven Rostedt wrote:
> On Thu, 6 Aug 2015 23:36:49 +0200
> Peter Zijlstra wrote:
>
> > On Thu, Aug 06, 2015 at 03:31:20PM -0400, Steven Rostedt wrote:
> > > > 4) poll_wait: currently it and poll_table_entry are both hard coupled
> > > >to
Hi,
We do a couple of things in this series which result in
cleaner device tree implementation, faster perfomance and
multi-platform support. As an added bonus we get new GPI/Interrupt pins
for use in the system.
- Establish a custom interface between NAND and GPMC driver. This is
needed because
Add a platform data structure for GPMC. It contains all the necessary
platform information that needs to be passed from platform init code
to GPMC driver.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 3 +--
include/linux/platform_data/gpmc-omap.h | 30
This is needed by OMAP NAND driver to poll the empty status
of the writebuffer.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index
The OMAP GPMC module has certain registers dedicated for NAND
access and some NAND bits mixed with other GPMC functionality.
For the NAND dedicated registers we have the struct gpmc_nand_regs.
The NAND driver needs to access NAND specific bits from the
following non-dedicated registers
1)
On 7 August 2015 at 17:07, Peter Chen wrote:
>
>> >> /**
>> >> * struct usb_udc - describes one usb device controller @@ -127,12
>> >> +128,45 @@ void usb_gadget_giveback_request(struct usb_ep *ep, }
>> >> EXPORT_SYMBOL_GPL(usb_gadget_giveback_request);
>> >>
>> >> +int
Instead of accessing the gpmc_status register directly start
using the gpmc_nand_ops->nand_writebuffer_empty() helper
to check write buffer empty status.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git
NAND IRQs will now be managed directly in the OMAP NAND driver
so remove the IRQchip model.
Another patch will add back GPIO-IRQchip code to handle the
WAITPIN interrupts.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 4 +-
drivers/memory/omap-gpmc.c | 164
Add compatible id and interrupts. The NAND interrupts are
provided by the GPMC controller node.
Signed-off-by: Roger Quadros
---
Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git
Copy all the platform data parameters to the driver's local data
structure 'omap_nand_info' and use it in the entire driver. This will
make it easer for device tree migration.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 26 ++
1 file changed, 18
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 5 +-
drivers/memory/omap-gpmc.c | 135
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
TODO: For now only dra7-evm and omap3-beagle are fixed.
Once series is reviewed I'll update this patch to
fix all omap boards.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 4 +++-
If the device attached to GPMC wants to use the WAIT pin
for WAIT monitoring then we reserve it internally for
exclusive use.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git
On (08/07/15 18:14), Sergey Senozhatsky wrote:
[..]
> hm... we also can simply forbid downgrading a multi stream backend
> to a single stream (in terms of performance it is much slower
> than a real single steam anyway). will this do the trick? if we
> have more than 1 stream and idle list then
As requested, here's a rebased version that doesn't depend on the page-flags
changes from Kirill. This obsoletes the following patches from that series:
page-flags-define-behavior-of-lru-related-flags-on-compound-pages-fix.patch
OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
input if not used for memory wait state insertion.
The first user will be the OMAP NAND chip to get the NAND
read/busy status using gpiolib.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 122
omap-gpmc.c is a memory controller so move the binding to the
right place.
Signed-off-by: Roger Quadros
---
.../bindings/{bus/ti-gpmc.txt => memory-controllers/omap-gpmc.txt}| 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{bus/ti-gpmc.txt
The WAIT pins support falling edge interrupts so add irqchip
support to the gpiochip model.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 111 +
1 file changed, 111 insertions(+)
diff --git a/drivers/memory/omap-gpmc.c
The GPMC WAIT pin status are now available over gpiolib.
Update the omap_dev_ready() function to use gpio instead of
directly accessing GPMC register space.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 29 +---
Partitions which are defined in the som file can not be deleted in the
board file.
Signed-off-by: Matthias Klein
---
arch/arm/boot/dts/am335x-phycore-som.dtsi | 37 -
arch/arm/boot/dts/am335x-wega.dtsi| 45 +++
2 files changed, 45
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
Read speed increases from 13768 KiB/ to 17246 KiB/s.
Write speed was unchanged at 7123 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 1 +
Am Donnerstag, 6. August 2015, 14:49:00 schrieb Brian Norris:
Hi Brian,
>The HTML output works a little nicer that way.
>
>Signed-off-by: Brian Norris
Thank you.
Ciao
Stephan
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