Le 17/08/2015 13:00, leroy christophe a écrit :
Le 17/08/2015 12:56, leroy christophe a écrit :
Le 07/08/2015 01:25, Segher Boessenkool a écrit :
On Thu, Aug 06, 2015 at 05:45:45PM -0500, Scott Wood wrote:
If this makes performance non-negligibly worse on other 32-bit
chips, and is
an
On 08/17/2015 01:10 AM, Jonathan Corbet wrote:
> On Tue, 28 Jul 2015 16:45:15 -0300
> Danilo Cesar Lemes de Paula wrote:
>
>> Functions, Structs and Parameters definitions on kernel documentation
>> are pure cosmetic, it only highlights the element.
>>
>> To ease the navigation in the
On Fri, 14 Aug, at 03:37:29PM, Jonathan (Zhixiong) Zhang wrote:
> From: "Jonathan (Zhixiong) Zhang"
>
> Table 8 of UEFI 2.5 section 2.3.6.1 defines mappings from EFI
> memory types to MAIR attribute encodings for arm64.
>
> If the physical address has memory attributes defined by EFI
> memmap
In case XXX returns with a status of IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY
ts->stat gets set to SAS_OPEN_REJECT but a missing 'break' statement causes a
fallthrough to the default handler of the switch statement overriding ts->stat
to SAS_DEV_NO_RESPONSE.
Signed-off-by: Johannes Thumshirn
---
On 2015-08-15 20:50, Chuck Ebbert wrote:
On Sun, 16 Aug 2015 02:00:34 +0200
noi...@a6.25u.com wrote:
Question: Wouldn't it be a good idea to enforce the Linux trademark
(somewhen) in a way that all these streamlined operating systems use the
word "Linux" more carefully (or not at all) in their
The Intel Baytrail pinctrl driver implements irqchip callbacks which are
called with desc->lock raw_spinlock held. In mainline this is fine because
spinlock resolves to raw_spinlock. However, running the same code in -rt we
get:
BUG: sleeping function called from invalid context at
+Adding Maxime in the loop
On 16/08/15 16:37, Stefan Wahren wrote:
>Another question which spring to mind is, do we want the eeprom to be
>in /sys twice, the old and the new way? Backwards compatibility says
>the old must stay. Do we want a way to suppress the new? Or should we
>be going as
On Thu, Aug 13, 2015 at 06:01:09PM -0700, Stephen Boyd wrote:
> On 07/28, Dong Aisheng wrote:
> > On Freescale i.MX7D platform, all clocks operations, including
> > enable/disable, rate change and re-parent, requires its parent
> > clock on. Current clock core can not support it well.
> > This
Hi,
Why is SECTOR_SIZE 512 ?
http://lxr.free-electrons.com/source/include/linux/ide.h#L118
http://lxr.free-electrons.com/source/include/linux/device-mapper.h#L548
548 #define SECTOR_SHIFT 9
I was looking at disks with hw_sector_size . Most of them i looked at
had 512 bytes except for one
Peter Zijlstra writes:
> On Fri, Jul 24, 2015 at 02:45:56PM +0300, Alexander Shishkin wrote:
>> +static void perf_error_report_site(struct perf_event_attr *attr,
>> + const struct perf_err_site *site)
>> +{
>> +void *buffer;
>> +
>> +if (!site ||
On Mon, Aug 17, 2015 at 3:45 PM, Vladimir Barinov
wrote:
> Hello Daniel,
>
> I've verified that your hrtimer trigger works.
>
> I have minor suggestions.
>
> Will not it be useful to have ability to stop/start hrtimer polling
> not only during attach/detach trigger.
>
> f.e. writing 0 to
Hello Daniel,
I've verified that your hrtimer trigger works.
I have minor suggestions.
Will not it be useful to have ability to stop/start hrtimer polling
not only during attach/detach trigger.
f.e. writing 0 to sampling_frequency will hrtimer_cancel
and writing any valid frequency will
Eric W. Biederman wrote:
> I don't have a clue what the issue would be but I would start with
> something like the patch below.
OK using it I got the following...
This time with /dev on another machine (same nfs root-fs):
Aug 17 13:57:04 dhcp195 kernel: NFS: nfs_lookup_revalidate(/dev):
Add missed description for GPIO irqchip fields in struct gpio_chip.
Signed-off-by: Grygorii Strashko
---
Changes in v2:
- New patch.
include/linux/gpio/driver.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
index
Since IRQ chip helpers were introduced drivers lose ability to
register separate lockdep classes for each registered GPIO IRQ
chip and the gpiolib now is using shared lockdep class for
all GPIO IRQ chips (gpiochip_irq_lock_class).
As result, lockdep will produce warning when there are min two
On 15/08/15 08:21, Stefan Wahren wrote:
Hi Srinivas,
Srinivas Kandagatla hat am 11. August 2015 um
13:03 geschrieben:
This patch adds perm variable to nvmem_config structure which will allow
providers to specify the permissions required for the sysfs binary file.
This permission is
On 16/08/15 21:24, Peter Zijlstra wrote:
> On Sat, Aug 15, 2015 at 09:03:33PM -0700, Michael Turquette wrote:
>> Quoting Peter Zijlstra (2015-08-15 05:46:38)
>>> On Tue, Jul 07, 2015 at 07:24:23PM +0100, Morten Rasmussen wrote:
diff --git a/kernel/sched/cpufreq_sched.c
On Mon, Aug 17, 2015 at 12:57:24PM +0200, Alexandre Belloni wrote:
> On 17/08/2015 at 12:09:14 +0200, Thierry Reding wrote :
> > On Sat, Aug 01, 2015 at 12:44:31AM +0200, Alexandre Belloni wrote:
> > > From: Josh Wu
> > >
> > > The QiaoDian Xianshi QD43003C0-40 is a 4"3 TFT LCD panel.
> > >
> >
The locking scheme used in ptlrpc_deactivate_and_unlock_import and
ptlrpc_deactivate_import generates the followings sparse errors:
drivers/staging/lustre/lustre/ptlrpc/import.c:209:9: warning: context
imbalance in 'ptlrpc_deactivate_and_unlock_import' - unexpected unlock
Huaitong Han writes:
> rdmsrl_safe does not lead to #GP in native kernel although CPU
> does not support INTEL_PT, but if KVM does not support INTEL_PT,
> the codes cannot understand MSR_IA32_RTIT_CTL, and the warning
> is produced.
"the codes"?
> If KVM does not support INTEL_PT, its guest
On Thu 2015-08-13 12:37:29, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> Add a document spelling out usage of the simple fpga bus.
>
> Signed-off-by: Alan Tull
Acked-by: Pavel Machek
Pavel
--
In bfa_fcs_lport_get_rport_max_speed() check if port is non NULL before
dereferencing it's child port->fcs->bfa to trl_enabled.
NB: I'm not entirely sure if port can even be NULL, so the check for NULL might
be useless as well.
Signed-off-by: Johannes Thumshirn
---
On Fri, Aug 14, 2015 at 12:31:32PM -0700, Dustin Byford wrote:
>
> (v2 corrects cc: list)
>
> I would like to add support for scanning I2C devices connected to ACPI
> OF compatible muxes described in ASL like this:
>
> Device (MUX0)
> {
> Name (_ADR, 0x70)
> Name (_HID, "PRP0001")
>
On Thu 2015-08-13 12:37:27, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> API to support programming FPGA.
I'd do s/fpga/FPGA/ in the comments, too. Otherwise looks ok to me.
Acked-by: Pavel Machek
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
Hi Daniel,
Find minor comments.
Regards,
Vladimir
On 11.08.2015 01:42, Daniel Baluta wrote:
Signed-off-by: Daniel Baluta
---
Documentation/ABI/testing/configfs-iio | 20
Documentation/iio/iio_configfs.txt | 57 ++
2 files changed, 77
On Wed, Aug 12, 2015 at 05:16:50PM -0700, David Rientjes wrote:
> On Wed, 12 Aug 2015, Mel Gorman wrote:
>
> > There is a seqcounter that protects against spurious allocation failures
> > when a task is changing the allowed nodes in a cpuset. There is no need
> > to check the seqcounter until a
Some of the pin-controllers like the Qualcomms "qcom,pm8921", which
require a pinconf to be setup to use pins as gpios. Using the pins
directly without pinconf setup would result in incorrect output voltage
or load settings. On the other hand pwrseq code does not configure the
pinctrl by default
On Thu 2015-08-13 12:37:32, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> Add simple fpga bus. This is a bus that configures an fpga and its
> bridges before populating the devices below it. This is intended
> for use with device tree overlays.
>
> Note that FPGA bridges are seen
On Thu 2015-08-13 12:37:30, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> New bindings document for simple fpga bus.
>
> Signed-off-by: Alan Tull
Acked-by: Pavel Machek
> + onchip_memory2_0: memory@0x0 {
> +
On Mon, 17 Aug 2015 19:47:21 +0800
Jisheng Zhang wrote:
> commit bb8175a8aa42 ("mmc: sdhci: clarify DDR timing mode between
> SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR mode to be
> distinguished from SD-UHS, but it missed setting driver type for
> MMC_DDR52 timing mode. This patches adds
I detected this issues with scripts/checkkconfigsymbols.py by diffing
next-20150814..next-20150817
drivers/staging/hfi1/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/hfi1/Kconfig b/drivers/staging/hfi1/Kconfig
index 87a385a02cba..fd25078ee
On 17 August 2015 at 16:20, Li Jun wrote:
> On Mon, Aug 17, 2015 at 02:02:08PM +0800, Baolin Wang wrote:
>> On 17 August 2015 at 09:15, Li Jun wrote:
>> > On Fri, Aug 14, 2015 at 07:04:56PM +0800, Baolin Wang wrote:
>> >> On 14 August 2015 at 16:55, Li Jun wrote:
>> >> > Hi Baolin,
>> >> >
>>
commit bb8175a8aa42 ("mmc: sdhci: clarify DDR timing mode between
SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR mode to be
distinguished from SD-UHS, but it missed setting driver type for
MMC_DDR52 timing mode. This patches adds the missing driver type
setting.
Fixes: bb8175a8aa42 ("mmc: sdhci:
On Mon, Aug 17, 2015 at 12:29:51PM +0100, Morten Rasmussen wrote:
> On Sun, Aug 16, 2015 at 10:46:05PM +0200, Peter Zijlstra wrote:
> > On Fri, Aug 14, 2015 at 05:23:08PM +0100, Morten Rasmussen wrote:
> > > Target: ARM TC2 A7-only (x3)
> > > Test: hackbench -g 25 --threads -l 1
> > >
> > >
On Mon, 17 Aug 2015 19:34:39 +0800
Jisheng Zhang wrote:
> commit 08f90f14aa93ad424c20bb176b52f329583e2183 ("mmc: sdhci: clarify
> DDR timing mode between SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR
> mode to be distinguished from SD-UHS, but it missed setting driver type
> for MMC_DDR52
Hi, Ingo, thanks for your review,
On Mon, 2015-08-17 at 12:11 +0200, Ingo Molnar wrote:
> So what your changelog fails to mention:
>
> - You only add this code to the 64-bit kernel. Are 32-bit kernels not
> affected?
Yes, 32-bit kernel should also do the save/restore operation.
I'll adjust
commit 08f90f14aa93ad424c20bb176b52f329583e2183 ("mmc: sdhci: clarify
DDR timing mode between SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR
mode to be distinguished from SD-UHS, but it missed setting driver type
for MMC_DDR52 timing mode. This patches adds the missing driver type
setting.
On 08/16, Arthur Marsh wrote:
>
> Would these patches address what I've seen in the last day or so using
> Linus' git head kernel and seeing problems like:
No, this series shouldn't make any difference.
> [0.00] Linux version 4.2.0-rc6+ (root@victoria) (gcc version
> 5.2.1 20150808
On 12 August 2015 at 10:24, Chaotian Jing wrote:
> Schedule a workqueue to do tuning when CRC error
> Call mmc_hw_reset to re-init card when data timeout
Thanks to Adrian Hunter, the mmc core already supports re-tuning for
the above scenarios through the mmc_retune_*() APIs.
SDHCI driver has
Hi Daniel,
Minor comments since I need your hrtimer trigger support.
1) The drivers/iio/industrialio-sw-trigger.c should probably
come to drivers/iio/trigger/ folder which is under ifdef condition
in drivers/iio/Kconfig
2) it breaks compilation
enabling IIO_HRTIMER_TRIGGER selects
On Thu, Aug 13, 2015 at 02:32:23PM +0200, Benjamin Gaignard wrote:
> Add Vincent Abriou and myself has maintainers.
>
> Signed-off-by: Benjamin Gaignard
> ---
> MAINTAINERS | 9 +
> 1 file changed, 9 insertions(+)
I'm glad to see this. I think we'll need a couple like this for other
On Sun, Aug 16, 2015 at 10:46:05PM +0200, Peter Zijlstra wrote:
> On Fri, Aug 14, 2015 at 05:23:08PM +0100, Morten Rasmussen wrote:
> > Target: ARM TC2 A7-only (x3)
> > Test: hackbench -g 25 --threads -l 1
> >
> > Before After
> > 315.545 313.408 -0.68%
> >
> > Target: Intel(R)
On 08/17/2015 02:52 PM, Michal Suchanek wrote:
> Hello,
>
> On 17 August 2015 at 03:55, Jaehoon Chung wrote:
>> Hi, Michal.
>>
>> On 08/12/2015 09:23 PM, Michal Suchanek wrote:
>>> The driver has open-coded test for SDIO cards. Use the mmc core provided
>>> MMC_QUIRK_BROKEN_CLK_GATING flag
Hi Mark,
On Sun, Aug 16, 2015 at 09:49:27PM +0100, Mark Salter wrote:
> The use of mem= could leave part or all of the initrd outside of
> the kernel linear map. This will lead to an error when unpacking
> the initrd and a probable failure to boot. This patch catches that
> situation and
This patch fix spelling typo "the the" found in controls.xml
and vidioc-g-param.xml.
These xml files are generated from NOT any files, so I have
to fix these xml files.
Signed-off-by: Masanari Iida
---
Documentation/DocBook/media/v4l/controls.xml | 2 +-
On Sat, Jul 25, 2015 at 8:57 AM, Andy Lutomirski wrote:
> This will allow IRQ stacks to nest inside NMIs or similar entries
> that can happen during IRQ stack setup or teardown.
>
> The Xen code here has a confusing comment.
>
> The new macros won't work correctly if they're invoked with IRQs on.
DAPM core already creates widgets for DAIs. It is not necessary
to declare them by SND_SOC_DAPM_AIF_IN/SND_SOC_DAPM_AIF_OUT.
Furthermore, original codes use backend DAI's stream name to be the AIF
widget name. It causes the same widget to be created twice, and after
commit 92fa12426741 ("ASoC:
On Tue, Aug 04, 2015 at 02:04:35PM +, Karajgaonkar, Saurabh (S.) wrote:
> From: Saurabh Karajgaonkar
>
> Replace redundant variable use in return statement.
>
> Signed-off-by: Saurabh Karajgaonkar
> ---
> drivers/usb/serial/mxuport.c | 10 +++---
> 1 file changed, 3 insertions(+), 7
Hi Peter,
On 16/08/15 21:35, Peter Zijlstra wrote:
> On Tue, Jul 07, 2015 at 07:24:28PM +0100, Morten Rasmussen wrote:
>> From: Juri Lelli
>>
>> Use the cpu argument of cpufreq_sched_set_cap() to handle per_cpu writes,
>> as the thing can be called remotely (e.g., from load balacing code).
>>
>>
If the bf_get() call in lpfc_mbx_cmpl_rdp_page_a2() does succeeds, execution
continues normally and mp gets kfree()d.
If the subsequent call to lpfc_sli_issue_mbox() fails execution jumps to the
error label where lpfc_mbuf_free() is called with mp->virt and mp->phys as
function arguments. This is
Le 17/08/2015 12:56, leroy christophe a écrit :
Le 07/08/2015 01:25, Segher Boessenkool a écrit :
On Thu, Aug 06, 2015 at 05:45:45PM -0500, Scott Wood wrote:
If this makes performance non-negligibly worse on other 32-bit
chips, and is
an important improvement on 8xx, then we can use an
On 08/17/2015 10:01 AM, Ingo Molnar wrote:
>
> (Sorry about the late reply, wasn't around on the weekend.)
>
> * Linus Torvalds wrote:
>
>> Now that said, I doubt anybody cares. Since we don't support the original
>> 80386,
>> the only way to ever trigger FP emulation is by having a 486SX or
Le 07/08/2015 01:25, Segher Boessenkool a écrit :
On Thu, Aug 06, 2015 at 05:45:45PM -0500, Scott Wood wrote:
If this makes performance non-negligibly worse on other 32-bit chips, and is
an important improvement on 8xx, then we can use an ifdef since 8xx already
requires its own kernel build.
On 17/08/2015 at 12:09:14 +0200, Thierry Reding wrote :
> On Sat, Aug 01, 2015 at 12:44:31AM +0200, Alexandre Belloni wrote:
> > From: Josh Wu
> >
> > The QiaoDian Xianshi QD43003C0-40 is a 4"3 TFT LCD panel.
> >
> > Timings from the OTA5180A document, ver 0.9, section
> > 10.1.1:
> >
Hi all,
Changes since 20150813:
Dropped tree: drm-exynos
The pci tree gained a conflict against the arm-soc tree.
The v4l-dvb tree still had its build failure so I used the version from
next-20150810.
The pm tree gained a conflict against the samsung tree.
The thermal-soc tree gained a
On Mon, Aug 17, 2015 at 12:52:20PM +0200, Thierry Reding wrote:
> On Tue, Aug 11, 2015 at 02:22:43PM +0200, Mike Looijmans wrote:
> > Header claims GPL v2, so make the MODULE_LICENSE reflect that properly.
> >
> > Signed-off-by: Mike Looijmans
> > ---
> > drivers/gpu/drm/i2c/adv7511.c | 2 +-
>
On Tue, Aug 11, 2015 at 02:22:43PM +0200, Mike Looijmans wrote:
> Header claims GPL v2, so make the MODULE_LICENSE reflect that properly.
>
> Signed-off-by: Mike Looijmans
> ---
> drivers/gpu/drm/i2c/adv7511.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
The subject prefix looks
On Sun, Aug 02, 2015 at 08:41:48PM -0700, Liu.Zhao wrote:
Make sure to always include a commit message.
Also change you Subject (patch summary) to something more descriptive
using the following format:
USB: option: add ZTE PIDs
> Signed-off-by: Liu.Zhao
> ---
>
Am Montag, 17. August 2015, 12:34:09 schrieb Ulf Hansson:
> [...]
>
> >>> - mmc->max_seg_size = mmc->max_req_size;
> >>> -#endif /* CONFIG_MMC_DW_IDMAC */
> >>> + if (host->use_dma) {
> >>> + mmc->max_segs = host->ring_size;
> >>
> >> I expect
Hi Phil,
On Mon, Aug 17, 2015 at 12:23 PM, Phil Edworthy
wrote:
> On 11 August 2015 13:43, Geert wrote:
>> On arm64/shmobile:
>>
>> drivers/pci/host/pci-rcar-gen2.c: In function 'rcar_pci_cfg_base':
>> drivers/pci/host/pci-rcar-gen2.c:112:34: error: dereferencing pointer to
>> incomplete
[...]
>>> - mmc->max_seg_size = mmc->max_req_size;
>>> -#endif /* CONFIG_MMC_DW_IDMAC */
>>> + if (host->use_dma) {
>>> + mmc->max_segs = host->ring_size;
>>
>> I expect this may cause a compiler error since host->ring_size is only
>> available in
Hi Paul,
Currently RCU tree distributes CPUs to leafs based on consequent CPU
IDs. That means CPUs from remote caches and even nodes might end up
in the same leaf.
I did not research the impact, but at the glance that seems at least
sub-optimal; especially in case of remote nodes, when CPUs
Hi Geert,
On 11 August 2015 13:43, Geert wrote:
> On arm64/shmobile:
>
> drivers/pci/host/pci-rcar-gen2.c: In function 'rcar_pci_cfg_base':
> drivers/pci/host/pci-rcar-gen2.c:112:34: error: dereferencing pointer to
> incomplete type
> struct rcar_pci_priv *priv = sys->private_data;
>
Hi, Ulf.
On 08/17/2015 07:16 PM, Ulf Hansson wrote:
> On 3 August 2015 at 17:04, Heiko Stübner wrote:
>> The dw_mci_init_dma() may decide to not use dma, but pio instead, caused
>> by things like wrong dma settings in the system.
>>
>> Till now the code dw_mci_init_slot() always assumed that dma
On Mon, 2015-08-17 at 11:53 +0200, Vlastimil Babka wrote:
> I meant why the kernel used for QEMU has also CMA enabled and used
> (for
> something else)? CMA is mostly used on mobile devices and they don't
> run
> QEMU?
I explained in a separeate reply but yes, we do use a CMA for KVM for
our
On 3 August 2015 at 17:04, Heiko Stübner wrote:
> The dw_mci_init_dma() may decide to not use dma, but pio instead, caused
> by things like wrong dma settings in the system.
>
> Till now the code dw_mci_init_slot() always assumed that dma is available
> when CONFIG_MMC_DW_IDMAC was defined,
On Sat, Aug 01, 2015 at 12:44:31AM +0200, Alexandre Belloni wrote:
> From: Josh Wu
>
> The QiaoDian Xianshi QD43003C0-40 is a 4"3 TFT LCD panel.
>
> Timings from the OTA5180A document, ver 0.9, section
> 10.1.1:
> http://www.orientdisplay.com/pdf/OTA5180A.pdf
>
> Signed-off-by: Josh Wu
>
* Chen Yu wrote:
> A bug is reported(https://bugzilla.redhat.com/show_bug.cgi?id=1227208)
> that, after resuming from S3, CPU is working at a low speed.
> After investigation, it is found that, BIOS has modified the value
> of THERM_CONTROL register during S3, changes it from 0 to 0x10,
> while
On Fri, Aug 14, 2015 at 01:35:53PM +0100, fu@linaro.org wrote:
> From: Tomasz Nowicki
>
> This commit provides APEI arch-specific bits for aarch64
>
> Changelog:
> Fu Wei:
> Move arch_apei_flush_tlb_one() to arch/arm64/include/asm/apci.h.
> Delete arch/arm64/kernel/apei.c.
>
On Mon, 2015-08-17 at 19:11 +1000, Alexey Kardashevskiy wrote:
> On 08/17/2015 05:45 PM, Vlastimil Babka wrote:
> > On 08/05/2015 10:08 AM, Alexey Kardashevskiy wrote:
> > > This is about VFIO aka PCI passthrough used from QEMU.
> > > KVM is irrelevant here.
> > >
> > > QEMU is a machine
On Mon, Aug 17, 2015 at 10:34:03AM +0300, Adrian Hunter wrote:
> On 29/07/15 00:14, Adrian Hunter wrote:
> > When TSC is stable perf/sched clock is based on it.
> > However the conversion from cycles to nanoseconds
> > is not as accurate as it could be. Because
> > CYC2NS_SCALE_FACTOR is 10, the
On 08/17/2015 11:11 AM, Alexey Kardashevskiy wrote:
On 08/17/2015 05:45 PM, Vlastimil Babka wrote:
On 08/05/2015 10:08 AM, Alexey Kardashevskiy wrote:
This is about VFIO aka PCI passthrough used from QEMU.
KVM is irrelevant here.
QEMU is a machine emulator. It allocates guest RAM from
Hi Andrew,
Thanks for the patch, few comments other than Stefan's comments.
On 16/08/15 03:54, Andrew Lunn wrote:
Add a read only regmap for accessing the EEPROM, and then use that
with the NVMEM framework.
Signed-off-by: Andrew Lunn
---
drivers/misc/eeprom/at24.c | 65
> -Original Message-
> From: Markus Pargmann [mailto:m...@pengutronix.de]
> Sent: 17 August, 2015 12:10
> To: Jonathan Cameron
> Cc: Tirdea, Irina; Wolfram Sang; linux-...@vger.kernel.org;
> linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Pandruvada,
> Srinivas; Peter Meerwald
> IBM Xseries 346, 2x Xeon 3.2 HT 64-bit (4 threads total, P4 era Xeon),
> 5G RAM. All kernels so far worked fine, last working one was
> 4.2.0-rc2-00077-gf760b87. First kernel tested after that was
> v4.2-rc6-20-g7a834ba and that one crashes on boot.
Same crash happens in 4.2.0-rc7.
>
On 17/08/15 08:52, Jani Nikula wrote:
On Fri, 14 Aug 2015, Srinivas Kandagatla wrote:
This patch adds support to get edid way early before the connector is
created, this is mainly used for panel drivers to auto-probe the panel
based on the vendor and product id from EDID.
Signed-off-by:
Am 15.08.2015 um 09:48 schrieb Alexander Holler:
Am 30.07.2015 um 13:57 schrieb Alexander Holler:
Am 29.07.2015 um 11:25 schrieb Alexander Holler:
Am 23.05.2015 um 05:55 schrieb Martin KaFai Lau:
To complete the discussion, that "annoying behaviour" is also a big
information leak.
Because
On 14 August 2015 at 13:39, Juri Lelli wrote:
> Hi vincent,
>
> On 13/08/15 13:08, Vincent Guittot wrote:
>> On 12 August 2015 at 17:15, Juri Lelli wrote:
>>> On 11/08/15 17:37, Vincent Guittot wrote:
On 11 August 2015 at 17:07, Juri Lelli wrote:
> Hi Vincent,
>
> On 11/08/15
On 08/14/2015 03:34 PM, Linus Walleij wrote:
> On Thu, Aug 13, 2015 at 4:58 PM, Grygorii Strashko
> wrote:
>
>> Since IRQ chip helpers were introduced drivers lose ability to
>> register separate lockdep classes for each registered GPIO IRQ
>> chip and the gpiolib now is using shared lockdep
> -Original Message-
> From: Jonathan Cameron [mailto:ji...@kernel.org]
> Sent: 16 August, 2015 12:25
> To: Tirdea, Irina; Wolfram Sang; linux-...@vger.kernel.org;
> linux-...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; Pandruvada, Srinivas; Peter Meerwald
> Subject: Re: [PATCH
On Mon, Aug 17, 2015 at 04:45:49PM +0900, byungchul.p...@lge.com wrote:
> From: Byungchul Park
i am very sorry for ugly versioning..
while i proposed several indivisual patches and was feedbacked, i felt
that i needed to pack some patches into one series.
thanks,
byungchul
>
> change from v1
On Mon, Aug 17, 2015 at 02:02:08PM +0800, Baolin Wang wrote:
> On 17 August 2015 at 09:15, Li Jun wrote:
> > On Fri, Aug 14, 2015 at 07:04:56PM +0800, Baolin Wang wrote:
> >> On 14 August 2015 at 16:55, Li Jun wrote:
> >> > Hi Baolin,
> >> >
> >> > On Fri, Aug 14, 2015 at 05:47:43PM +0800,
On Mon, Aug 17, 2015 at 12:47 PM, Alexandre Courbot wrote:
> On Thu, Aug 13, 2015 at 4:29 PM, Vaishali Thakkar
> wrote:
>> Use managed resource functions devm_clk_put and
>> devm_snd_soc_register_component to simplify error handling.
>>
>> To be compatible with the change various gotos are
> -Original Message-
> From: Lars-Peter Clausen [mailto:l...@metafoo.de]
> Sent: 12 August, 2015 18:04
> To: Markus Pargmann; Jonathan Cameron
> Cc: Srinivas Pandruvada; Dogaru, Vlad; Paul Bolle; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org; ker...@pengutronix.de;
> Tirdea,
Mediatek MT8173 is an ARMv8 based quad-core (2*Cortex-A53 and
2*Cortex-A72) SoC with duall clusters. For each cluster, two voltage
inputs, Vproc and Vsram are supplied by two regulators. For the big
cluster, two regulators come from different PMICs. In this case, when
scaling voltage inputs of the
This patch adds the clock and regulator consumer properties part of
document for CPU DVFS clocks on Mediatek MT8173 SoC.
Signed-off-by: Pi-Cheng Chen
Acked-by: Michael Turquette
Acked-by: Viresh Kumar
---
.../devicetree/bindings/clock/mt8173-cpu-dvfs.txt | 83 ++
1 file
This patch adds the required properties in device tree to enable MT8173
cpufreq driver.
Signed-off-by: Pi-Cheng Chen
Acked-by: Viresh Kumar
---
It is based on the top of MT8173 SoC maintainer's tree:
https://github.com/mbgg/linux-mediatek.git v4.2-next/arm64
commit id:
MT8173 is a ARMv8 based SoC with 2 clusters. All CPUs in a single cluster
share the same power and clock domain. This series tries to add cpufreq support
for MT8173 SoC. The v6 of this series is resent with Acks added.
changes in v6:
- Move clock and regulator consumer properties document to the
Hi Morten,
On Tue, Jul 07, 2015 at 07:24:01PM +0100, Morten Rasmussen wrote:
> From: Dietmar Eggemann
>
> This patch is only here to be able to test provisioning of energy related
> data from an arch topology shim layer to the scheduler. Since there is no
> code today which deals with
On 08/15/2015 11:13 PM, Chuck Ebbert wrote:
> On Wed, 12 Aug 2015 10:13:24 -0400
> Sasha Levin wrote:
>
>> While fuzzing with trinity inside a KVM tools guest running -next I've
>> stumbled on the following:
>>
>> [64092.216447]
>>
Thanks, Arnd,
You are right. This is the same IP as hip04_mdio.c. We just mis-understand the
hardware design. We will merge them and re-submit the patches.
On Fri, Aug 14, 2015 at 10:57:28PM +0200, Arnd Bergmann wrote:
> On Friday 14 August 2015 18:30:20 Kenneth Lee wrote:
>
> > +#define
HYVÄ ASIAKAS
Uuden ohjelmiston asentaminen internetpankkiisi.
Tämän palvelun avulla NORDEA-internetpankkisi on vapaa viruksista,
saat lisäturvan internetpetoksia vastaan ja nopean pääsyn e-pankkiisi
suoraan puhelimellasi. Aloittaaksesi ohjelmistopäivityksen,
pyydämme sinua klikkaamaan alla
On Mon, Aug 17, 2015 at 3:52 PM, Yingjoe Chen wrote:
> On Fri, 2015-08-14 at 16:38 +0800, maoguang.m...@mediatek.com wrote:
>> From: Maoguang Meng
>>
>> This patch implement irq_set_wake to get who is wakeup source and
>> setup on suspend resume.
>>
>> Signed-off-by: Maoguang Meng
>>
>> ---
>>
Include asm-generic/msi.h to support CONFIG_GENERIC_MSI_IRQ_DOMAIN.
This to fix compilation error:
"include/linux/msi.h:123:21: fatal error: asm/msi.h:
No such file or directory"
Signed-off-by: Ley Foon Tan
---
arch/arm/include/asm/Kbuild | 1 +
1 file changed, 1 insertion(+)
diff --git
This patch adds the Altera PCIe host controller driver.
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/Kconfig | 7 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-altera.c | 543 +
3 files changed, 551 insertions(+)
create mode
On 08/17/2015 05:45 PM, Vlastimil Babka wrote:
On 08/05/2015 10:08 AM, Alexey Kardashevskiy wrote:
This is about VFIO aka PCI passthrough used from QEMU.
KVM is irrelevant here.
QEMU is a machine emulator. It allocates guest RAM from anonymous memory
and these pages are movable which is ok.
Saturday, August 15, 2015, 12:39:25 AM, you wrote:
> On Sat, 2015-08-15 at 00:09 +0200, Sander Eikelenboom wrote:
>> On 2015-08-13 00:41, Eric Dumazet wrote:
>> > On Wed, 2015-08-12 at 23:46 +0200, Sander Eikelenboom wrote:
>> >
>> >> Thanks for the reminder, but luckily i was aware of that,
>>
Signed-off-by: Ley Foon Tan
---
MAINTAINERS | 16
1 file changed, 16 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fd60784..32f5287 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7759,6 +7759,14 @@ F: include/linux/pci*
F: arch/x86/pci/
F:
This patch adds the bindings for Altera PCIe host controller driver and
Altera PCIe MSI driver.
Signed-off-by: Ley Foon Tan
---
.../devicetree/bindings/pci/altera-pcie-msi.txt| 27
.../devicetree/bindings/pci/altera-pcie.txt| 49 ++
2 files changed,
This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/Kconfig | 8 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-altera-msi.c | 322
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