Hi Jens,
I hope this is not too late. Here are some NBD updates.
The most interesting one is probably the first patch, which improves the
timeout detection of NBD. The timout covers now the last reaction of the
server. If there are open requests and we don't receive anything from the
server
This patch renames functions so that it is clear what the function does.
Otherwise it is not directly understandable what for example 'do_it' means.
Signed-off-by: Markus Pargmann
---
drivers/block/nbd.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
The flags variable is used as u32 variable. This patch changes the type
to be u32.
Signed-off-by: Markus Pargmann
---
drivers/block/nbd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c
index 9862c3e64ff2..1176a3b27a7e 100644
---
Instead of a variable 'harderror' we can simply try to correctly
propagate errors to the userspace.
This patch removes the harderror variable and passes errors through
error pointers and nbd_do_it back to the userspace.
Signed-off-by: Markus Pargmann
Acked-by: Pavel Machek
---
On Mon, Aug 17, 2015 at 02:06:07PM +1000, Michael Ellerman wrote:
> On Wed, 2015-08-12 at 08:43 -0700, Paul E. McKenney wrote:
> > On Wed, Aug 12, 2015 at 02:44:15PM +0100, Will Deacon wrote:
> > > Hello Paul,
> > >
> > > On Fri, Jul 24, 2015 at 04:30:46PM +0100, Paul E. McKenney wrote:
> > > >
Will,
On 08/12/2015 02:03 AM, Will Deacon wrote:
On Tue, Aug 04, 2015 at 08:44:06AM +0100, AKASHI Takahiro wrote:
A stack frame pointer may be used in a different way depending on
cpu architecture. Thus it is not always appropriate to slurp the stack
contents, as currently done in
Hi all,
On Mon, 17 Aug 2015 15:29:53 +1000 Stephen Rothwell
wrote:
>
> After a bit of digging, I installed libssl-dev on my Debian build
> machines.
Is this worth a mention in Documentation/Changes along with all the
other prerequisites?
--
Cheers,
Stephen Rothwell
On 17 August 2015 at 09:15, Li Jun wrote:
> On Fri, Aug 14, 2015 at 07:04:56PM +0800, Baolin Wang wrote:
>> On 14 August 2015 at 16:55, Li Jun wrote:
>> > Hi Baolin,
>> >
>> > On Fri, Aug 14, 2015 at 05:47:43PM +0800, Baolin Wang wrote:
>> >> Currently the Linux kernel does not provide any
From: Noam Camus
We define buf_int_enable in the minimal namespace it is used.
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_enet.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/ezchip/nps_enet.c
From: Noam Camus
This is needed for when TX done interrupt is in
"level mode".
For example it is true for some simulators of this device.
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_enet.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git
From: Noam Camus
We set controller to drop control frames and not trying
to pass them on. This is only needed for debug reasons.
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_enet.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Noam Camus
We need to set tx_skb pointer before send frame.
If we receive interrupt before we set pointer we will try
to free SKB with wrong pointer.
Now we are sure that SKB pointer will never be NULL during
handling TX done and check is removed.
Signed-off-by: Noam Camus
---
From: Noam Camus
When interrupt is received we read directly from control
register for RX/TX instead of reading cause register
since this register fails to indicate TX done when
TX interrupt is "edge mode".
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_enet.c |9 +
From: Noam Camus
TX handler is minimalistic and there is no need to schedule
a NAPI job.
Tx done will be processed during hardware interrupt context.
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_enet.c | 17 ++---
1 files changed, 10 insertions(+), 7
From: Noam Camus
This patch set is a bunch of fixes to make nps_enet work correctly with
all platforms, i.e. real device, emulation system, and simulation system.
The main trigger for this patch set was that in our emulation system
the TX end interrupt is "edge-sensitive" and therefore we cannot
On 08/17/2015 02:39 PM, naresh.kamb...@linaro.org wrote:
From: Naresh Kamboju naresh.kamb...@linaro.org
Are you using git send-email to send this patch? Not sure why
I see this From and the one below.
zram.sh: sanity check of CONFIG_ZRAM and run zram01.sh and zram02.sh
zram01.sh: creates
On Fri, Aug 14, 2015 at 07:11:27PM -0700, Dan Williams wrote:
On Fri, Aug 14, 2015 at 3:33 PM, Dan Williams dan.j.willi...@intel.com
wrote:
On Fri, Aug 14, 2015 at 3:06 PM, Jerome Glisse j.gli...@gmail.com wrote:
On Fri, Aug 14, 2015 at 02:52:15PM -0700, Dan Williams wrote:
On Fri, Aug
On Mon, 2015-08-17 at 21:25 +0800, Yingjoe Chen wrote:
On Mon, 2015-08-17 at 17:09 +0800, Daniel Kurtz wrote:
On Mon, Aug 17, 2015 at 3:52 PM, Yingjoe Chen yingjoe.c...@mediatek.com
wrote:
On Fri, 2015-08-14 at 16:38 +0800, maoguang.m...@mediatek.com wrote:
From: Maoguang Meng
Commit-ID: 75e3b37d059856a972a5bf2bdfeac0f0f2db9ea3
Gitweb: http://git.kernel.org/tip/75e3b37d059856a972a5bf2bdfeac0f0f2db9ea3
Author: Luiz Capitulino lcapitul...@redhat.com
AuthorDate: Tue, 11 Aug 2015 16:40:43 -0400
Committer: Thomas Gleixner t...@linutronix.de
CommitDate: Mon, 17 Aug
On Sun, 16 Aug 2015 00:26:46 +0600 Alexander Kuleshov kuleshovm...@gmail.com
wrote:
This patch adds a check for memblock_reserve() call in the
memblock_virt_alloc_internal() function, because memblock_reserve()
can return -errno on fail.
...
--- a/mm/memblock.c
+++ b/mm/memblock.c
@@
On Mon, 17 Aug 2015, John Stultz wrote:
From: Shaohua Li s...@fb.com
From time to time we saw TSC is marked as unstable in our systems, while
Stray ''
the CPUs declare to have stable TSC. Looking at the clocksource unstable
detection, there are two problems:
- watchdog clock source wrap.
On Mon, Aug 17, 2015 at 2:24 PM, Thomas Gleixner t...@linutronix.de wrote:
On Mon, 17 Aug 2015, John Stultz wrote:
From: Shaohua Li s...@fb.com
Add a sanity check to make sure watchdog clocksource doesn't wrap too
quickly.
Too quickly for what?
The maximum interval delay limit (which
On Mon, Aug 17, 2015 at 07:15:01AM +0100, Paul E. McKenney wrote:
On Mon, Aug 17, 2015 at 02:06:07PM +1000, Michael Ellerman wrote:
On Wed, 2015-08-12 at 08:43 -0700, Paul E. McKenney wrote:
On Wed, Aug 12, 2015 at 02:44:15PM +0100, Will Deacon wrote:
On Fri, Jul 24, 2015 at 04:30:46PM
On Fri, Aug 14, 2015 at 09:26:21PM +0100, Bjorn Helgaas wrote:
On Fri, Aug 14, 2015 at 11:43 AM, Will Deacon will.dea...@arm.com wrote:
On Fri, Aug 14, 2015 at 05:40:51PM +0100, Bjorn Helgaas wrote:
Do we need support for pci-probe-only in pci-host-generic at all?
You're removing the use in
Thanks, Arnd,
You are right. This is the same IP as hip04_mdio.c. We just mis-understand the
hardware design. We will merge them and re-submit the patches.
On Fri, Aug 14, 2015 at 10:57:28PM +0200, Arnd Bergmann wrote:
On Friday 14 August 2015 18:30:20 Kenneth Lee wrote:
+#define
IBM Xseries 346, 2x Xeon 3.2 HT 64-bit (4 threads total, P4 era Xeon),
5G RAM. All kernels so far worked fine, last working one was
4.2.0-rc2-00077-gf760b87. First kernel tested after that was
v4.2-rc6-20-g7a834ba and that one crashes on boot.
Same crash happens in 4.2.0-rc7.
Screenshot
Hi, Ulf.
On 08/17/2015 07:16 PM, Ulf Hansson wrote:
On 3 August 2015 at 17:04, Heiko Stübner he...@sntech.de wrote:
The dw_mci_init_dma() may decide to not use dma, but pio instead, caused
by things like wrong dma settings in the system.
Till now the code dw_mci_init_slot() always assumed
On Mon, 2015-08-17 at 11:53 +0200, Vlastimil Babka wrote:
I meant why the kernel used for QEMU has also CMA enabled and used
(for
something else)? CMA is mostly used on mobile devices and they don't
run
QEMU?
I explained in a separeate reply but yes, we do use a CMA for KVM for
our MMU
Am Montag, 17. August 2015, 12:34:09 schrieb Ulf Hansson:
[...]
- mmc-max_seg_size = mmc-max_req_size;
-#endif /* CONFIG_MMC_DW_IDMAC */
+ if (host-use_dma) {
+ mmc-max_segs = host-ring_size;
I expect this may cause a compiler error
On Thu 2015-08-13 12:37:30, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
New bindings document for simple fpga bus.
Signed-off-by: Alan Tull at...@opensource.altera.com
Acked-by: Pavel Machek pa...@ucw.cz
+ onchip_memory2_0:
On Mon, 17 Aug 2015 19:47:21 +0800
Jisheng Zhang jszh...@marvell.com wrote:
commit bb8175a8aa42 (mmc: sdhci: clarify DDR timing mode between
SD-UHS and eMMC) added MMC_DDR52 as eMMC's DDR mode to be
distinguished from SD-UHS, but it missed setting driver type for
MMC_DDR52 timing mode. This
In bfa_fcs_lport_get_rport_max_speed() check if port is non NULL before
dereferencing it's child port-fcs-bfa to trl_enabled.
NB: I'm not entirely sure if port can even be NULL, so the check for NULL might
be useless as well.
Signed-off-by: Johannes Thumshirn jthumsh...@suse.de
---
On Thu 2015-08-13 12:37:29, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
Add a document spelling out usage of the simple fpga bus.
Signed-off-by: Alan Tull at...@opensource.altera.com
Acked-by: Pavel Machek pa...@denx.de
Huaitong Han huaitong@intel.com writes:
rdmsrl_safe does not lead to #GP in native kernel although CPU
does not support INTEL_PT, but if KVM does not support INTEL_PT,
the codes cannot understand MSR_IA32_RTIT_CTL, and the warning
is produced.
the codes?
If KVM does not support
-Original Message-
From: Lars-Peter Clausen [mailto:l...@metafoo.de]
Sent: 12 August, 2015 18:04
To: Markus Pargmann; Jonathan Cameron
Cc: Srinivas Pandruvada; Dogaru, Vlad; Paul Bolle; linux-...@vger.kernel.org;
linux-kernel@vger.kernel.org; ker...@pengutronix.de;
Tirdea, Irina
Am 15.08.2015 um 09:48 schrieb Alexander Holler:
Am 30.07.2015 um 13:57 schrieb Alexander Holler:
Am 29.07.2015 um 11:25 schrieb Alexander Holler:
Am 23.05.2015 um 05:55 schrieb Martin KaFai Lau:
To complete the discussion, that annoying behaviour is also a big
information leak.
Because
On 14 August 2015 at 13:39, Juri Lelli juri.le...@arm.com wrote:
Hi vincent,
On 13/08/15 13:08, Vincent Guittot wrote:
On 12 August 2015 at 17:15, Juri Lelli juri.le...@arm.com wrote:
On 11/08/15 17:37, Vincent Guittot wrote:
On 11 August 2015 at 17:07, Juri Lelli juri.le...@arm.com wrote:
On 08/17/2015 11:11 AM, Alexey Kardashevskiy wrote:
On 08/17/2015 05:45 PM, Vlastimil Babka wrote:
On 08/05/2015 10:08 AM, Alexey Kardashevskiy wrote:
This is about VFIO aka PCI passthrough used from QEMU.
KVM is irrelevant here.
QEMU is a machine emulator. It allocates guest RAM from
On Mon, Aug 17, 2015 at 12:29:51PM +0100, Morten Rasmussen wrote:
On Sun, Aug 16, 2015 at 10:46:05PM +0200, Peter Zijlstra wrote:
On Fri, Aug 14, 2015 at 05:23:08PM +0100, Morten Rasmussen wrote:
Target: ARM TC2 A7-only (x3)
Test: hackbench -g 25 --threads -l 1
BeforeAfter
Some of the pin-controllers like the Qualcomms qcom,pm8921, which
require a pinconf to be setup to use pins as gpios. Using the pins
directly without pinconf setup would result in incorrect output voltage
or load settings. On the other hand pwrseq code does not configure the
pinctrl by default as
The locking scheme used in ptlrpc_deactivate_and_unlock_import and
ptlrpc_deactivate_import generates the followings sparse errors:
drivers/staging/lustre/lustre/ptlrpc/import.c:209:9: warning: context
imbalance in 'ptlrpc_deactivate_and_unlock_import' - unexpected unlock
Saturday, August 15, 2015, 12:39:25 AM, you wrote:
On Sat, 2015-08-15 at 00:09 +0200, Sander Eikelenboom wrote:
On 2015-08-13 00:41, Eric Dumazet wrote:
On Wed, 2015-08-12 at 23:46 +0200, Sander Eikelenboom wrote:
Thanks for the reminder, but luckily i was aware of that,
seen enough
Signed-off-by: Ley Foon Tan lf...@altera.com
---
MAINTAINERS | 16
1 file changed, 16 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fd60784..32f5287 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7759,6 +7759,14 @@ F: include/linux/pci*
F: arch/x86/pci/
This patch adds the bindings for Altera PCIe host controller driver and
Altera PCIe MSI driver.
Signed-off-by: Ley Foon Tan lf...@altera.com
---
.../devicetree/bindings/pci/altera-pcie-msi.txt| 27
.../devicetree/bindings/pci/altera-pcie.txt| 49 ++
2
Mediatek MT8173 is an ARMv8 based quad-core (2*Cortex-A53 and
2*Cortex-A72) SoC with duall clusters. For each cluster, two voltage
inputs, Vproc and Vsram are supplied by two regulators. For the big
cluster, two regulators come from different PMICs. In this case, when
scaling voltage inputs of the
This patch adds the required properties in device tree to enable MT8173
cpufreq driver.
Signed-off-by: Pi-Cheng Chen pi-cheng.c...@linaro.org
Acked-by: Viresh Kumar viresh.ku...@linaro.org
---
It is based on the top of MT8173 SoC maintainer's tree:
https://github.com/mbgg/linux-mediatek.git
This patch adds the clock and regulator consumer properties part of
document for CPU DVFS clocks on Mediatek MT8173 SoC.
Signed-off-by: Pi-Cheng Chen pi-cheng.c...@linaro.org
Acked-by: Michael Turquette mturque...@baylibre.com
Acked-by: Viresh Kumar viresh.ku...@linaro.org
---
On Mon, Aug 17, 2015 at 10:34:03AM +0300, Adrian Hunter wrote:
On 29/07/15 00:14, Adrian Hunter wrote:
When TSC is stable perf/sched clock is based on it.
However the conversion from cycles to nanoseconds
is not as accurate as it could be. Because
CYC2NS_SCALE_FACTOR is 10, the accuracy
Hi Phil,
On Mon, Aug 17, 2015 at 12:23 PM, Phil Edworthy
phil.edwor...@renesas.com wrote:
On 11 August 2015 13:43, Geert wrote:
On arm64/shmobile:
drivers/pci/host/pci-rcar-gen2.c: In function 'rcar_pci_cfg_base':
drivers/pci/host/pci-rcar-gen2.c:112:34: error: dereferencing pointer to
On Sun, Aug 02, 2015 at 08:41:48PM -0700, Liu.Zhao wrote:
Make sure to always include a commit message.
Also change you Subject (patch summary) to something more descriptive
using the following format:
USB: option: add ZTE PIDs
Signed-off-by: Liu.Zhao lzsos...@163.com
---
On 08/17/2015 10:01 AM, Ingo Molnar wrote:
(Sorry about the late reply, wasn't around on the weekend.)
* Linus Torvalds torva...@linux-foundation.org wrote:
Now that said, I doubt anybody cares. Since we don't support the original
80386,
the only way to ever trigger FP emulation is by
Le 17/08/2015 12:56, leroy christophe a écrit :
Le 07/08/2015 01:25, Segher Boessenkool a écrit :
On Thu, Aug 06, 2015 at 05:45:45PM -0500, Scott Wood wrote:
If this makes performance non-negligibly worse on other 32-bit
chips, and is
an important improvement on 8xx, then we can use an
On Wed, Aug 12, 2015 at 05:16:50PM -0700, David Rientjes wrote:
On Wed, 12 Aug 2015, Mel Gorman wrote:
There is a seqcounter that protects against spurious allocation failures
when a task is changing the allowed nodes in a cpuset. There is no need
to check the seqcounter until a cpuset
On Mon, Aug 17, 2015 at 12:57:24PM +0200, Alexandre Belloni wrote:
On 17/08/2015 at 12:09:14 +0200, Thierry Reding wrote :
On Sat, Aug 01, 2015 at 12:44:31AM +0200, Alexandre Belloni wrote:
From: Josh Wu josh...@atmel.com
The QiaoDian Xianshi QD43003C0-40 is a 43 TFT LCD panel.
From: pi-cheng.chen pi-cheng.c...@linaro.org
This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
for intermediate clock source switching.
Signed-off-by: Pi-Cheng Chen pi-cheng.c...@linaro.org
Reviewed-by: Daniel Kurtz djku...@chromium.org
---
Changes in v5:
- Replace
On Mon, Aug 17, 2015 at 10:23 AM, Alexandre Courbot acour...@nvidia.com wrote:
As reported by Alexey Khoroshilov:
grgpio_irq_unmap() code looks quite suspicious regarding usage of
priv-bgc.lock spinlock.
It locks the spinlock in line 310:
On Fri, Aug 14, 2015 at 01:08:32PM -0400, Raphaël Beamonte wrote:
Fix a macro with complex value coding style error.
This patch description is too vague.
regards,
dan carpenter
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to
Hi Morten,
On Tue, Jul 07, 2015 at 07:24:01PM +0100, Morten Rasmussen wrote:
From: Dietmar Eggemann dietmar.eggem...@arm.com
This patch is only here to be able to test provisioning of energy related
data from an arch topology shim layer to the scheduler. Since there is no
code today which
Hi Geert,
On 11 August 2015 13:43, Geert wrote:
On arm64/shmobile:
drivers/pci/host/pci-rcar-gen2.c: In function 'rcar_pci_cfg_base':
drivers/pci/host/pci-rcar-gen2.c:112:34: error: dereferencing pointer to
incomplete type
struct rcar_pci_priv *priv = sys-private_data;
DAPM core already creates widgets for DAIs. It is not necessary
to declare them by SND_SOC_DAPM_AIF_IN/SND_SOC_DAPM_AIF_OUT.
Furthermore, original codes use backend DAI's stream name to be the AIF
widget name. It causes the same widget to be created twice, and after
commit 92fa12426741 (ASoC:
cannot
test it.
I detected this issues with scripts/checkkconfigsymbols.py by diffing
next-20150814..next-20150817
drivers/staging/hfi1/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/hfi1/Kconfig b/drivers/staging/hfi1/Kconfig
index 87a385a02cba
On 17 August 2015 at 16:20, Li Jun b47...@freescale.com wrote:
On Mon, Aug 17, 2015 at 02:02:08PM +0800, Baolin Wang wrote:
On 17 August 2015 at 09:15, Li Jun b47...@freescale.com wrote:
On Fri, Aug 14, 2015 at 07:04:56PM +0800, Baolin Wang wrote:
On 14 August 2015 at 16:55, Li Jun
This patch adds the Altera PCIe host controller driver.
Signed-off-by: Ley Foon Tan lf...@altera.com
---
drivers/pci/host/Kconfig | 7 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-altera.c | 543 +
3 files changed, 551
On 08/17/2015 05:45 PM, Vlastimil Babka wrote:
On 08/05/2015 10:08 AM, Alexey Kardashevskiy wrote:
This is about VFIO aka PCI passthrough used from QEMU.
KVM is irrelevant here.
QEMU is a machine emulator. It allocates guest RAM from anonymous memory
and these pages are movable which is ok.
Include asm-generic/msi.h to support CONFIG_GENERIC_MSI_IRQ_DOMAIN.
This to fix compilation error:
include/linux/msi.h:123:21: fatal error: asm/msi.h:
No such file or directory
Signed-off-by: Ley Foon Tan lf...@altera.com
---
arch/arm/include/asm/Kbuild | 1 +
1 file changed, 1 insertion(+)
On Mon, Aug 17, 2015 at 3:52 PM, Yingjoe Chen yingjoe.c...@mediatek.com wrote:
On Fri, 2015-08-14 at 16:38 +0800, maoguang.m...@mediatek.com wrote:
From: Maoguang Meng maoguang.m...@mediatek.com
This patch implement irq_set_wake to get who is wakeup source and
setup on suspend resume.
On Mon, Aug 17, 2015 at 04:45:49PM +0900, byungchul.p...@lge.com wrote:
From: Byungchul Park byungchul.p...@lge.com
i am very sorry for ugly versioning..
while i proposed several indivisual patches and was feedbacked, i felt
that i needed to pack some patches into one series.
thanks,
byungchul
[...]
- mmc-max_seg_size = mmc-max_req_size;
-#endif /* CONFIG_MMC_DW_IDMAC */
+ if (host-use_dma) {
+ mmc-max_segs = host-ring_size;
I expect this may cause a compiler error since host-ring_size is only
available in the struct dw_mci *host
Hi Peter,
On 16/08/15 21:35, Peter Zijlstra wrote:
On Tue, Jul 07, 2015 at 07:24:28PM +0100, Morten Rasmussen wrote:
From: Juri Lelli juri.le...@arm.com
Use the cpu argument of cpufreq_sched_set_cap() to handle per_cpu writes,
as the thing can be called remotely (e.g., from load balacing
On Tue, Aug 04, 2015 at 02:04:35PM +, Karajgaonkar, Saurabh (S.) wrote:
From: Saurabh Karajgaonkar skara...@visteon.com
Replace redundant variable use in return statement.
Signed-off-by: Saurabh Karajgaonkar skara...@visteon.com
---
drivers/usb/serial/mxuport.c | 10 +++---
1
On Sat, Jul 25, 2015 at 8:57 AM, Andy Lutomirski l...@kernel.org wrote:
This will allow IRQ stacks to nest inside NMIs or similar entries
that can happen during IRQ stack setup or teardown.
The Xen code here has a confusing comment.
The new macros won't work correctly if they're invoked with
Hi Mark,
On Sun, Aug 16, 2015 at 09:49:27PM +0100, Mark Salter wrote:
The use of mem= could leave part or all of the initrd outside of
the kernel linear map. This will lead to an error when unpacking
the initrd and a probable failure to boot. This patch catches that
situation and relocates
On Thu, Aug 13, 2015 at 02:32:23PM +0200, Benjamin Gaignard wrote:
Add Vincent Abriou and myself has maintainers.
Signed-off-by: Benjamin Gaignard benjamin.gaign...@linaro.org
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
I'm glad to see this. I think we'll need a couple
On Mon, 17 Aug 2015 19:34:39 +0800
Jisheng Zhang jszh...@marvell.com wrote:
commit 08f90f14aa93ad424c20bb176b52f329583e2183 (mmc: sdhci: clarify
DDR timing mode between SD-UHS and eMMC) added MMC_DDR52 as eMMC's DDR
mode to be distinguished from SD-UHS, but it missed setting driver type
for
From: Dongdong Yang yangdongd...@xiaomi.com
If system restart after panic, this patch also enables
panic and oops messages which in suspend context to be
logged into ramoops console buffer where it can be read
back at some later point.
Signed-off-by: Dongdong Yang yangdongd...@xiaomi.com
On Sat, Aug 15, 2015 at 06:59:25AM +0100, Viresh Kumar wrote:
On 14-08-15, 18:56, Javi Merino wrote:
The OPP library is now used for power models to calculate the power
that a device would consume at a specific OPP. To do that, we use a
simple power model which takes frequency and voltage
On Fri, Aug 14, 2015 at 2:40 PM, Lars-Peter Clausen l...@metafoo.de wrote:
On 08/14/2015 02:34 PM, Linus Walleij wrote:
[...]
Every chip will get their own lock class on the heap.
But I think it is a bit kludgy.
Is it not possible to have the lock key in struct gpio_chip
be a real member
On Tue, Aug 11, 2015 at 02:22:43PM +0200, Mike Looijmans wrote:
Header claims GPL v2, so make the MODULE_LICENSE reflect that properly.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
---
drivers/gpu/drm/i2c/adv7511.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
The
On Fri, Aug 14, 2015 at 12:31:32PM -0700, Dustin Byford wrote:
(v2 corrects cc: list)
I would like to add support for scanning I2C devices connected to ACPI
OF compatible muxes described in ASL like this:
Device (MUX0)
{
Name (_ADR, 0x70)
Name (_HID, PRP0001)
Name (_CRS,
Hi Daniel,
Find minor comments.
Regards,
Vladimir
On 11.08.2015 01:42, Daniel Baluta wrote:
Signed-off-by: Daniel Baluta daniel.bal...@intel.com
---
Documentation/ABI/testing/configfs-iio | 20
Documentation/iio/iio_configfs.txt | 57 ++
2
On Thu 2015-08-13 12:37:27, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
API to support programming FPGA.
I'd do s/fpga/FPGA/ in the comments, too. Otherwise looks ok to me.
Acked-by: Pavel Machek pa...@denx.de
--
(english)
On 08/15/2015 11:13 PM, Chuck Ebbert wrote:
On Wed, 12 Aug 2015 10:13:24 -0400
Sasha Levin sasha.le...@oracle.com wrote:
While fuzzing with trinity inside a KVM tools guest running -next I've
stumbled on the following:
[64092.216447]
On 17/08/15 08:52, Jani Nikula wrote:
On Fri, 14 Aug 2015, Srinivas Kandagatla srinivas.kandaga...@linaro.org wrote:
This patch adds support to get edid way early before the connector is
created, this is mainly used for panel drivers to auto-probe the panel
based on the vendor and product id
-Original Message-
From: Markus Pargmann [mailto:m...@pengutronix.de]
Sent: 17 August, 2015 12:10
To: Jonathan Cameron
Cc: Tirdea, Irina; Wolfram Sang; linux-...@vger.kernel.org;
linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Pandruvada,
Srinivas; Peter Meerwald
Hi Andrew,
Thanks for the patch, few comments other than Stefan's comments.
On 16/08/15 03:54, Andrew Lunn wrote:
Add a read only regmap for accessing the EEPROM, and then use that
with the NVMEM framework.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/misc/eeprom/at24.c | 65
On Fri, Aug 14, 2015 at 01:35:53PM +0100, fu@linaro.org wrote:
From: Tomasz Nowicki tomasz.nowi...@linaro.org
This commit provides APEI arch-specific bits for aarch64
Changelog:
Fu Wei:
Move arch_apei_flush_tlb_one() to arch/arm64/include/asm/apci.h.
Delete
Hi Paul,
Currently RCU tree distributes CPUs to leafs based on consequent CPU
IDs. That means CPUs from remote caches and even nodes might end up
in the same leaf.
I did not research the impact, but at the glance that seems at least
sub-optimal; especially in case of remote nodes, when CPUs
On 17/08/2015 at 12:09:14 +0200, Thierry Reding wrote :
On Sat, Aug 01, 2015 at 12:44:31AM +0200, Alexandre Belloni wrote:
From: Josh Wu josh...@atmel.com
The QiaoDian Xianshi QD43003C0-40 is a 43 TFT LCD panel.
Timings from the OTA5180A document, ver 0.9, section
10.1.1:
Le 07/08/2015 01:25, Segher Boessenkool a écrit :
On Thu, Aug 06, 2015 at 05:45:45PM -0500, Scott Wood wrote:
If this makes performance non-negligibly worse on other 32-bit chips, and is
an important improvement on 8xx, then we can use an ifdef since 8xx already
requires its own kernel build.
If the bf_get() call in lpfc_mbx_cmpl_rdp_page_a2() does succeeds, execution
continues normally and mp gets kfree()d.
If the subsequent call to lpfc_sli_issue_mbox() fails execution jumps to the
error label where lpfc_mbuf_free() is called with mp-virt and mp-phys as
function arguments. This is
This patch fix spelling typo the the found in controls.xml
and vidioc-g-param.xml.
These xml files are generated from NOT any files, so I have
to fix these xml files.
Signed-off-by: Masanari Iida standby2...@gmail.com
---
Documentation/DocBook/media/v4l/controls.xml | 2 +-
On Thu 2015-08-13 12:37:32, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
Add simple fpga bus. This is a bus that configures an fpga and its
bridges before populating the devices below it. This is intended
for use with device tree overlays.
Note that
This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.
Signed-off-by: Ley Foon Tan lf...@altera.com
---
drivers/pci/host/Kconfig | 8 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-altera-msi.c |
On Sun, Aug 16, 2015 at 10:24:47AM +0100, Jonathan Cameron wrote:
On 12/08/15 15:31, Irina Tirdea wrote:
Some i2c busses (e.g.: Synopsys DesignWare I2C adapter) need to
enable/disable the bus at each i2c transfer and must wait for
the enable/disable to happen before sending the data.
This is the 4th version of patch set to add support for Altera PCIe host
controller with MSI feature on Altera FPGA device families. This patchset
mainly resolve comments from Marc Zyngier in v3.
It is based on patch series from Marc Zyngier Per-device MSI domain
platform MSI [1] to get rid of
On Sun, Aug 16, 2015 at 01:30:12AM -0400, Raphaël Beamonte wrote:
#define MALLOC_WILC_BUFFER(name, size) \
- exported_ ## name = kmalloc(size, GFP_KERNEL);\
- if (!exported_ ## name) { \
- printk(fail to alloc: %s memory\n, exported_ ## name); \
-
On Mon, Aug 17, 2015 at 02:02:08PM +0800, Baolin Wang wrote:
On 17 August 2015 at 09:15, Li Jun b47...@freescale.com wrote:
On Fri, Aug 14, 2015 at 07:04:56PM +0800, Baolin Wang wrote:
On 14 August 2015 at 16:55, Li Jun b47...@freescale.com wrote:
Hi Baolin,
On Fri, Aug 14, 2015 at
On Mon, Aug 17, 2015 at 12:47 PM, Alexandre Courbot gnu...@gmail.com wrote:
On Thu, Aug 13, 2015 at 4:29 PM, Vaishali Thakkar
vthakkar1...@gmail.com wrote:
Use managed resource functions devm_clk_put and
devm_snd_soc_register_component to simplify error handling.
To be compatible with the
On 3 August 2015 at 17:04, Heiko Stübner he...@sntech.de wrote:
The dw_mci_init_dma() may decide to not use dma, but pio instead, caused
by things like wrong dma settings in the system.
Till now the code dw_mci_init_slot() always assumed that dma is available
when CONFIG_MMC_DW_IDMAC was
Hi all,
Changes since 20150813:
Dropped tree: drm-exynos
The pci tree gained a conflict against the arm-soc tree.
The v4l-dvb tree still had its build failure so I used the version from
next-20150810.
The pm tree gained a conflict against the samsung tree.
The thermal-soc tree gained a
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