On 30.10.2015 15:25, Alim Akhtar wrote:
> From: Thomas Abraham
>
> Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device
> is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators.
> This also supports RTC and three 32.768KHz clock
set an id for crypto clk, so that it can be called in other part.
Signed-off-by: Zain Wang
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
This commit support three cipher(AES/DES/DES3) and two chainmode(ecb/cbc),
and the more algorithms or new hash drivers will be added later on.
Zain Wang (4):
Crypto: Crypto driver support aes/des/des3 for rk3288
clk: rockchip: set an id for crypto clk
ARM: dts: rockchip: Add Crypto drivers
Add DT bindings documentation for the rk3288 crypto drivers.
Signed-off-by: Zain Wang
---
.../devicetree/bindings/crypto/rk-crypto.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644
Hello!
> -Original Message-
> From: linux-samsung-soc-ow...@vger.kernel.org
> [mailto:linux-samsung-soc-ow...@vger.kernel.org]
> On Behalf Of Pankaj Dubey
> Sent: Thursday, October 29, 2015 8:28 PM
> To: Pavel Fedin
> Cc: devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
Hi Bjorn,
On 29 October 2015 23:03, Bjorn wrote:
> On Thu, Oct 29, 2015 at 07:48:00PM +0100, Wolfram Sang wrote:
> > On Thu, Oct 29, 2015 at 04:44:06PM +, Phil Edworthy wrote:
> > > Hi Wolfram,
> > >
> > > On 29 October 2015 16:40, Wolfram wrote:
> > > > > Ouch, my bad. I have been working
Do you need a direct,easy and fast loan offer from a bank or a private lender.
We offer loan at 3% per anum. Please reply us if you need a loan. phone number
: +(1)614-392-8352
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the body
In eDMA the events are directly mapped to a DMA channel (for example DMA
event 14 can only be handled by DMA channel 14). If the memcpy is enabled
on the eDMA, there is a possibility that the crossbar driver would assign
DMA event number already allocated in eDMA for memcpy. Furthermore the
eDMA
Hi,
Changes since v1:
- Fixed issue introduced by the bitops patch: wrong error check, also switch to
use find_first_zero_bit() instead of find_next_zero_bit()
Cover letter:
This series depends on the eDMA work I have done, which has been now applied:
https://lkml.org/lkml/2015/10/16/64
DRA7
On 10/28/2015 12:15 PM, Yaniv Gardi wrote:
> This patch adds ufshcd_get_variant() and ufshcd_set_variant()
> routines in order to get/set the variant specific data.
>
> Reviewed-by: Akinobu Mita
> Reviewed-by: Subhash Jadavani
> Reviewed-by:
On Tuesday 27 October 2015 17:50:24 Jens Kuske wrote:
>
> +static int sun8i_h3_bus_reset_xlate(struct reset_controller_dev *rcdev,
> + const struct of_phandle_args *reset_spec)
> +{
> + unsigned int index = reset_spec->args[0];
> +
> + if (index < 96)
On Thu, Oct 29, 2015 at 12:21 PM, Geert Uytterhoeven
wrote:
> Add a new R-Car H3 Clock Pulse Generator / Module Standby and Software
> Reset driver, using the new CPG/MSSR driver core.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> v5:
> -
Add Crypto drivers for rk3288 including crypto controller and dma clk.
Signed-off-by: Zain Wang
---
arch/arm/boot/dts/rk3288.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index
On 10/30/2015 05:07 AM, Jon Masters wrote:
Hi Tomasz,
Thanks for posting this series.
On 10/27/2015 12:38 PM, Tomasz Nowicki wrote:
From the functionality point of view this series might be split into two logic
parts:
1. Making MMCONFIG code arch-agnostic which allows all architectures to
On 10/28/2015 12:15 PM, Yaniv Gardi wrote:
> This change is required in order to be able to build the component
> as a module.
>
> Reviewed-by: Akinobu Mita
> Reviewed-by: Subhash Jadavani
> Reviewed-by: Gilad Broner
>
Crypto driver support cbc/ecb two chainmode, and aes/des/des3 three cipher mode.
The names registered are:
ecb(aes) cbc(aes) ecb(des) cbc(des) ecb(des3_ede) cbc(des3_ede)
You can alloc tags above in your case.
And other algorithms and platforms will be added later on.
Signed-off-by: Zain
On 10/30/2015, Sudip Mukherjee wrote:
On Thu, Oct 29, 2015 at 09:15:01PM +0100, Bogicevic Sasa wrote:
This fixes all errors about alignment with open parentheses as well as
one spacing needed around "-" sign since the patch would not be valid if
I left it there
1) That becomes two different
Am Freitag, 30. Oktober 2015, 16:22:46 schrieb Zain Wang:
Hi Zain,
>Crypto driver support cbc/ecb two chainmode, and aes/des/des3 three cipher
>mode. The names registered are:
>ecb(aes) cbc(aes) ecb(des) cbc(des) ecb(des3_ede) cbc(des3_ede)
>You can alloc tags above in your case.
>
>And
Hi Bjorn,
On 30 October 2015 07:24, Phil wrote:
> On 30 October 2015 07:19, Phil wrote
> > On 29 October 2015 23:03, Bjorn wrote:
> > > On Thu, Oct 29, 2015 at 07:48:00PM +0100, Wolfram Sang wrote:
> > > > On Thu, Oct 29, 2015 at 04:44:06PM +, Phil Edworthy wrote:
> > > > > Hi Wolfram,
> > >
在 2015/10/29 23:09, Will Deacon 写道:
> On Thu, Oct 29, 2015 at 09:35:42PM +0800, kbuild test robot wrote:
>> [auto build test ERROR on arm64/for-next/core -- if it's inappropriate base,
>> please suggest rules for selecting the more suitable base]
>>
>> url:
>>
Hi Sinan,
[auto build test ERROR on lwn/docs-next -- if it's inappropriate base, please
suggest rules for selecting the more suitable base]
url:
https://github.com/0day-ci/linux/commits/Sinan-Kaya/dma-add-Qualcomm-Technologies-HIDMA-management-driver/20151030-111408
config: i386
Hi Stephan,
> For supporting asymmetric ciphers, user space must be able to set the
> public key. The patch adds a new setsockopt call for setting the public
> key.
>
> Signed-off-by: Stephan Mueller
> ---
> crypto/af_alg.c | 14 +++---
>
From: Zhang Rui
Current thermal code does not handle system sleep well because
1. the cooling device cooling state may be changed during suspend
2. the previous temperature reading becomes invalid after resumed because
it is got before system sleep
3. updating thermal
When a new cooling device is registered, we need to update the
thermal zone to set the new registered cooling device to a proper
state.
This fixes a problem that the system is cool, while the fan devices
are left running on full speed after boot, if fan device is registered
after thermal zone
This patch set fixes two problems when system is trying to
suspend and boot up:
1.After system is woken up from suspend, the thermal framework uses
the dirty 'cached' thermal variables before suspend, which might
cause expected behavior.
2.If a cooling device is registered after the thermal
From: Zhang Rui
After thermal zone device registered, as we have not read any
temperature before, thus tz->temperature should not be 0,
which actually means 0C, and thermal trend is not available.
In this case, we need specially handling for the first
On Fri, Oct 30, 2015 at 03:21:29AM +, John Youn wrote:
> On 10/29/2015 9:43 AM, Doug Anderson wrote:
> > John,
> >
> > On Thu, Oct 22, 2015 at 1:05 PM, Douglas Anderson
> > wrote:
> >> In commit 734643dfbdde ("usb: dwc2: host: add flag to reflect bus
> >> state") we
On 10/28/2015 12:15 PM, Yaniv Gardi wrote:
> In order to simplify the code a set of wrapper functions is created
> to test and call each of the variant operations.
>
> Reviewed-by: Akinobu Mita
> Reviewed-by: Subhash Jadavani
> Reviewed-by: Gilad
on 2015/10/30 16:31, Li Bin wrote:
> In nop_mcount, shdr->sh_offset and welp->r_offset should handle
> endianness properly, otherwise it will trigger Segmentation fault
> if the recordmcount main and file.o have different endianness.
>
For more information, please refer to
On Fri, Oct 30, 2015 at 04:22:46PM +0800, Zain Wang wrote:
> Crypto driver support cbc/ecb two chainmode, and aes/des/des3 three cipher
> mode.
> The names registered are:
> ecb(aes) cbc(aes) ecb(des) cbc(des) ecb(des3_ede) cbc(des3_ede)
> You can alloc tags above in your case.
>
> And other
On 2015/10/23 10:44, Luck, Tony wrote:
> First part of each memory controller. I have two memory controllers on each
> node
>
If each memory controller has the same distance/latency, you (your firmware)
don't need
to allocate reliable memory per each memory controller.
If distance is problem,
The NAND controller on NS2 SoC is compatible with existing
BRCM IPROC NAND driver so let's enable it in NS2 DT and
NS2 SVK DT.
This patch also fixes use of node labels in ns2-svk.dts.
Signed-off-by: Anup Patel
Reviewed-by: Ray Jui
Reviewed-by: Scott
as return type of function rds_iw_flush_mr_pool no where checked, chnaging its
return type from int to void.
also removing the unused variable rc as there is nothing to return.
Signed-off-by: Saurabh Sengar
---
net/rds/iw_rdma.c | 6 ++
1 file changed, 2
From: Brian Norris
Use enum instead of magic numbers for CFG and CFG_EXT bitfields.
Signed-off-by: Brian Norris
Tested-by: Anup Patel
---
drivers/mtd/nand/brcmnand/brcmnand.c | 38
On 29.10.2015 21:42, Pavel Fedin wrote:
> Add documentation for new subnode properties, allowing bank configuration.
> Based on u-boot implementation, but heavily reworked.
Please, carefully look at:
Documentation/devicetree/bindings/net/gpmc-eth.txt
On Monday 26 October 2015 06:14 PM, Anju T wrote:
> The registers to sample are passed through the sample_regs_intr bitmask.
> The name and bit position for each register is defined in asm/perf_regs.h.
> This feature can be enabled by using -I option with perf record command.
> To display the
On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske wrote:
> Currently, the sunxi clock driver gets the name for the base factor clock
> of divs clocks from the name field in factors_data. This prevents reusing
> of the factor clock for clocks with same properties, but different
McASP3 is used by default on DRA7x based boards for audio.
Signed-off-by: Peter Ujfalusi
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 56 +++
1 file changed, 56 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
Some module needs more than one functional clock in order to be accessible,
like the McASPs found in DRA7xx family.
This flag will indicate that the opt_clks need to be handled at the same
time as the main_clk for the given hwmod, ensuring that all needed clocks
are enabled before we try to access
McASP node needs to list all mandatory clocks: gfclk and ahclkx
Signed-off-by: Peter Ujfalusi
---
arch/arm/boot/dts/dra7.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index
Hi Paul, Tony,
Changes since v2:
- DTS patch added which is needed because of the clock handling changes
Felip Balbi reported that linux-next is broken right now since the DTS part of
the earlier series has been applied, but we do not have the mcasp hwmod in the
kernel:
...
[0.181029]
By now, the recordmcount only records the function that in
following sections:
.text/.ref.text/.sched.text/.spinlock.text/.irqentry.text/
.kprobes.text/.text.unlikely
For the function that not in these sections, the call mcount
will be in place and not be replaced when kernel boot up. And
it will
Although, the default value of rel_type_nop is zero, and the value
of R_386_NONE/R_X86_64_NONE is zero too, but it should be assigned
a meaningful value explicitly, otherwise it looks confused.
Assign R_386_NONE to rel_type_nop for 386, assign R_X86_64_NONE
to rel_type_nop for x86_64.
Li Bin (3):
recordmcount: fix endianness handling bug for nop_mcount
recordmcount: x86: assign a meaningful value to rel_type_nop
recordmcount: arm64: replace the ignored mcount call into nop
scripts/recordmcount.c | 26 +-
scripts/recordmcount.h | 5 +++--
2 files
On Thu, Oct 29, 2015 at 11:50:47PM +0200, Kirill A. Shutemov wrote:
...
>
> Okay, the problem is that the page was freed under stable_page_flags().
>
> Is the code performance sensitive? Can we get reference to the page before
> touching it? If not, we can rewrite the helper like this:
>
>
on 2015/10/30 16:31, Li Bin wrote:
> By now, the recordmcount only records the function that in
> following sections:
> .text/.ref.text/.sched.text/.spinlock.text/.irqentry.text/
> .kprobes.text/.text.unlikely
>
> For the function that not in these sections, the call mcount
> will be in place
On Thu, Oct 29, 2015 at 03:07:58AM -0400, Steven Rostedt wrote:
> static ssize_t
> ftrace_event_pid_write(struct file *filp, const char __user *ubuf,
> size_t cnt, loff_t *ppos)
> @@ -1711,6 +1727,12 @@ ftrace_event_pid_write(struct file *filp, const char
> __user *ubuf,
>
From: Thomas Abraham
The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
27 LDO and 10 Buck regulators and allows programming these regulators via a
I2C interface. This patch adds initial support for LDO/Buck regulators of
S2MPS15 PMIC.
From: Thomas Abraham
Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15
PMIC supports 27 LDO regulators, 10 buck regulators, RTC, three 32.768KHz
clock outputs and battery charger. This patch adds initial support for
LDO and buck regulators of
From: Thomas Abraham
Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device
is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators.
This also supports RTC and three 32.768KHz clock outputs.
Cc: devicet...@vger.kernel.org
RTC found in s2mps15 is almost same as one found on s2mps13
with few differences in RTC_UPDATE register fields, like:
1> Bit[4] and Bit[1] are reversed
- On s2mps13
WUDR -> bit[4], AUDR -> bit[1]
- On s2mps15
WUDR -> bit[1], AUDR -> bit[4]
2> In case of s2mps13, for alarm
Samsung's S2MPS15 PMIC is targetted to be used with Samsung's Exynos7 SoC.
The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
27 LDO and 10 Buck regulators, RTC, three 32.768 KHz clock outputs and allows
programming these blocks via a I2C interface. This patch series adds
Linux doesn't have an ability to free pages lazy while other OS already
have been supported that named by madvise(MADV_FREE).
The gain is clear that kernel can discard freed pages rather than swapping
out or OOM if memory pressure happens.
Without memory pressure, freed pages would be reused by
MADV_FREE is on linux-next so long time. The reason was two, I think.
1. MADV_FREE code on reclaim path was really mess.
2. Andrew really want to see voice of userland people who want to use
the syscall.
A few month ago, Daniel Micay(jemalloc active contributor) requested me
to make progress
Hi Bjorn,
On 30 October 2015 07:19, Phil wrote
> On 29 October 2015 23:03, Bjorn wrote:
> > On Thu, Oct 29, 2015 at 07:48:00PM +0100, Wolfram Sang wrote:
> > > On Thu, Oct 29, 2015 at 04:44:06PM +, Phil Edworthy wrote:
> > > > Hi Wolfram,
> > > >
> > > > On 29 October 2015 16:40, Wolfram
On 10/21/2015 07:33 AM, Douglas Anderson wrote:
The comment for ahbcfg for rk3066 parameters (also used for rk3288)
claimed that ahbcfg was INCR16, but it wasn't. Since the bits weren't
shifted properly, the 0x7 ended up being masked and we ended up
programming 0x3 for the HBstLen. Let's set
Hi,
On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske wrote:
> The H3 uses the same pin controller as previous SoC's from Allwinner.
> Add support for the pins controlled by the main PIO controller.
>
> Signed-off-by: Jens Kuske
> Acked-by: Maxime Ripard
On Fri 30-10-15 14:23:59, KAMEZAWA Hiroyuki wrote:
> On 2015/10/30 0:17, mho...@kernel.org wrote:
[...]
> > @@ -3135,13 +3145,56 @@ __alloc_pages_slowpath(gfp_t gfp_mask, unsigned int
> > order,
> > if (gfp_mask & __GFP_NORETRY)
> > goto noretry;
> >
> > - /* Keep reclaiming
On 10/28/2015 07:39 PM, Alexander Potapenko wrote:
> Add GFP flags to KASAN hooks for future patches to use.
Really? These flags are still not used in the next patch (unless I missed
something).
> This is the first part of the "mm: kasan: unified support for SLUB and
> SLAB allocators" patch
On Fri 30-10-15 14:48:40, KAMEZAWA Hiroyuki wrote:
[...]
> > @@ -3191,8 +3191,23 @@ __alloc_pages_slowpath(gfp_t gfp_mask, unsigned int
> > order,
> > */
> > if (__zone_watermark_ok(zone, order, min_wmark_pages(zone),
> > ac->high_zoneidx,
On Fri 30-10-15 12:18:50, Hillf Danton wrote:
>
> > --- a/mm/page_alloc.c
> > +++ b/mm/page_alloc.c
> > @@ -3191,8 +3191,23 @@ __alloc_pages_slowpath(gfp_t gfp_mask, unsigned int
> > order,
> > */
> > if (__zone_watermark_ok(zone, order, min_wmark_pages(zone),
> >
On 30.10.2015 15:25, Alim Akhtar wrote:
> RTC found in s2mps15 is almost same as one found on s2mps13
> with few differences in RTC_UPDATE register fields, like:
> 1> Bit[4] and Bit[1] are reversed
>- On s2mps13
> WUDR -> bit[4], AUDR -> bit[1]
>- On s2mps15
> WUDR ->
On 10/28/2015 12:15 PM, Yaniv Gardi wrote:
> Export the following functions in order to avoid build errors
> when the component PHY_QCOM_UFS is compiled as a module:
>
> ERROR: "ufs_qcom_phy_disable_ref_clk"
> [drivers/scsi/ufs/ufs-qcom.ko] undefined!
> ERROR: "ufs_qcom_phy_enable_ref_clk"
Hi Zain,
Am Freitag, 30. Oktober 2015, 16:22:47 schrieb Zain Wang:
> set an id for crypto clk, so that it can be called in other part.
>
> Signed-off-by: Zain Wang
> ---
> drivers/clk/rockchip/clk-rk3288.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
>
> Thanks for the conversion. Can you please check if other (scsi) drivers
> have the same y2038 issues? A quick "git grep do_gettimeofday
> drivers/scsi/ | wc -l" reveals 30 occurrences (of cause not all are
> problematic).
>
Hi Johannes,
Yes, there are quite a few occurrences of timeval
Crypto driver support cbc/ecb two chainmode, and aes/des/des3 three cipher mode.
The names registered are:
ecb(aes) cbc(aes) ecb(des) cbc(des) ecb(des3_ede) cbc(des3_ede)
You can alloc tags above in your case.
And other algorithms and platforms will be added later on.
Signed-off-by: Zain
Add Crypto drivers for rk3288 including crypto controller and dma clk.
Signed-off-by: Zain Wang
---
arch/arm/boot/dts/rk3288.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index
Add DT bindings documentation for the rk3288 crypto drivers.
Signed-off-by: Zain Wang
---
.../devicetree/bindings/crypto/rk-crypto.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644
set an id for crypto clk, so that it can be called in other part.
Signed-off-by: Zain Wang
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
This commit support three cipher(AES/DES/DES3) and two chainmode(ecb/cbc),
and the more algorithms or new hash drivers will be added later on.
Zain Wang (4):
Crypto: Crypto driver support aes/des/des3 for rk3288
clk: rockchip: set an id for crypto clk
ARM: dts: rockchip: Add Crypto drivers
Hello!
> > Add documentation for new subnode properties, allowing bank configuration.
> > Based on u-boot implementation, but heavily reworked.
>
> Please, carefully look at:
> Documentation/devicetree/bindings/net/gpmc-eth.txt
> Documentation/devicetree/bindings/bus/ti-gpmc.txt
Thank you
> -Original Message-
> From: Anup Patel [mailto:anup.pa...@broadcom.com]
> Sent: 30 October 2015 11:49
> To: David Woodhouse; Brian Norris; Linux MTD
> Cc: Rob Herring; Pawel Moll; Mark Rutland; Catalin Marinas; Will Deacon;
> Sudeep Holla; Ian Campbell; Kumar Gala; Ray Jui; Scott
Hi All,
Please disregard this patchset.
There is an accidental typo in patch2.
We should use ~CFG_BUS_WIDTH instead of CFG_BUS_WIDTH
in patch2. I will quickly send v5 patchset to fix this.
Sorry, for the noise.
Regards,
Anup
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On Thu, Oct 29, 2015 at 07:28:21PM -0400, James Simmons wrote:
> With nidstring now having the latest fixes we can
> now clean up all the remaining checkpatch errors
> for nidstring.c.
>
> Signed-off-by: James Simmons
> ---
You are doing different types of changes in
The commit 54e8827d5f0e ("mfd: sec-core: Add support for S2MPU02
device") added new MFD child devices for S2MPU02: RTC and clock
provider (the clock provider with new compatible). However support for
these devices was not added to existing drivers (rtc-s5m, clk-s2mps11).
New drivers were not
On 10/28/2015 12:15 PM, Yaniv Gardi wrote:
> New revisions of UFS host controller supports the new UniPro
> hardware controller (referred as QUniPro). This patch adds
> the support to enable this new UniPro controller hardware.
>
> This change also adds power optimization for bus scaling feature,
Implement an ARM delay timer to be used for udelay(). This allows us to
skip the delay loop calibration at boot on Marvell BG2, BG2Q, BG2CD
platforms. And after this patch, udelay() will be unaffected by CPU
frequency changes.
Signed-off-by: Jisheng Zhang
---
On 10/28/2015 12:15 PM, Yaniv Gardi wrote:
> Adds support for configuring and reading the test bus and debug
> registers. This change also adds another vops in order to print the
> debug registers.
>
> Reviewed-by: Subhash Jadavani
> Reviewed-by: Gilad Broner
In nop_mcount, shdr->sh_offset and welp->r_offset should handle
endianness properly, otherwise it will trigger Segmentation fault
if the recordmcount main and file.o have different endianness.
Cc: # 3.0+
Signed-off-by: Li Bin
---
Hi,
On Fri, 2015-10-30 at 01:30 -0700, Tina Ruchandani wrote:
> Function stex_gettime uses 'struct timeval' whose tv_sec value
> will overflow on 32-bit systems in year 2038 and beyond. This patch
> replaces the use of struct timeval and do_gettimeofday with
> ktime_get_real_seconds, which
UUID calculation uses 'struct timespec' whose seconds will overflow
in year 2038 and beyond for 32-bit systems. This patch removes the
dependency on 'struct timespec' by using ktime_get_real().
While the patch does not fix a 'bug' as such, it is part of a larger
effort to remove instances of
Hi Daniel,
[auto build test ERROR on tip/timers/core -- if it's inappropriate base, please
suggest rules for selecting the more suitable base]
url:
https://github.com/0day-ci/linux/commits/Daniel-Lezcano/time-Define-dummy-functions-for-the-generic-sched-clock/20151030-065823
config: parisc
On certain hardware after software reboot the chip may get stuck and fail
to reinitialize during reset. This can be fixed by ensuring that PHY is
reset too.
Old PHY resetting method required operational MDIO interface, therefore
the chip should have been already set up. In order to be able to
Use devm_ioremap_resource() in order to make the code simpler,
and remove redundant return value check of platform_get_resource()
because this value is alreadytaken care by devm_ioremap_resource()
Signed-off-by: Sanjeev Sharma
---
drivers/pinctrl/pinctrl-single.c | 21
This patch changes the use of struct timespec in
dccp_probe to use struct timespec64 instead. timespec uses a 32-bit
seconds field which will overflow in the year 2038 and beyond. timespec64
uses a 64-bit seconds field. Note that the correctness of the code isn't
changed, since the original code
Am Freitag, 30. Oktober 2015, 17:16:47 schrieb Marcel Holtmann:
Hi Marcel,
>Hi Stephan,
>
>> For supporting asymmetric ciphers, user space must be able to set the
>> public key. The patch adds a new setsockopt call for setting the public
>> key.
>>
>> Signed-off-by: Stephan Mueller
On Thu, Oct 29, 2015 at 10:45:44AM +0100, Paolo Bonzini wrote:
>
>
> On 29/10/2015 04:11, Alex Williamson wrote:
> > > The irqfd is already able to schedule a work item, because it runs with
> > > interrupts disabled, so I think we can always return IRQ_HANDLED.
> >
> > I'm confused by this.
Most architectures use asm-generic, but alpha, mips, parisc, xtensa
need their own definitions.
This patch defines MADV_FREE for them so it should fix build break
for their architectures.
Maybe, I should split and feed piecies to arch maintainers but
included here for mmotm convenience.
Cc:
From: Brian Norris
Use enum instead of magic numbers for CFG and CFG_EXT bitfields.
Signed-off-by: Brian Norris
Tested-by: Anup Patel
---
drivers/mtd/nand/brcmnand/brcmnand.c | 38
We enable NAND support for Broadcom NS2 SoC by reusing existing
BRCMNAND driver.
This patchset applies on-top of "arm64: Simple additions to
NS2 DT" v1 patchset and is available in ns2_nand_v5 branch of
https://github.com/Broadcom/arm64-linux.git.
The patchset is tested on NS2 SVK.
Changes
Just like other NAND controllers, the NAND READID command only works
in 8bit mode for all versions of BRCMNAND controller.
This patch forces 8bit mode for each NAND CS in brcmnand_init_cs()
before doing nand_scan_ident() to ensure that BRCMNAND controller
is in 8bit mode when NAND READID command
The NAND controller on NS2 SoC is compatible with existing
BRCM IPROC NAND driver so let's enable it in NS2 DT and
NS2 SVK DT.
This patch also fixes use of node labels in ns2-svk.dts.
Signed-off-by: Anup Patel
Reviewed-by: Ray Jui
Reviewed-by: Scott
removing unused variables, found by coccinelle
Signed-off-by: Saurabh Sengar
---
arch/x86/kvm/x86.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 9a9a198..ec15294 100644
---
Hi,
On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske wrote:
> The Allwinner H3 is a home entertainment system oriented SoC with
> four Cortex-A7 cores and a Mali-400MP2 GPU.
>
> Signed-off-by: Jens Kuske
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 482
>
Hi Sinan,
[auto build test ERROR on lwn/docs-next -- if it's inappropriate base, please
suggest rules for selecting the more suitable base]
url:
https://github.com/0day-ci/linux/commits/Sinan-Kaya/dma-add-Qualcomm-Technologies-HIDMA-management-driver/20151030-111408
config: i386
For the record...
On 10/29/2015 10:28 AM, Peter Ujfalusi wrote:
> The use of idr was nice, but it was a bit heavy and we did not need the
> features it provides. Using simple bitmap to track allocated DMA channels
> is adequate here and it will be easier to add support for reserving
> channels
On Tuesday 27 October 2015 17:50:22 Jens Kuske wrote:
> + of_property_read_string_index(node, "clock-output-names",
> + i, _name);
> +
> + if (index == 17 || (index >= 29 && index <= 31))
> + clk_parent =
Function stex_gettime uses 'struct timeval' whose tv_sec value
will overflow on 32-bit systems in year 2038 and beyond. This patch
replaces the use of struct timeval and do_gettimeofday with
ktime_get_real_seconds, which returns a 64-bit seconds value.
Suggested-by: Arnd Bergmann
On 10/28/2015 12:15 PM, Yaniv Gardi wrote:
> This change turns the UFS variant (SCSI_UFS_QCOM) into a UFS
> a platform device.
> In order to do so a few additional changes are required:
> 1. The ufshcd-pltfrm is no longer serves as a platform device.
>Now it only serves as a group of platform
Just like other NAND controllers, the NAND READID command only works
in 8bit mode for all versions of BRCMNAND controller.
This patch forces 8bit mode for each NAND CS in brcmnand_init_cs()
before doing nand_scan_ident() to ensure that BRCMNAND controller
is in 8bit mode when NAND READID command
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