[PATCH 07/12] staging: lustre: libcfs: Fix NUMA emulated mode

From: Andriy Skulysh Kernel commit c1c3443c9c5e9be92641029ed229a41563e44506 assigns all allowed cpus to emulated node. End cpt initialization loop when all CPUs are assigned. Signed-off-by: Andriy Skulysh Intel-bug-id: https://jira.hpdd.intel.com/browse/LU-3992 Reviewed-on:

[PATCH 04/12] staging: lustre: ldlm: check all errors during ldlm_debugfs_setup()

From: Dmitry Eremin Fix ignoring errors from ldebugfs_add_vars() function. Signed-off-by: Dmitry Eremin Intel-bug-id: https://jira.hpdd.intel.com/browse/LU-3885 Reviewed-on: http://review.whamcloud.com/8115 Reviewed-by: John L. Hammond Reviewed-by: Andreas Dilger Signed-off-by: James Simmons

[PATCH 03/12] staging: lustre: ptlrpc: use unified handler for OST requests

From: Mikhail Pershin Switch OST/OFD request processing to the unified request handle. Signed-off-by: Mikhail Pershin Intel-bug-id: https://jira.hpdd.intel.com/browse/LU-3467 Reviewed-on: http://review.whamcloud.com/7130 Reviewed-by: Andreas Dilger Reviewed-by: Alex Zhuravlev Signed-off-by:

[PATCH 01/12] staging: lustre: obd: remove newline from LCONSOLE string

From: Amir Shehata Remove the newline from the LCONSOLE debug macro in the function class_config_dump_handler(). Signed-off-by: Amir Shehata Intel-bug-id: https://jira.hpdd.intel.com/browse/LU-2149 Reviewed-on: http://review.whamcloud.com/4254 Reviewed-by: Alex Zhuravlev Reviewed-by: Andreas

[PATCH 09/12] staging: lustre: llite: check ret of ll_prep_md_op_data in ll_dir_filler

From: Swapnil Pimpale ll_dir_filler() now checks the returned pointer from ll_prep_md_op_data() using IS_ERR() Signed-off-by: Swapnil Pimpale Intel-bug-id: https://jira.hpdd.intel.com/browse/LU-4082 Reviewed-on: http://review.whamcloud.com/8073 Reviewed-by:

[PATCH 09/12] staging: lustre: llite: check ret of ll_prep_md_op_data in ll_dir_filler

From: Swapnil Pimpale ll_dir_filler() now checks the returned pointer from ll_prep_md_op_data() using IS_ERR() Signed-off-by: Swapnil Pimpale Intel-bug-id: https://jira.hpdd.intel.com/browse/LU-4082 Reviewed-on: http://review.whamcloud.com/8073 Reviewed-by: Dmitry Eremin Reviewed-by: John L.

Re: [PATCH v14 2/2] drm/bridge: Add I2C based driver for ps8640 bridge

On Thu, 2016-04-14 at 16:28 +0200, Thierry Reding wrote: > On Sun, Apr 03, 2016 at 12:20:45PM +0800, Jitao Shi wrote: > [...] > > diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c > > b/drivers/gpu/drm/bridge/parade-ps8640.c > > new file mode 100644 > > index 000..87f8bc7 > > --- /dev/null

Re: [PATCH v14 2/2] drm/bridge: Add I2C based driver for ps8640 bridge

On Thu, 2016-04-14 at 16:28 +0200, Thierry Reding wrote: > On Sun, Apr 03, 2016 at 12:20:45PM +0800, Jitao Shi wrote: > [...] > > diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c > > b/drivers/gpu/drm/bridge/parade-ps8640.c > > new file mode 100644 > > index 000..87f8bc7 > > --- /dev/null

[PATCH net v3 2/5] drivers: net: cpsw: fix segfault in case of bad phy-handle

From: David Rivshin If an emac node has a phy-handle property that points to something which is not a phy, then a segmentation fault will occur when the interface is brought up. This is because while phy_connect() will return ERR_PTR() on failure, of_phy_connect() will

[PATCH net v3 2/5] drivers: net: cpsw: fix segfault in case of bad phy-handle

From: David Rivshin If an emac node has a phy-handle property that points to something which is not a phy, then a segmentation fault will occur when the interface is brought up. This is because while phy_connect() will return ERR_PTR() on failure, of_phy_connect() will return NULL. The common

Re: [PATCH V4] audit: add tty field to LOGIN event

On 16/04/22, Peter Hurley wrote: > On 04/21/2016 11:14 AM, Richard Guy Briggs wrote: > > The tty field was missing from AUDIT_LOGIN events. > > > > Refactor code to create a new function audit_get_tty(), using it to > > replace the call in audit_log_task_info() and to add it to > >

Re: [PATCH V4] audit: add tty field to LOGIN event

On 16/04/22, Peter Hurley wrote: > On 04/21/2016 11:14 AM, Richard Guy Briggs wrote: > > The tty field was missing from AUDIT_LOGIN events. > > > > Refactor code to create a new function audit_get_tty(), using it to > > replace the call in audit_log_task_info() and to add it to > >

[PATCH net v3 1/5] drivers: net: cpsw: fix parsing of phy-handle DT property in dual_emac config

From: David Rivshin Commit 9e42f715264ff158478fa30eaed847f6e131366b ("drivers: net: cpsw: add phy-handle parsing") saved the "phy-handle" phandle into a new cpsw_priv field. However, phy connections are per-slave, so the phy_node field should be in cpsw_slave_data rather

[PATCH net v3 1/5] drivers: net: cpsw: fix parsing of phy-handle DT property in dual_emac config

From: David Rivshin Commit 9e42f715264ff158478fa30eaed847f6e131366b ("drivers: net: cpsw: add phy-handle parsing") saved the "phy-handle" phandle into a new cpsw_priv field. However, phy connections are per-slave, so the phy_node field should be in cpsw_slave_data rather than cpsw_priv. This

Re: [PATCH perf/core v5 02/15] perf-buildid-cache: Use path/to/bin/buildid/elf instead of path/to/bin/buildid

Hi Masami, On Thu, Apr 28, 2016 at 03:37:23AM +0900, Masami Hiramatsu wrote: > From: Masami Hiramatsu > > Use path/to/bin/buildid/elf instead of path/to/bin/buildid > to store corresponding elf binary. > This also stores vdso in buildid/vdso, kallsyms in

Re: [PATCH perf/core v5 02/15] perf-buildid-cache: Use path/to/bin/buildid/elf instead of path/to/bin/buildid

Hi Masami, On Thu, Apr 28, 2016 at 03:37:23AM +0900, Masami Hiramatsu wrote: > From: Masami Hiramatsu > > Use path/to/bin/buildid/elf instead of path/to/bin/buildid > to store corresponding elf binary. > This also stores vdso in buildid/vdso, kallsyms in buildid/kallsyms. > > Note that the

Re: [PATCH] mptsas: fix checks for dma mapping errors

> "Alexey" == Alexey Khoroshilov writes: Alexey> mptsas_smp_handler() checks for dma mapping errors by comparison Alexey> returned address with zero, while pci_dma_mapping_error() should Alexey> be used. Broadcom folks, please review! -- Martin K. Petersen

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Re: [PATCH] mptsas: fix checks for dma mapping errors

> "Alexey" == Alexey Khoroshilov writes: Alexey> mptsas_smp_handler() checks for dma mapping errors by comparison Alexey> returned address with zero, while pci_dma_mapping_error() should Alexey> be used. Broadcom folks, please review! -- Martin K. Petersen Oracle Linux Engineering

[PATCH 01/21] X86_64, UV: Add Initial UV4 definitions

Add preliminary UV4 defines. Signed-off-by: Mike Travis Tested-by: John Estabrook Tested-by: Gary Kroening --- arch/x86/include/asm/uv/uv_hub.h | 64 +++--- arch/x86/include/asm/uv/uv_mmrs.h | 22

[PATCH 02/21] X86_64, UV: Add UV Architecture Defines

Add defines to control which UV architectures are supported, and modify the 'if (is_uvX_*)' functions to return constant 0 for those not supported. This will help optimize code paths when support for specific UV arches is removed. Signed-off-by: Mike Travis Reviewed-by: Dimitri

[PATCH 07/21] X86_64, UV: Remove Support for UV1

The UV1 architecture is no longer being supported in future Linux kernels, so remove UV1 specific code. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Tested-by: John Estabrook Tested-by: Gary Kroening ---

[PATCH 15/21] X86_64, UV: Add UV4 addressing discovery function

UV4 requires early system wide addressing values. This involves the use of the CPUID instruction to obtain these values. The current function (detect_extended_topology()) in the kernel has been copied and streamlined, with the limitation that only CPU's used by UV architectures are supported.

[PATCH 14/21] X86_64, UV: Fold blade info into per node hub info structs

Migrate references from the blade info structs to the per node hub info structs. This phases out the allocation of the list of per blade info structs on node 0, in favor of a per node hub info struct allocated on the node's local memory. There are also some minor cosemetic changes in the

[PATCH 01/21] X86_64, UV: Add Initial UV4 definitions

Add preliminary UV4 defines. Signed-off-by: Mike Travis Tested-by: John Estabrook Tested-by: Gary Kroening --- arch/x86/include/asm/uv/uv_hub.h | 64 +++--- arch/x86/include/asm/uv/uv_mmrs.h | 22 + 2 files changed, 62 insertions(+), 24

[PATCH 02/21] X86_64, UV: Add UV Architecture Defines

Add defines to control which UV architectures are supported, and modify the 'if (is_uvX_*)' functions to return constant 0 for those not supported. This will help optimize code paths when support for specific UV arches is removed. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich

[PATCH 07/21] X86_64, UV: Remove Support for UV1

The UV1 architecture is no longer being supported in future Linux kernels, so remove UV1 specific code. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Tested-by: John Estabrook Tested-by: Gary Kroening --- arch/x86/include/asm/uv/uv_hub.h |9 --

[PATCH 15/21] X86_64, UV: Add UV4 addressing discovery function

UV4 requires early system wide addressing values. This involves the use of the CPUID instruction to obtain these values. The current function (detect_extended_topology()) in the kernel has been copied and streamlined, with the limitation that only CPU's used by UV architectures are supported.

[PATCH 14/21] X86_64, UV: Fold blade info into per node hub info structs

Migrate references from the blade info structs to the per node hub info structs. This phases out the allocation of the list of per blade info structs on node 0, in favor of a per node hub info struct allocated on the node's local memory. There are also some minor cosemetic changes in the

[PATCH 04/21] X86_64, UV: Add UV MMR Illegal Access Function

This new function is generated by the UV MMR generation script to identify MMR registers and fields that are not defined for a specific UV architecture. With this switch, the immediate panic can be replaced with a message and a bad return value allowing either hardware or the emulator to diagnose

[PATCH 20/21] X86_64, UV: Remove Obsolete GRU MMR address translation

From: Dimitri Sivanich Use no-op messages in place of cross-partition interrupts when nacking a put message in the GRU. This allows us to remove MMR's as a destination from the GRU driver. Signed-off-by: Dimitri Sivanich Signed-off-by: Mike Travis

[PATCH 00/21] X86_64, UV: Update kernel for SGI UV4 support

This patch set primarily updates the Linux kernel to support the next generation SGI Ultraviolet system, UV4. This architecture change is a larger incremental change than previous UV updates because of a major change to the addressing scheme. Previous UV architectures used a fixed address width

[PATCH 04/21] X86_64, UV: Add UV MMR Illegal Access Function

This new function is generated by the UV MMR generation script to identify MMR registers and fields that are not defined for a specific UV architecture. With this switch, the immediate panic can be replaced with a message and a bad return value allowing either hardware or the emulator to diagnose

[PATCH 20/21] X86_64, UV: Remove Obsolete GRU MMR address translation

From: Dimitri Sivanich Use no-op messages in place of cross-partition interrupts when nacking a put message in the GRU. This allows us to remove MMR's as a destination from the GRU driver. Signed-off-by: Dimitri Sivanich Signed-off-by: Mike Travis Tested-by: John Estabrook Tested-by: Gary

[PATCH 00/21] X86_64, UV: Update kernel for SGI UV4 support

This patch set primarily updates the Linux kernel to support the next generation SGI Ultraviolet system, UV4. This architecture change is a larger incremental change than previous UV updates because of a major change to the addressing scheme. Previous UV architectures used a fixed address width

[PATCH v3 2/3] fs: direct-io: call .bi_end_io via bio_endio()

bio_endio() is the graceful way to complete one bio. Signed-off-by: Ming Lei --- fs/direct-io.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/fs/direct-io.c b/fs/direct-io.c index a8dd60a..0a35e51 100644 --- a/fs/direct-io.c +++

Re: [PATCH 0/5] mpt3sas: driver update for Phase12

> "Chaitra" == Chaitra P B writes: > Here is the change list: > * Updated MPI version and MPI header files. > * Handle active cable exception event for Intruder/Cutlass HBAs. > * Use scsi_prot_ref_tag()API to fill reference tag field in the CDB. > * Set maximum

[PATCH v3 2/3] fs: direct-io: call .bi_end_io via bio_endio()

bio_endio() is the graceful way to complete one bio. Signed-off-by: Ming Lei --- fs/direct-io.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/fs/direct-io.c b/fs/direct-io.c index a8dd60a..0a35e51 100644 --- a/fs/direct-io.c +++ b/fs/direct-io.c @@ -350,15 +350,10 @@

Re: [PATCH 0/5] mpt3sas: driver update for Phase12

> "Chaitra" == Chaitra P B writes: > Here is the change list: > * Updated MPI version and MPI header files. > * Handle active cable exception event for Intruder/Cutlass HBAs. > * Use scsi_prot_ref_tag()API to fill reference tag field in the CDB. > * Set maximum transfer length per IO on RAID

[PATCH v3 3/3] block: avoid to call .bi_end_io() recursively

There were reports about heavy stack use by recursive calling .bi_end_io()([1][2][3]). For example, more than 16K stack is consumed in a single bio complete path[3], and in [2] stack overflow can be triggered if 20 nested dm-crypt is used. Also patches[1] [2] [3] were posted for addressing the

[PATCH net v3 0/5] drivers: net: cpsw: phy-handle fixes

From: David Rivshin This series fixes a number of related issues around using phy-handle properties in cpsw emac nodes. Patch 1 fixes a bug if more than one slave is used, and either slave uses the phy-handle property in the devicetree. Patch 2 fixes a NULL pointer

[PATCH v3 3/3] block: avoid to call .bi_end_io() recursively

There were reports about heavy stack use by recursive calling .bi_end_io()([1][2][3]). For example, more than 16K stack is consumed in a single bio complete path[3], and in [2] stack overflow can be triggered if 20 nested dm-crypt is used. Also patches[1] [2] [3] were posted for addressing the

[PATCH net v3 0/5] drivers: net: cpsw: phy-handle fixes

From: David Rivshin This series fixes a number of related issues around using phy-handle properties in cpsw emac nodes. Patch 1 fixes a bug if more than one slave is used, and either slave uses the phy-handle property in the devicetree. Patch 2 fixes a NULL pointer dereference which can occur

Re: [PATCH v2] lib/mpi: Fix kernel unaligned access in mpi_write_to_sgl

On (04/28/16 09:01), Herbert Xu wrote: > Subject: Re: [PATCH v2] lib/mpi: Fix kernel unaligned access in > mpi_write_to_sgl > > Please cc linux-crypto. Just bounced the message to linux-crypto as well. I think get_maintainers.pl might also need to be updated to generate this automatically.

[PATCH v3 0/3] block: avoid to call .bi_end_io() recursively

Hi, The 1st patch handles bio error in dio_end_io() which is only used by btrfs. The 2nd patch uses bio_endio() to call .bi_end_io() in dio_end_io(). The 3rd patch avoids to call .bi_end_io recursively in complete path. xfstests(-g auto) is run over ext4, xfs and btrfs with this patchset and

[PATCH v3 1/3] fs: direct-io: handle error in dio_end_io()

If error is passed to dio_end_io(), it should have been dealt with. Unfortunately current code just ignores that silently. Only btrfs uses dio_end_io(). Signed-off-by: Ming Lei --- fs/direct-io.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/direct-io.c

Re: [PATCH v2] lib/mpi: Fix kernel unaligned access in mpi_write_to_sgl

On (04/28/16 09:01), Herbert Xu wrote: > Subject: Re: [PATCH v2] lib/mpi: Fix kernel unaligned access in > mpi_write_to_sgl > > Please cc linux-crypto. Just bounced the message to linux-crypto as well. I think get_maintainers.pl might also need to be updated to generate this automatically.

[PATCH v3 0/3] block: avoid to call .bi_end_io() recursively

Hi, The 1st patch handles bio error in dio_end_io() which is only used by btrfs. The 2nd patch uses bio_endio() to call .bi_end_io() in dio_end_io(). The 3rd patch avoids to call .bi_end_io recursively in complete path. xfstests(-g auto) is run over ext4, xfs and btrfs with this patchset and

[PATCH v3 1/3] fs: direct-io: handle error in dio_end_io()

If error is passed to dio_end_io(), it should have been dealt with. Unfortunately current code just ignores that silently. Only btrfs uses dio_end_io(). Signed-off-by: Ming Lei --- fs/direct-io.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/direct-io.c b/fs/direct-io.c index

[PATCH 10/21] X86_64, UV: Create per cpu info structs to replace per hub info structs

The major portion of the hub info is common to all cpus on that hub. This is step one of moving the per cpu hub info to a per node hub info struct. This patch creates the small per cpu info struct that will contain only information specific to each CPU. Signed-off-by: Mike Travis

[PATCH 13/21] X86_64, UV: Allocate common per node hub info structs on local node

Allocate and setup per node hub info structs. CPU 0/Node 0 hub info is statically allocated to be accessible early in system startup. The remaining hub info structs are allocated on the node's local memory, and shared among the CPU's on that node. This leaves the small amount of info unique to

[PATCH 10/21] X86_64, UV: Create per cpu info structs to replace per hub info structs

The major portion of the hub info is common to all cpus on that hub. This is step one of moving the per cpu hub info to a per node hub info struct. This patch creates the small per cpu info struct that will contain only information specific to each CPU. Signed-off-by: Mike Travis Reviewed-by:

[PATCH 13/21] X86_64, UV: Allocate common per node hub info structs on local node

Allocate and setup per node hub info structs. CPU 0/Node 0 hub info is statically allocated to be accessible early in system startup. The remaining hub info structs are allocated on the node's local memory, and shared among the CPU's on that node. This leaves the small amount of info unique to

[PATCH 12/21] X86_64, UV: Move blade local processor ID to the per cpu info struct

Move references to blade local processor ID to the new per cpu info structs. Create an access function that makes this move, and potential other moves opaque to callers of this function. Define a flag that indicates to callers in external GPL modules that this function replaces any local

[PATCH 21/21] X86_64, UV: Fix incorrect nodes and pnodes for cpuless and memoryless nodes

From: Dimitri Sivanich This patch fixes the problem of incorrect nodes and pnodes being returned when referring to nodes that either have no cpus (AKA "headless") or no memory. Signed-off-by: Dimitri Sivanich Signed-off-by: Mike Travis

[PATCH 18/21] X86_64, UV: Build GAM reference tables

An aspect of the UV4 system architecture changes involve changing the way sockets, nodes, and pnodes are translated between one another. Decode the information from the BIOS provided EFI system table to build the needed conversion tables. Signed-off-by: Mike Travis Reviewed-by:

[PATCH 12/21] X86_64, UV: Move blade local processor ID to the per cpu info struct

Move references to blade local processor ID to the new per cpu info structs. Create an access function that makes this move, and potential other moves opaque to callers of this function. Define a flag that indicates to callers in external GPL modules that this function replaces any local

[PATCH 21/21] X86_64, UV: Fix incorrect nodes and pnodes for cpuless and memoryless nodes

From: Dimitri Sivanich This patch fixes the problem of incorrect nodes and pnodes being returned when referring to nodes that either have no cpus (AKA "headless") or no memory. Signed-off-by: Dimitri Sivanich Signed-off-by: Mike Travis Tested-by: John Estabrook Tested-by: Gary Kroening ---

[PATCH 18/21] X86_64, UV: Build GAM reference tables

An aspect of the UV4 system architecture changes involve changing the way sockets, nodes, and pnodes are translated between one another. Decode the information from the BIOS provided EFI system table to build the needed conversion tables. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich

[PATCH 16/21] X86_64, UV: Add obtaining GAM Range Table from UV BIOS

UV4 uses a GAM (globally addressed memory) architecture that supports variable sized memory per node. This replaces the old "M" value (number of address bits per node) with a range table for conversions between addresses and physical node (pnode) id's. This table is obtained from UV BIOS via the

[PATCH 09/21] X86_64, UV: Update MMIOH setup function to work for both UV3 and UV4

Since UV3 and UV4 MMIOH regions are setup the same, we can use a common function to setup both. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Tested-by: John Estabrook Tested-by: Gary Kroening ---

[PATCH 03/21] X86_64, UV: Add UV4 Specific Defines

Add UV4 specific defines to determine if current system type is a UV4 system. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Tested-by: John Estabrook Tested-by: Gary Kroening --- arch/x86/kernel/apic/x2apic_uv_x.c

[PATCH 16/21] X86_64, UV: Add obtaining GAM Range Table from UV BIOS

UV4 uses a GAM (globally addressed memory) architecture that supports variable sized memory per node. This replaces the old "M" value (number of address bits per node) with a range table for conversions between addresses and physical node (pnode) id's. This table is obtained from UV BIOS via the

[PATCH 09/21] X86_64, UV: Update MMIOH setup function to work for both UV3 and UV4

Since UV3 and UV4 MMIOH regions are setup the same, we can use a common function to setup both. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Tested-by: John Estabrook Tested-by: Gary Kroening --- arch/x86/kernel/apic/x2apic_uv_x.c |3 ++- 1 file changed, 2 insertions(+), 1

[PATCH 03/21] X86_64, UV: Add UV4 Specific Defines

Add UV4 specific defines to determine if current system type is a UV4 system. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Tested-by: John Estabrook Tested-by: Gary Kroening --- arch/x86/kernel/apic/x2apic_uv_x.c | 12 +--- 1 file changed, 9 insertions(+), 3

[PATCH 08/21] X86_64, UV: Clean up redunduncies after merge of UV4 MMR definitions

Clean up any redundancies caused by new UV4 MMR definitions superseding any previously definitions local to functions. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Reviewed-by: Andrew Banman Tested-by: John Estabrook

[PATCH 08/21] X86_64, UV: Clean up redunduncies after merge of UV4 MMR definitions

Clean up any redundancies caused by new UV4 MMR definitions superseding any previously definitions local to functions. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Reviewed-by: Andrew Banman Tested-by: John Estabrook Tested-by: Gary Kroening --- arch/x86/include/asm/uv/uv_hub.h

[PATCH 19/21] X86_64, UV: Update physical address conversions for UV4

This patch builds support for the new conversions of physical addresses to and from sockets, pnodes and nodes in UV4. It is designed to be as efficient as possible as lookups are done inside an interrupt context in some cases. It will be further optimized when physical hardware is available to

[PATCH 17/21] X86_64, UV: Support UV4 socket address changes

With the UV4 system architecture addressing changes, BIOS now provides this information via an EFI system table. This is the initial decoding of that system table. It also collects the sizing information for later allocation of dynamic conversion tables. Signed-off-by: Mike Travis

[PATCH 11/21] X86_64, UV: Move scir info to the per cpu info struct

Change the references to the SCIR fields to the new per cpu info structs. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Tested-by: John Estabrook Tested-by: Gary Kroening --- arch/x86/include/asm/uv/uv_hub.h |

[PATCH 19/21] X86_64, UV: Update physical address conversions for UV4

This patch builds support for the new conversions of physical addresses to and from sockets, pnodes and nodes in UV4. It is designed to be as efficient as possible as lookups are done inside an interrupt context in some cases. It will be further optimized when physical hardware is available to

[PATCH 17/21] X86_64, UV: Support UV4 socket address changes

With the UV4 system architecture addressing changes, BIOS now provides this information via an EFI system table. This is the initial decoding of that system table. It also collects the sizing information for later allocation of dynamic conversion tables. Signed-off-by: Mike Travis Reviewed-by:

[PATCH 11/21] X86_64, UV: Move scir info to the per cpu info struct

Change the references to the SCIR fields to the new per cpu info structs. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Tested-by: John Estabrook Tested-by: Gary Kroening --- arch/x86/include/asm/uv/uv_hub.h | 17 ++--- arch/x86/kernel/apic/x2apic_uv_x.c | 18

[PATCH 05/21] X86_64, UV: Prep for UV4 MMR updates

Cleanup patch to rearrange code and modify some defines so the next patch, the new UV4 MMR definitions can be merged cleanly. * Clean up the M/N related address constants (M is # of address bits per blade, N is the # of blade selection bits per SSI/partition). * Fix the lookup of the alias

[PATCH 05/21] X86_64, UV: Prep for UV4 MMR updates

Cleanup patch to rearrange code and modify some defines so the next patch, the new UV4 MMR definitions can be merged cleanly. * Clean up the M/N related address constants (M is # of address bits per blade, N is the # of blade selection bits per SSI/partition). * Fix the lookup of the alias

Re: [PATCH v2] lib/mpi: Fix kernel unaligned access in mpi_write_to_sgl

On Wed, Apr 27, 2016 at 01:43:56PM -0400, Sowmini Varadhan wrote: > > Commit 2d4d1eea540b ("lib/mpi: Add mpi sgl helpers") added > mpi_write_to_sgl() which generates traps due to unaligned > access on some platforms like sparc. Fix this by using > the get_unaligned* and put_unaligned* functions.

Re: [PATCH v2] lib/mpi: Fix kernel unaligned access in mpi_write_to_sgl

On Wed, Apr 27, 2016 at 01:43:56PM -0400, Sowmini Varadhan wrote: > > Commit 2d4d1eea540b ("lib/mpi: Add mpi sgl helpers") added > mpi_write_to_sgl() which generates traps due to unaligned > access on some platforms like sparc. Fix this by using > the get_unaligned* and put_unaligned* functions.

Re: [PATCH 1/3] module: Invalidate signatures on force-loaded modules

Ben Hutchings writes: > On Tue, 2016-04-26 at 20:07 +0930, Rusty Russell wrote: >> Ben Hutchings writes: >> > - if (info->len > markerlen && >> > + /* >> > +  * Require flags == 0, as a module with version information >> > +  * removed is no longer

Re: [PATCH 1/3] module: Invalidate signatures on force-loaded modules

Ben Hutchings writes: > On Tue, 2016-04-26 at 20:07 +0930, Rusty Russell wrote: >> Ben Hutchings writes: >> > - if (info->len > markerlen && >> > + /* >> > +  * Require flags == 0, as a module with version information >> > +  * removed is no longer the module that was signed >> > +  */ >> >

Re: [PATCH 3.2 085/115] veth: don’t modify ip_summed; doing so treats packets with bad checksums as good.

On 04/27/2016 05:00 PM, Hannes Frederic Sowa wrote: Hi Ben, On Wed, Apr 27, 2016, at 20:07, Ben Hutchings wrote: On Wed, 2016-04-27 at 08:59 -0700, Ben Greear wrote: On 04/26/2016 04:02 PM, Ben Hutchings wrote: 3.2.80-rc1 review patch. If anyone has any objections, please let me know. I

Re: [PATCH 3.2 085/115] veth: don’t modify ip_summed; doing so treats packets with bad checksums as good.

On 04/27/2016 05:00 PM, Hannes Frederic Sowa wrote: Hi Ben, On Wed, Apr 27, 2016, at 20:07, Ben Hutchings wrote: On Wed, 2016-04-27 at 08:59 -0700, Ben Greear wrote: On 04/26/2016 04:02 PM, Ben Hutchings wrote: 3.2.80-rc1 review patch. If anyone has any objections, please let me know. I

Re: [PATCH 3.16 106/217] sd: disable discard_zeroes_data for UNMAP

> "Rafael" == Rafael David Tinoco writes: Rafael> It seems that changing discard method from UNMAP to WRITE Rafael> SAME(16) without using NDOB bit (as first described in Rafael> sbc3r35b.pdf) can cause performance problems on big discards Rafael> (since data-out

Re: [PATCH 3.16 106/217] sd: disable discard_zeroes_data for UNMAP

> "Rafael" == Rafael David Tinoco writes: Rafael> It seems that changing discard method from UNMAP to WRITE Rafael> SAME(16) without using NDOB bit (as first described in Rafael> sbc3r35b.pdf) can cause performance problems on big discards Rafael> (since data-out buffer will be checked for

[PATCH V5 6/6] slim: qcom: Add runtime-pm support using clock-pause feature

Slimbus HW mandates that clock-pause sequence has to be executed before disabling relevant interface and core clocks. Runtime-PM's autosuspend feature is used here to enter/exit low power mode for Qualcomm's Slimbus controller. Autosuspend feature enables driver to avoid changing power-modes too

[PATCH V5 6/6] slim: qcom: Add runtime-pm support using clock-pause feature

Slimbus HW mandates that clock-pause sequence has to be executed before disabling relevant interface and core clocks. Runtime-PM's autosuspend feature is used here to enter/exit low power mode for Qualcomm's Slimbus controller. Autosuspend feature enables driver to avoid changing power-modes too

Re: [PATCH 3.2 085/115] veth: don’t modify ip_summed; doing so treats packets with bad checksums as good.

Hi Ben, On Wed, Apr 27, 2016, at 20:07, Ben Hutchings wrote: > On Wed, 2016-04-27 at 08:59 -0700, Ben Greear wrote: > > On 04/26/2016 04:02 PM, Ben Hutchings wrote: > > > > > > 3.2.80-rc1 review patch.  If anyone has any objections, please let me > > > know. > > I would be careful about this.  

Re: [PATCH 3.2 085/115] veth: don’t modify ip_summed; doing so treats packets with bad checksums as good.

Hi Ben, On Wed, Apr 27, 2016, at 20:07, Ben Hutchings wrote: > On Wed, 2016-04-27 at 08:59 -0700, Ben Greear wrote: > > On 04/26/2016 04:02 PM, Ben Hutchings wrote: > > > > > > 3.2.80-rc1 review patch.  If anyone has any objections, please let me > > > know. > > I would be careful about this.  

[PATCH V5 3/6] slimbus: Add messaging APIs to slimbus framework

Slimbus devices use value-element, and information elements to control device parameters (e.g. value element is used to represent gain for codec, information element is used to represent interrupt status for codec when codec interrupt fires). Messaging APIs are used to set/get these value and

[PATCH V5 3/6] slimbus: Add messaging APIs to slimbus framework

Slimbus devices use value-element, and information elements to control device parameters (e.g. value element is used to represent gain for codec, information element is used to represent interrupt status for codec when codec interrupt fires). Messaging APIs are used to set/get these value and

[PATCH V5 2/6] of/slimbus: OF helper for SLIMbus

OF helper routine scans the SLIMbus DeviceTree, allocates resources, and creates slim_devices according to the hierarchy. Signed-off-by: Sagar Dharia --- Documentation/devicetree/bindings/slimbus/bus.txt | 55 ++ drivers/slimbus/slim-core.c

[PATCH V5 5/6] slimbus: Add support for 'clock-pause' feature

Per slimbus specification, a reconfiguration sequence known as 'clock pause' needs to be broadcast over the bus while entering low- power mode. Clock-pause is initiated by the controller driver. To exit clock-pause, controller typically wakes up the framer device. Since wakeup precedure is

[PATCH V5 1/6] SLIMbus: Device management on SLIMbus

SLIMbus (Serial Low Power Interchip Media Bus) is a specification developed by MIPI (Mobile Industry Processor Interface) alliance. SLIMbus is a 2-wire implementation, which is used to communicate with peripheral components like audio-codec. SLIMbus uses Time-Division-Multiplexing to accommodate

[PATCH V5 4/6] slim: qcom: Add Qualcomm Slimbus controller driver

This controller driver programs manager, interface, and framer devices for Qualcomm's slimbus HW block. Manager component currently implements logical address setting, and messaging interface. Interface device reports bus synchronization information, and framer device clocks the bus from the time

[PATCH V5 2/6] of/slimbus: OF helper for SLIMbus

OF helper routine scans the SLIMbus DeviceTree, allocates resources, and creates slim_devices according to the hierarchy. Signed-off-by: Sagar Dharia --- Documentation/devicetree/bindings/slimbus/bus.txt | 55 ++ drivers/slimbus/slim-core.c | 57

[PATCH V5 5/6] slimbus: Add support for 'clock-pause' feature

Per slimbus specification, a reconfiguration sequence known as 'clock pause' needs to be broadcast over the bus while entering low- power mode. Clock-pause is initiated by the controller driver. To exit clock-pause, controller typically wakes up the framer device. Since wakeup precedure is

[PATCH V5 1/6] SLIMbus: Device management on SLIMbus

SLIMbus (Serial Low Power Interchip Media Bus) is a specification developed by MIPI (Mobile Industry Processor Interface) alliance. SLIMbus is a 2-wire implementation, which is used to communicate with peripheral components like audio-codec. SLIMbus uses Time-Division-Multiplexing to accommodate

[PATCH V5 4/6] slim: qcom: Add Qualcomm Slimbus controller driver

This controller driver programs manager, interface, and framer devices for Qualcomm's slimbus HW block. Manager component currently implements logical address setting, and messaging interface. Interface device reports bus synchronization information, and framer device clocks the bus from the time

[PATCH V5 0/6] Introduce framework for SLIMbus device drivers

SLIMbus (Serial Low Power Interchip Media Bus) is a specification developed by MIPI (Mobile Industry Processor Interface) alliance. SLIMbus is a 2-wire implementation, which is used to communicate with peripheral components like audio-codec. SLIMbus uses Time-Division-Multiplexing to accommodate

[PATCH V5 0/6] Introduce framework for SLIMbus device drivers

SLIMbus (Serial Low Power Interchip Media Bus) is a specification developed by MIPI (Mobile Industry Processor Interface) alliance. SLIMbus is a 2-wire implementation, which is used to communicate with peripheral components like audio-codec. SLIMbus uses Time-Division-Multiplexing to accommodate

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