Re: [PATCH 1/2] mm: use is_migrate_highatomic() to simplify the code

On Fri 03-03-17 15:06:19, Andrew Morton wrote: > On Fri, 3 Mar 2017 14:18:08 +0100 Michal Hocko wrote: > > > On Fri 03-03-17 19:10:13, Xishi Qiu wrote: > > > Introduce two helpers, is_migrate_highatomic() and > > > is_migrate_highatomic_page(). > > > Simplify the code, no functional changes. > >

Re: [Patch v2 03/11] s5p-mfc: Use min scratch buffer size as provided by F/W

On 03.03.2017 10:07, Smitha T Murthy wrote: > After MFC v8.0, mfc f/w lets the driver know how much scratch buffer > size is required for decoder. If mfc f/w has the functionality, > E_MIN_SCRATCH_BUFFER_SIZE, driver can know how much scratch buffer size > is required for encoder too. > > Signed-of

[v2 PATCH 3/3] mmc: sdhci-cadence: Update PHY delay configuration

PHY settings can be different for different platforms and SoCs. Fixed PHY input delays was replaced with SoC specific compatible data. DTS properties are used for configuration new PHY DLL delays. Signed-off-by: Piotr Sroka --- Changes for v2: - dts part was removed from this patch - most delays

[PATCH v2 1/4] mmc: core: Add post_ios_power_on callback for power sequences

Currently, ->pre_power_on() callback is called at the beginning of the mmc_power_up() function before MMC_POWER_UP and MMC_POWER_ON sequences. The callback ->post_power_on() is called at the end of the mmc_power_up() function. Some SDIO Chipsets require to gate the clock after than the vqmmc supply

Re: [PATCHv3 33/33] mm, x86: introduce PR_SET_MAX_VADDR and PR_GET_MAX_VADDR

On Mon, Mar 06, 2017 at 05:00:28PM +0300, Dmitry Safonov wrote: > 2017-02-21 15:42 GMT+03:00 Kirill A. Shutemov : > > On Tue, Feb 21, 2017 at 02:54:20PM +0300, Dmitry Safonov wrote: > >> 2017-02-17 19:50 GMT+03:00 Andy Lutomirski : > >> > On Fri, Feb 17, 2017 at 6:13 AM, Kirill A. Shutemov > >> >

[PATCH v2 3/4] mmc: pwrseq_simple: Add an optional pre-power-on-delay

Some devices need a while between the enablement of its clk and the time where the reset line is asserted. When this time happens between the pre_power_on and the post_power_on callbacks, there is a need to do an msleep at the end of the pre_power_on callback. This commit adds an optional DT prope

[PATCH v2 2/4] mmc: pwrseq-simple: Add optional op. for post_ios_power_on callback

Some devices require to do their entire power sequence after that the power supply of the MMC has been powered on. This can be done by only implementing the optional post_ios_power_on() callback that rely on pre_power_on/post_power_on functions, other functions being NULL. Then we introduce a new D

[PATCH v2 0/4] mmc: pwrseq: post_ios power sequence

Some devices, like WiFi chipsets AP6335 require a specific power-up sequence ordering before being used. You must enable the vqmmc power supply and wait until it reaches its minimum voltage, gate the clock and wait at least two cycles and then assert the reset line. See DS 1/ Currently, there is

Re: [PATCH 01/10] x86: assembly, ENTRY for fn, GLOBAL for data

On 03/03/2017, 07:20 PM, h...@zytor.com wrote: > On March 1, 2017 2:27:54 AM PST, Ingo Molnar wrote: >> >> * Thomas Gleixner wrote: >> >>> On Wed, 1 Mar 2017, Ingo Molnar wrote: * Jiri Slaby wrote: > This is a start of series to unify use of ENTRY, ENDPROC, GLOBAL, >> END, >>>

[PATCH 3/3] dt-bindings: mtd: Add Octal SPI support to Cadence QSPI.

This patch updates Cadence QSPI Device Tree documentation to include information about new property used to indicate, whether or not Octal SPI transfers are supported by the device. Signed-off-by: Artur Jedrysek --- Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4 1 file chang

Re: [PATCH 1/3] futex: remove duplicated code

Hi Jiri, On Mon, Mar 6, 2017 at 9:46 AM, Jiri Slaby wrote: > futex: make the encoded_op decoding readable > > Decoding of encoded_op is a bit unreadable. It contains shifts to the > left and to the right by some constants. Make it clearly visible what > part of the bit mask is tak

[PATCH v4 3/7] perf/sdt: Allow recording of existing events

Add functionality to fetch matching events from uprobe_events. If no events are fourd from it, fetch matching events from probe-cache and add them in uprobe_events. If all events are already present in uprobe_events, reuse them. If few of them are present, add entries for missing events and record

[PATCHv4 19/33] x86: convert the rest of the code to support p4d_t

This patch converts x86 to use proper folding of new page table level with . That's a bit of kitchen sink, but I don't see how to split it further. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/paravirt.h | 33 +- arch/x86/include/asm/paravirt_types.h | 12 ++- arch/x86

[PATCHv4 02/33] asm-generic: introduce 5level-fixup.h

We are going to switch core MM to 5-level paging abstraction. This is preparation step which adds As with 4level-fixup.h, the new header allows quickly make all architectures compatible with 5-level paging in core MM. In long run we would like to switch architectures to properly folded p4d level

[PATCHv4 28/33] x86/mm: add support of additional page table level during early boot

This patch adds support for 5-level paging during early boot. It generalizes boot for 4- and 5-level paging on 64-bit systems with compile-time switch between them. Signed-off-by: Kirill A. Shutemov --- arch/x86/boot/compressed/head_64.S | 23 +-- arch/x86/include/asm/pgtable.h

Re: Build regressions/improvements in v4.11-rc1

On Mon, Mar 6, 2017 at 2:59 PM, Geert Uytterhoeven wrote: > Below is the list of build error/warning regressions/improvements in > v4.11-rc1[1] compared to v4.10[2]. > > Summarized: > - build errors: +19/-1 > [1] > http://kisskb.ellerman.id.au/kisskb/head/c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d92

[PATCHv4 22/33] x86/mm: define virtual memory map for 5-level paging

The first part of memory map (up to %esp fixup) simply scales existing map for 4-level paging by factor of 9 -- number of bits addressed by additional page table level. The rest of the map is uncahnged. Signed-off-by: Kirill A. Shutemov --- Documentation/x86/x86_64/mm.txt | 33 +

[PATCHv4 23/33] x86/paravirt: make paravirt code support 5-level paging

Add operations to allocate/release p4ds. TODO: cover XEN. Not-yet-Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/paravirt.h | 44 +++ arch/x86/include/asm/paravirt_types.h | 7 +- arch/x86/include/asm/pgalloc.h| 2 ++ arch/x86/kern

[PATCHv4 01/33] x86/cpufeature: Add 5-level paging detection

Look for 'la57' in /proc/cpuinfo to see if your machine supports 5-level paging. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/cpufeatures.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h

[PATCHv4 30/33] x86/mm: make kernel_physical_mapping_init() support 5-level paging

Properly populate addition pagetable level if CONFIG_X86_5LEVEL is enabled. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/init_64.c | 71 --- 1 file changed, 62 insertions(+), 9 deletions(-) diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/ini

[PATCHv4 05/33] asm-generic: introduce

Like with pgtable-nopud.h for 4-level paging, this new header is base for converting an architectures to properly folded p4d_t level. Signed-off-by: Kirill A. Shutemov --- include/asm-generic/pgtable-nop4d.h | 56 + include/asm-generic/pgtable-nopud.h | 43 +++

[PATCHv4 27/33] x86/espfix: support 5-level paging

We don't need extra virtual address space for ESPFIX, so it stays within one PUD page table for both 4- and 5-level paging. Signed-off-by: Kirill A. Shutemov --- arch/x86/kernel/espfix_64.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/espfix_64

[PATCHv4 21/33] x86/asm: remove __VIRTUAL_MASK_SHIFT==47 assert

We don't need it anymore. 17be0aec74fb ("x86/asm/entry/64: Implement better check for canonical addresses") made canonical address check generic wrt. address width. Signed-off-by: Kirill A. Shutemov --- arch/x86/entry/entry_64.S | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff

[PATCHv4 14/33] x86/kexec: support p4d_t

Handle additional page table level in kexec code. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/kexec.h | 1 + arch/x86/kernel/machine_kexec_32.c | 4 +++- arch/x86/kernel/machine_kexec_64.c | 14 -- 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a

[PATCHv4 20/33] x86: detect 5-level paging support

5-level paging support is required from hardware when compiled with CONFIG_X86_5LEVEL=y. We may implement runtime switch support later. Signed-off-by: Kirill A. Shutemov --- arch/x86/boot/cpucheck.c | 9 + arch/x86/boot/cpuflags.c | 12 ++-- arch/

[PATCHv4 18/33] x86/xen: convert __xen_pgd_walk() and xen_cleanmfnmap() to support p4d

Split these helpers few per-level functions and add p4d support. Signed-off-by: Xiong Zhang [kirill.shute...@linux.intel.com: split off into separate patch] Signed-off-by: Kirill A. Shutemov --- arch/x86/xen/mmu.c | 243 - arch/x86/xen/mmu.h |

[PATCHv4 00/33] 5-level paging

Here is v4 of 5-level paging patchset. Please review and consider applying. == Overview == x86-64 is currently limited to 256 TiB of virtual address space and 64 TiB of physical address space. We are already bumping into this limit: some vendors offers servers with 64 TiB of memory today. To ove

[PATCHv4 09/33] x86: trivial portion of 5-level paging conversion

This patch covers simple cases only. Signed-off-by: Kirill A. Shutemov --- arch/x86/kernel/tboot.c| 6 +- arch/x86/kernel/vm86_32.c | 6 +- arch/x86/mm/fault.c| 39 +-- arch/x86/mm/init_32.c | 22

[PATCHv4 08/33] x86: basic changes into headers for 5-level paging

This patch extends x86 headers to enable 5-level paging support. It's still based on . We will get to the point where we can have later. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/pgtable-2level_types.h | 1 + arch/x86/include/asm/pgtable-3level_types.h | 1 + arch/x86/includ

[PATCH] iommu/arm-smmu: Report smmu type in dmesg

The ARM SMMU detection especially depends from system firmware. For better diagnostic, log the detected type in dmesg. The smmu type's name is now stored in struct arm_smmu_type and ACPI code is modified to use that struct too. Rename ARM_SMMU_MATCH_DATA() macro to ARM_SMMU_TYPE() for better reada

Re: [Patch v2 02/11] s5p-mfc: Adding initial support for MFC v10.10

On 03.03.2017 10:07, Smitha T Murthy wrote: > Adding the support for MFC v10.10, with new register file and > necessary hw control, decoder, encoder and structural changes. > > Signed-off-by: Smitha T Murthy Reviewed-by: Andrzej Hajda Few nitpicks below. > CC: Rob Herring > CC: devicet...@vger

[PATCHv4 15/33] x86/efi: handle p4d in EFI pagetables

Allocate additional page table level and change efi_sync_low_kernel_mappings() to make syncing logic work with additional page table level. Signed-off-by: Kirill A. Shutemov Reviewed-by: Matt Fleming --- arch/x86/platform/efi/efi_64.c | 33 +++-- 1 file changed, 23 i

Re: [PATCH] mm: do not call mem_cgroup_free() from within mem_cgroup_alloc()

On Fri 03-03-17 18:53:56, Tahsin Erdogan wrote: > mem_cgroup_free() indirectly calls wb_domain_exit() which is not > prepared to deal with a struct wb_domain object that hasn't executed > wb_domain_init(). For instance, the following warning message is > printed by lockdep if alloc_percpu() fails i

[PATCHv4 12/33] x86/mm: add support of p4d_t in vmalloc_fault()

With 4-level paging copying happens on p4d level, as we have pgd_none() always false when p4d_t folded. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/fault.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c inde

[v2 PATCH 1/3] mmc: sdhci-cadence: Fix writing PHY delay

Add polling for ACK to be sure that data are written to PHY register. Signed-off-by: Piotr Sroka --- Changes for v2: - fix indent --- drivers/mmc/host/sdhci-cadence.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/ho

[PATCHv4 10/33] x86/gup: add 5-level paging support

It's simply extension for one more page table level. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/gup.c | 33 +++-- 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c index 99c7805a9693..eb407cf0f6d3 100644 --- a/

[PATCH v2 6/6] powerpc/perf: Add Power8 mem_access event to sysfs

Patch add "mem_access" event to sysfs. This as-is not a raw event supported by Power8 pmu. Instead, it is formed based on raw event encoding specificed in isa207-common.h. Primary PMU event used here is PM_MRK_INST_CMPL. This event tracks only the completed marked instructions. Random sampling mo

[PATCHv4 16/33] x86/mm/pat: handle additional page table

Straight-forward extension of existing code to support additional page table level. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/pageattr.c | 56 -- 1 file changed, 41 insertions(+), 15 deletions(-) diff --git a/arch/x86/mm/pageattr.c b/arch/

[RESEND PATCH v3 5/8] phy: phy-mt65xx-usb3: add support for new version phy

There are some variations from mt2701 to mt2712: 1. banks shared by multiple ports are put back into each port, such as SPLLC and U2FREQ; 2. add a new bank MISC for u2port, and CHIP for u3port; 3. bank's offset in each port are also rearranged; Signed-off-by: Chunfeng Yun --- drivers/phy/phy

[RESEND PATCH v3 3/8] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones

Currently usb3 port in fact includes two sub-ports, but it is not flexible for some cases, such as following one: usb3 port0 includes u2port0 and u3port0; usb2 port0 includes u2port1; If wants to support only HS, we can use u2port0 or u2port1, when select u2port0, u3port0 is not needed; If

Re: [PATCH V11 10/10] arm/arm64: KVM: add guest SEA support

Hello James, On 3/6/2017 3:28 AM, James Morse wrote: On 28/02/17 19:43, Baicar, Tyler wrote: On 2/24/2017 3:42 AM, James Morse wrote: On 21/02/17 21:22, Tyler Baicar wrote: Currently external aborts are unsupported by the guest abort handling. Add handling for SEAs so that the host kernel re

[RESEND PATCH v3 2/8] phy: phy-mt65xx-usb3: increase LFPS filter threshold

Increase LFPS filter threshold to avoid some fake remote wakeup signal which cause U3 link fail and link to U2 only at about 0.01% probability. Signed-off-by: Chunfeng Yun --- drivers/phy/phy-mt65xx-usb3.c |9 + 1 file changed, 9 insertions(+) diff --git a/drivers/phy/phy-mt65xx-usb

[RESEND PATCH v3 6/8] arm64: dts: mt8173: split usb SuperSpeed port into two ports

split the old SuperSpeed port node into a HighSpeed one and a new SuperSpeed one. Signed-off-by: Chunfeng Yun --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 19 +-- 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/a

[RESEND PATCH v3 1/8] phy: phy-mt65xx-usb3: improve RX detection stable time

The default value of RX detection stable time is 10us, and this margin is too big for some critical cases which cause U3 link fail and link to U2(probability is about 1%). So change it to 5us. Signed-off-by: Chunfeng Yun --- drivers/phy/phy-mt65xx-usb3.c | 18 ++ 1 file changed

[RESEND PATCH v3 7/8] arm64: dts: mt8173: move clock from phy node into port nodes

there is a reference clock for each port, HighSpeed port is 48M, and SuperSpeed port is 26M which usually comes from 26M oscillator directly, but some SoCs is not. it is flexible to move it into port node. Signed-off-by: Chunfeng Yun --- arch/arm64/boot/dts/mediatek/mt8173.dtsi |8 ++--

[PATCHv4 33/33] x86/mm: allow to have userspace mappigs above 47-bits

On x86, 5-level paging enables 56-bit userspace virtual address space. Not all user space is ready to handle wide addresses. It's known that at least some JIT compilers use higher bits in pointers to encode their information. It collides with valid pointers with 5-level paging and leads to crashes.

Re: [PATCH net] team: use ETH_MAX_MTU as max mtu

Mon, Mar 06, 2017 at 02:48:58PM CET, ja...@redhat.com wrote: >This restores the ability to set a team device's mtu to anything higher >than 1500. Similar to the reported issue with bonding, the team driver >calls ether_setup(), which sets an initial max_mtu of 1500, while the >underlying hardware c

Re: [PATCHv3 33/33] mm, x86: introduce PR_SET_MAX_VADDR and PR_GET_MAX_VADDR

2017-02-21 15:42 GMT+03:00 Kirill A. Shutemov : > On Tue, Feb 21, 2017 at 02:54:20PM +0300, Dmitry Safonov wrote: >> 2017-02-17 19:50 GMT+03:00 Andy Lutomirski : >> > On Fri, Feb 17, 2017 at 6:13 AM, Kirill A. Shutemov >> > wrote: >> >> This patch introduces two new prctl(2) handles to manage maxi

[PATCHv4 32/33] x86: enable 5-level paging support

Most of things are in place and we can enable support of 5-level paging. Enabling XEN with 5-level paging requires more work. The patch makes XEN dependent on !X86_5LEVEL. Signed-off-by: Kirill A. Shutemov --- arch/x86/Kconfig | 5 + arch/x86/xen/Kconfig | 1 + 2 files changed, 6 insert

Re: Question Regarding ERMS memcpy

On Mon, Mar 06, 2017 at 05:41:22AM -0800, h...@zytor.com wrote: > It isn't really that straightforward IMO. > > For UC memory transaction size really needs to be specified explicitly > at all times and should be part of the API, rather than implicit. > > For WC/WT/WB device memory, the ordinary mem

[PATCHv4 11/33] x86/ident_map: add 5-level paging support

Nothing special: just handle one more level. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/ident_map.c | 47 --- 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/arch/x86/mm/ident_map.c b/arch/x86/mm/ident_map.c index 4473cb4f8b90..2c

[PATCHv4 07/33] mm: introduce __p4d_alloc()

For full 5-level paging we need a helper to allocate p4d page table. Signed-off-by: Kirill A. Shutemov --- mm/memory.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/mm/memory.c b/mm/memory.c index 7f1c2163b3ce..235ba51b2fbf 100644 --- a/mm/memory.c +++ b/mm/memory.

[PATCHv4 13/33] x86/power: support p4d_t in hibernate code

set_up_temporary_text_mapping() and relocate_restore_code() require trivial adjustments to handle additional page table level. Signed-off-by: Kirill A. Shutemov --- arch/x86/power/hibernate_64.c | 49 ++- 1 file changed, 35 insertions(+), 14 deletions(-)

[PATCH net] team: use ETH_MAX_MTU as max mtu

This restores the ability to set a team device's mtu to anything higher than 1500. Similar to the reported issue with bonding, the team driver calls ether_setup(), which sets an initial max_mtu of 1500, while the underlying hardware can handle something much larger. Just set it to ETH_MAX_MTU to su

Build regressions/improvements in v4.11-rc1

Below is the list of build error/warning regressions/improvements in v4.11-rc1[1] compared to v4.10[2]. Summarized: - build errors: +19/-1 - build warnings: +1108/-835 Happy fixing! ;-) Thanks to the linux-next team for providing the build service. [1] http://kisskb.ellerman.id.au/kisskb/h

[PATCHv4 26/33] x86/kasan: extend to support 5-level paging

This patch bring support for non-folded additional page table level. Signed-off-by: Kirill A. Shutemov Cc: Dmitry Vyukov = 5 && i < PTRS_PER_P4D; i++) + kasan_zero_p4d[i] = __p4d(p4d_val); + kasan_map_early_shadow(early_level4_pgt); kasan_map_early_shadow(init_level4

[PATCHv4 03/33] asm-generic: introduce __ARCH_USE_5LEVEL_HACK

We are going to introduce to provide abstraction for properly (in opposite to 5level-fixup.h hack) folded p4d level. The new header will be included from pgtable-nopud.h. If an architecture uses , we cannot use 5level-fixup.h directly to quickly convert the architecture to 5-level paging as it wo

[PATCHv4 24/33] x86/mm: basic defines/helpers for CONFIG_X86_5LEVEL

Extends pagetable headers to support new paging mode. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/pgtable_64.h | 11 +++ arch/x86/include/asm/pgtable_64_types.h | 20 +++ arch/x86/include/asm/pgtable_types.h| 10 +- arch/x86/mm/pgtable.c

[PATCHv4 06/33] mm: convert generic code to 5-level paging

Convert all non-architecture-specific code to 5-level paging. It's mostly mechanical adding handling one more page table level in places where we deal with pud_t. Signed-off-by: Kirill A. Shutemov --- drivers/misc/sgi-gru/grufault.c | 9 +- fs/userfaultfd.c| 6 +- include/as

[PATCHv4 31/33] x86/mm: add support for 5-level paging for KASLR

With 5-level paging randomization happens on P4D level instead of PUD. Maximum amount of physical memory also bumped to 52-bits for 5-level paging. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/kaslr.c | 82 - 1 file changed, 63 insertions

[PATCHv4 25/33] x86/dump_pagetables: support 5-level paging

Simple extension to support one more page table level. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/dump_pagetables.c | 49 --- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/arch/x86/mm/dump_pagetables.c b/arch/x86/mm/dump_pagetables.

[PATCHv4 04/33] arch, mm: convert all architectures to use 5level-fixup.h

If an architecture uses 4level-fixup.h we don't need to do anything as it includes 5level-fixup.h. If an architecture uses pgtable-nop*d.h, define __ARCH_USE_5LEVEL_HACK before inclusion of the header. It makes asm-generic code to use 5level-fixup.h. If an architecture has 4-level paging or folds

[PATCHv4 29/33] x86/mm: add sync_global_pgds() for configuration with 5-level paging

This basically restores slightly modified version of original sync_global_pgds() which we had before foldedl p4d was introduced. The only modification is protection against 'address' overflow. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/init_64.c | 37 +

[PATCHv4 17/33] x86/kasan: prepare clear_pgds() to switch to

With folded p4d, pgd_clear() is nop. Change clear_pgds() to use p4d_clear() instead. Signed-off-by: Kirill A. Shutemov Cc: Dmitry Vyukov --- arch/x86/mm/kasan_init_64.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/mm/kasan_init_64.c b/arch/x86/mm/kasa

cfq-iosched: two questions about the hrtimer version of CFQ

Hi Jan and list, When testing the hrtimer version of CFQ, we found a performance degradation problem which seems to be caused by commit 0b31c10 ("cfq-iosched: Charge at least 1 jiffie instead of 1 ns"). The following is the test process: * filesystem and block device * XFS + /dev/sda mou

[RESEND PATCH v3 4/8] phy: phy-mt65xx-usb3: move clock from phy node into port nodes

the reference clock of HighSpeed port is 48M which comes from PLL; the reference clock of SuperSpeed port is 26M which usually comes from 26M oscillator directly, but some SoCs are not, add it for compatibility, and put them into port node for flexibility. Signed-off-by: Chunfeng Yun --- drivers

[RESEND PATCH v3 8/8] dt-bindings: phy-mt65xx-usb: add support for new version phy

add a new compatible string for "mt2712", and move reference clock into each port node; Signed-off-by: Chunfeng Yun Acked-by: Rob Herring --- .../devicetree/bindings/phy/phy-mt65xx-usb.txt | 93 +--- 1 file changed, 80 insertions(+), 13 deletions(-) diff --git a/Documenta

Re: [PATCH] HID: get rid of HID_QUIRK_NO_INIT_REPORTS

On Mar 06 2017 or thereabouts, Jiri Kosina wrote: > On Thu, 5 Jan 2017, Benjamin Tissoires wrote: > > > For case 1, the hiddev documentation provides an ioctl to do the > > init manually. A solution could be to retrieve the requested report > > when EVIOCGUSAGE is called, in the same way hidraw do

Re: [PATCH v2 6/9] kasan: improve slab object description

On Fri, Mar 3, 2017 at 3:39 PM, Andrey Ryabinin wrote: > > > On 03/03/2017 04:52 PM, Alexander Potapenko wrote: >> On Fri, Mar 3, 2017 at 2:31 PM, Andrey Ryabinin >> wrote: >>> On 03/02/2017 04:48 PM, Andrey Konovalov wrote: Changes slab object description from: Object at 8800

Re: Question Regarding ERMS memcpy

On March 6, 2017 5:33:28 AM PST, Borislav Petkov wrote: >On Mon, Mar 06, 2017 at 12:01:10AM -0700, Logan Gunthorpe wrote: >> Well honestly my issue was solved by fixing my kernel config. I have >no >> idea why I had optimize for size in there in the first place. > >I still think that we should add

Re: [PATCH v5 1/2] perf sdt: add scanning of sdt probles arguments

On Wed, 14 Dec 2016 01:07:31 +0100 Alexis Berlemont wrote: > During a "perf buildid-cache --add" command, the section > ".note.stapsdt" of the "added" binary is scanned in order to list the > available SDT markers available in a binary. The parts containing the > probes arguments were left unscan

[PATCH 7/7] jbd2: make the whole kjournald2 kthread NOFS safe

From: Michal Hocko kjournald2 is central to the transaction commit processing. As such any potential allocation from this kernel thread has to be GFP_NOFS. Make sure to mark the whole kernel thread GFP_NOFS by the memalloc_nofs_save. Suggested-by: Jan Kara Reviewed-by: Jan Kara Signed-off-by:

[PATCH 3/7] xfs: abstract PF_FSTRANS to PF_MEMALLOC_NOFS

From: Michal Hocko xfs has defined PF_FSTRANS to declare a scope GFP_NOFS semantic quite some time ago. We would like to make this concept more generic and use it for other filesystems as well. Let's start by giving the flag a more generic name PF_MEMALLOC_NOFS which is in line with an exiting PF

Re: [PATCH v2] arm64: kvm: Use has_vhe() instead of hyp_alternate_select()

Hi Marc, On 03/06/2017 02:34 AM, Marc Zyngier wrote: Hi Shanker, On Mon, Mar 06 2017 at 2:33:18 am GMT, Shanker Donthineni wrote: Now all the cpu_hwcaps features have their own static keys. We don't need a separate function hyp_alternate_select() to patch the vhe/nvhe code. We can achieve

[PATCH v4 7/7] perf/sdt: Remove stale warning

Perf was showing warning if user tries to record sdt event without creating a probepoint. Now we are allowing direct record on sdt events, remove this stale warning/hint. Signed-off-by: Ravi Bangoria --- tools/lib/api/fs/tracing_path.c | 17 - 1 file changed, 4 insertions(+), 13

[PATCH 6/7] jbd2: mark the transaction context with the scope GFP_NOFS context

From: Michal Hocko now that we have memalloc_nofs_{save,restore} api we can mark the whole transaction context as implicitly GFP_NOFS. All allocations will automatically inherit GFP_NOFS this way. This means that we do not have to mark any of those requests with GFP_NOFS and moreover all the ext4

[PATCH 1/7] lockdep: teach lockdep about memalloc_noio_save

From: Nikolay Borisov Commit 21caf2fc1931 ("mm: teach mm by current context info to not do I/O during memory allocation") added the memalloc_noio_(save|restore) functions to enable people to modify the MM behavior by disabling I/O during memory allocation. This was further extended in Fixes: 934f

[PATCH 2/7] lockdep: allow to disable reclaim lockup detection

From: Michal Hocko The current implementation of the reclaim lockup detection can lead to false positives and those even happen and usually lead to tweak the code to silence the lockdep by using GFP_NOFS even though the context can use __GFP_FS just fine. See http://lkml.kernel.org/r/201605120803

Re: [PATCH] x86, kasan: add KASAN checks to atomic operations

On Mon, Mar 06, 2017 at 01:58:51PM +0100, Peter Zijlstra wrote: > On Mon, Mar 06, 2017 at 01:50:47PM +0100, Dmitry Vyukov wrote: > > On Mon, Mar 6, 2017 at 1:42 PM, Dmitry Vyukov wrote: > > > KASAN uses compiler instrumentation to intercept all memory accesses. > > > But it does not see memory acc

Re: [PATCH v5 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC

Hi, On Monday 06 March 2017 05:12 PM, Alim Akhtar wrote: > Hi Kishon > > On 03/01/2017 10:07 AM, Kishon Vijay Abraham I wrote: >> Hi, >> >> On Tuesday 28 February 2017 01:51 PM, Alim Akhtar wrote: >>> Hi Kishon, >>> >>> On 02/28/2017 09:04 AM, Kishon Vijay Abraham I wrote: Hi, On M

Re: [RFC PATCH 10/12] staging: android: ion: Use CMA APIs directly

Hi Daniel, On Monday 06 Mar 2017 11:32:04 Daniel Vetter wrote: > On Fri, Mar 03, 2017 at 10:50:20AM -0800, Laura Abbott wrote: > > On 03/03/2017 08:41 AM, Laurent Pinchart wrote: > >> On Thursday 02 Mar 2017 13:44:42 Laura Abbott wrote: > >>> When CMA was first introduced, its primary use was for

[PATCH] LOCAL / input: touchscreen: fix semicolon.cocci warnings

Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci CC: Beomho Seo Signed-off-by: Julia Lawall Signed-off-by: Fengguang Wu --- I also received the following warning from kbuild, without any other information: drivers/input/touchscreen/fts_ts.c:750:1-6: WARNING:

Re: [PATCH] HID: usbhid: Use pr_ and remove unnecessary OOM messages

On Wed, 1 Mar 2017, Joe Perches wrote: > Use a more common logging style and remove the unnecessary > OOM messages as there is default dump_stack when OOM. > > Miscellanea: > > o Hoist an assignment in an if > o Realign arguments > o Realign a deeply indented if descendent above a printk > > Si

Re: [PATCH 0/5] perf/sdt: Argument support for x86 and powepc

On Mon, 6 Mar 2017 13:23:30 +0530 Ravi Bangoria wrote: > > > On Tuesday 07 February 2017 08:25 AM, Masami Hiramatsu wrote: > > On Thu, 2 Feb 2017 16:41:38 +0530 > > Ravi Bangoria wrote: > > > >> The v5 patchset for sdt marker argument support for x86 [1] has > >> couple of issues. For exampl

[PATCH 0/7 v5] scope GFP_NOFS api

Hi, I have posted the previous version here [1]. There are no real changes in the implementation since then. I've just added "lockdep: teach lockdep about memalloc_noio_save" from Nikolay which is a lockdep bugfix developed independently but "mm: introduce memalloc_nofs_{save,restore} API" depends

[PATCH] irqchip: crossbar: Fix incorrect type of register size

The 'size' variable is unsigned according to the dt-bindings. As this variable is used as integer in other places, create a new variable that allows to fix the following sparse issue (-Wtypesign): drivers/irqchip/irq-crossbar.c:279:52: warning: incorrect type in argument 3 (different signedness

Re: [PATCH] HID: i2c-hid: Fix error handling

On Sun, 19 Feb 2017, Christophe JAILLET wrote: > According to error handling in this function, it is likely that some > resources should be freed before returning. > Replace 'return ret', with 'goto err'. > > While at it, remove some spaces at the beginning of the lines to be more > consistent. >

Re: [PATCH v17 2/3] usb: USB Type-C connector class

Hi Mats, On Fri, Mar 03, 2017 at 08:27:08PM +0100, Mats Karrman wrote: > On 2017-03-03 13:59, Heikki Krogerus wrote: > > > On Fri, Mar 03, 2017 at 08:29:18AM +0100, Mats Karrman wrote: > > > > > How would something like that sound to you guys? > > Complicated... Need to marinate on that fo

[PATCH v2 2/8] irqchip/gic-v3-its: Initialize MSIs with subsys_initcalls

This allows us to use kernel core functionality (e.g. cma) for ITS initialization. MSIs must be up before the device_initcalls (pci and platform device probe) and after arch_initcalls (dma init), so subsys_initcall is fine. Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-v3-its-pci-msi

Re: perf: use-after-free in perf_release

On Mon, Mar 6, 2017 at 2:14 PM, Peter Zijlstra wrote: > On Mon, Mar 06, 2017 at 10:57:07AM +0100, Dmitry Vyukov wrote: > >> == >> BUG: KASAN: use-after-free in atomic_dec_and_test >> arch/x86/include/asm/atomic.h:123 [inline] at addr

Re: [RFC PATCH 00/12] Ion cleanup in preparation for moving out of staging

On Mon 06-03-17 11:40:41, Daniel Vetter wrote: > On Mon, Mar 06, 2017 at 08:42:59AM +0100, Michal Hocko wrote: > > On Fri 03-03-17 09:37:55, Laura Abbott wrote: > > > On 03/03/2017 05:29 AM, Michal Hocko wrote: > > > > On Thu 02-03-17 13:44:32, Laura Abbott wrote: > > > >> Hi, > > > >> > > > >> The

Re: Question Regarding ERMS memcpy

On Mon, Mar 06, 2017 at 12:01:10AM -0700, Logan Gunthorpe wrote: > Well honestly my issue was solved by fixing my kernel config. I have no > idea why I had optimize for size in there in the first place. I still think that we should address the iomem memcpy Linus mentioned. So how about this partia

Re: perf: use-after-free in perf_release

On Mon, Mar 06, 2017 at 10:57:07AM +0100, Dmitry Vyukov wrote: > == > BUG: KASAN: use-after-free in atomic_dec_and_test > arch/x86/include/asm/atomic.h:123 [inline] at addr 880079c30158 > BUG: KASAN: use-after-free in put_task_str

Re: [PATCH v17 2/3] usb: USB Type-C connector class

Hi Peter, On Mon, Mar 06, 2017 at 09:15:51AM +0800, Peter Chen wrote: > > > What interface you use when you receive this event to handle > > > dual-role switch? I am wonder if a common dual-role class is > > > needed, then we can have a common user utility. > > > > > > Eg, if "data_role" has chan

[PATCH v2] f2fs: combine nat_bits and free_nid_bitmap cache

Both nat_bits cache and free_nid_bitmap cache provide same functionality as a intermediate cache between free nid cache and disk, but with different granularity of indicating free nid range, and different persistence policy. nat_bits cache provides better persistence ability, and free_nid_bitmap pr

[PATCH 4/7] mm: introduce memalloc_nofs_{save,restore} API

From: Michal Hocko GFP_NOFS context is used for the following 5 reasons currently - to prevent from deadlocks when the lock held by the allocation context would be needed during the memory reclaim - to prevent from stack overflows during the reclaim because the

Re: [PATCH] pinctrl: samsung: fix segfault when using external interrupts on s3c24xx

Hi Krzysztof, > > This is a regression from commit 8b1bd11c1f8f529057369c5b3702d13fd24e2765. > > Checkpatch should complain here about commit format. > > > > > Tested on FriendlyARM mini2440. > > > > Please add: > Fixes: 8b1bd11c1f8f ("pinctrl: samsung: Add the support the multiple > IORES

[PATCH 5/7] xfs: use memalloc_nofs_{save,restore} instead of memalloc_noio*

From: Michal Hocko kmem_zalloc_large and _xfs_buf_map_pages use memalloc_noio_{save,restore} API to prevent from reclaim recursion into the fs because vmalloc can invoke unconditional GFP_KERNEL allocations and these functions might be called from the NOFS contexts. The memalloc_noio_save will en

Re: [PATCH v2 1/2] HID: reject input outside logical range only if null state is set

On Tue, 14 Feb 2017, Tomasz Kramkowski wrote: > From: Valtteri Heikkilä > > This patch fixes an issue in drivers/hid/hid-input.c where USB HID > control null state flag is not checked upon rejecting inputs outside > logical minimum-maximum range. The check should be made according to USB > HID s

Re: [PATCH 1/2] xfs: allow kmem_zalloc_greedy to fail

On Sat 04-03-17 09:54:44, Dave Chinner wrote: > On Thu, Mar 02, 2017 at 04:45:40PM +0100, Michal Hocko wrote: > > From: Michal Hocko > > > > Even though kmem_zalloc_greedy is documented it might fail the current > > code doesn't really implement this properly and loops on the smallest > > allowed

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