On Wed, 26 Apr 2017, Catalin Marinas wrote:
> On Wed, Apr 26, 2017 at 10:00:30AM -0700, Stefano Stabellini wrote:
> > On Wed, 26 Apr 2017, Catalin Marinas wrote:
> > > On Tue, Apr 25, 2017 at 10:22:00AM -0700, Stefano Stabellini wrote:
> > > > On Tue, 25 Apr 2017, Julien Grall wrote:
> > > > > On 2
On Wed, Apr 26, 2017 at 10:00:30AM -0700, Stefano Stabellini wrote:
> On Wed, 26 Apr 2017, Catalin Marinas wrote:
> > On Tue, Apr 25, 2017 at 10:22:00AM -0700, Stefano Stabellini wrote:
> > > On Tue, 25 Apr 2017, Julien Grall wrote:
> > > > On 24/04/17 20:16, Stefano Stabellini wrote:
> > > > > Giv
On Wed, Apr 26, 2017 at 03:50:57PM +0100, Mark Rutland wrote:
> Hi Ganapatrao,
>
> Thanks for tracking this down.
>
> On Wed, Apr 26, 2017 at 02:56:20PM +0530, Ganapatrao Kulkarni wrote:
> > In some cases, ncpus used for perf_evsel__alloc_fd and for
> > perf_evsel__close are not the same, this is
On Thu, Apr 20, 2017 at 9:58 AM, Anatolij Gustschin wrote:
Hi Anatolij,
> Add FPGA manager driver for loading Arria/Cyclone/Stratix
> FPGAs via CvP.
>
> Signed-off-by: Anatolij Gustschin
> ---
> Changes in v3:
>
> - removed V-series from description (since the driver works
> also with Arr
Hi Heloise,
[auto build test WARNING on linus/master]
[also build test WARNING on v4.11-rc8 next-20170426]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Heloise/drivers-block-mtip32xx-mtip32xx
Kirill Tkhai writes:
> On 26.04.2017 19:32, Eric W. Biederman wrote:
>> Kirill Tkhai writes:
>>
>>> On 26.04.2017 19:11, Kirill Tkhai wrote:
On 26.04.2017 18:53, Oleg Nesterov wrote:
> On 04/17, Kirill Tkhai wrote:
>>
>> +struct pidns_ioc_req {
>> +/* Set vector of last pid
On Wed, Apr 26, 2017 at 09:48:33AM -0400, Geoff Lansberry wrote:
> In prior commits the selected clock frequency does not propagate
> correctly to what is written the the TRF7970A_MODULATOR_SYS_CLK_CTRL
> register.
> Also fixes a bug that causes the device tree property check to always
> pass.
>
>
Hello!
Just to let you know, that I got following test report from Stephen (thanks a
lot!).
The patch won’t work due to full cyclic transfer doesn’t fit into mcbufsz (256
bytes long).
His application requested driver to do cyclic transfer with large number of
cycles.
pl330 microcode has restri
Linus Walleij writes:
> On Mon, Apr 24, 2017 at 9:45 PM, Eric Anholt wrote:
>
>> This is required for the panel to work on bcm911360, where CLCDCLK is
>> the fixed 200Mhz AXI41 clock. The rate set is still passed up to the
>> CLCDCLK, for platforms that have a settable rate on that one.
>>
>> S
On Tue, Apr 25, 2017 at 4:19 PM, Christian König
wrote:
> From: Christian König
>
> This allows device drivers to request resizing their BARs.
>
> The function only tries to reprogram the windows of the bridge directly above
> the requesting device and only the BAR of the same type (usually mem,
On Wed, 26 Apr 2017, Catalin Marinas wrote:
> On Tue, Apr 25, 2017 at 10:22:00AM -0700, Stefano Stabellini wrote:
> > On Tue, 25 Apr 2017, Julien Grall wrote:
> > > On 24/04/17 20:16, Stefano Stabellini wrote:
> > > > Given the outstanding regression we need to fix as soon as possible,
> > > > I'll
On 26/04/2017 13:47, Satoru Takeuchi wrote:
> OK, here it is.
It looks like the cause is that AMD has removed TBM instructions
compared to e.g. Piledriver, so libvirt resorts to a much older base
model (thanks to Dave Gilbert for sorting through the list of feature bits).
Can you please run thi
Linus Walleij writes:
> On Mon, Apr 24, 2017 at 9:45 PM, Eric Anholt wrote:
>> +static long pl111_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
>> +unsigned long *prate)
>> +{
>> + int div = pl111_clk_div_choose_div(hw, rate, prate, true);
>
From: Markus Elfring
Date: Wed, 26 Apr 2017 18:33:15 +0200
Multiplications for the size determination of memory allocations
indicated that array data structures should be processed.
Thus use the corresponding function "devm_kcalloc".
This issue was detected by using the Coccinelle software.
Sig
Le Tuesday 25 Apr 2017 à 11:12:19 (-0700), Tejun Heo a écrit :
> Hello,
>
> On Tue, Apr 25, 2017 at 10:35:53AM +0200, Vincent Guittot wrote:
> > not sure to catch your example:
> > a task TA with a load_avg = 1 is the only task in a task group GB so
> > the cfs_rq load_avg = 1 too and the group_en
On Tue, Apr 25, 2017 at 4:19 PM, Christian König
wrote:
> From: Christian König
>
> Just the defines and helper functions to read the possible sizes of a BAR and
> update it's size.
>
> See
> https://pcisig.com/sites/default/files/specification_documents/ECN_Resizable-BAR_24Apr2008.pdf
> and PCI
> -Original Message-
> From: Borislav Petkov [mailto:b...@alien8.de]
> Sent: Wednesday, April 26, 2017 9:56 AM
...
>
> Oh well, here's an updated version with those suggestions incorporated.
>
> Also, I've carved out the common functionality into a _log_error_bank() which
> is more compac
On 26.04.2017 19:32, Eric W. Biederman wrote:
> Kirill Tkhai writes:
>
>> On 26.04.2017 19:11, Kirill Tkhai wrote:
>>> On 26.04.2017 18:53, Oleg Nesterov wrote:
On 04/17, Kirill Tkhai wrote:
>
> +struct pidns_ioc_req {
> +/* Set vector of last pids in namespace hierarchy */
>
On Wed, April 26, 2017 at 7:26 AM, Linus Walleij wrote:
>On Mon, Apr 24, 2017 at 9:15 PM,
> wrote:
>
>> From: Kuppuswamy Sathyanarayanan
>>
>>
>> According to Whiskey Cove PMIC spec, bit 7 of GPIOIRQ0_REG belongs to
>> battery IO. So we should skip this bit when checking for GPIO IRQ
>> pending
Kirill Tkhai writes:
> On 26.04.2017 19:11, Kirill Tkhai wrote:
>> On 26.04.2017 18:53, Oleg Nesterov wrote:
>>> On 04/17, Kirill Tkhai wrote:
+struct pidns_ioc_req {
+/* Set vector of last pids in namespace hierarchy */
+#define PIDNS_REQ_SET_LAST_PID_VEC0x1
+ u
Hi,
On Fri, 21 Apr 2017 16:14:31 -0500
Li, Yi yi1...@linux.intel.com wrote:
> From the User guild
>https://www.altera.com/documentation/dsu1441819344145.html#dsu1442261652730,
>it says Configuration via Protocol (CvP) is a configuration scheme
>supported inArria^® V,Cyclone^® V,Stratix^® V, an
On Wed, Apr 26, 2017 at 12:26 AM, Greg KH wrote:
> On Sun, Apr 23, 2017 at 03:37:29PM +0530, Adheer Chandravanshi wrote:
>> Use tab instead of spaces for indentation, as reported by checkpatch.pl
>>
>> Signed-off-by: Adheer Chandravanshi
>> ---
>> drivers/staging/android/ion/ion_cma_heap.c | 6 +
On 26.04.2017 19:11, Kirill Tkhai wrote:
> On 26.04.2017 18:53, Oleg Nesterov wrote:
>> On 04/17, Kirill Tkhai wrote:
>>>
>>> +struct pidns_ioc_req {
>>> +/* Set vector of last pids in namespace hierarchy */
>>> +#define PIDNS_REQ_SET_LAST_PID_VEC 0x1
>>> + unsigned int req;
>>> + void __user *
Please have a look here:
git://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git sched/wip
I think that has them all.
I'm still thinking on how to best create a test to assert on the SGC
condition, but I don't seem to get much further than brute-force
matching all group masks. At leas
From: Hou Pengyang
We don't need to rewrite the page under cp_rwsem and dnode locks.
Signed-off-by: Hou Pengyang
Signed-off-by: Chao Yu
Signed-off-by: Jaegeuk Kim
---
fs/f2fs/data.c| 39 ---
fs/f2fs/f2fs.h| 2 +-
fs/f2fs/gc.c | 1 +
fs/f2fs/
IOMMU harms performance signficantly when we run very fast networking
workloads. It's 40GB networking doing XDP test. Software overhead is
almost unaware, but it's the IOTLB miss (based on our analysis) which
kills the performance. We observed the same performance issue even with
software passthrou
On Wed, Apr 26, 2017 at 05:03:44PM +0100, Suzuki K Poulose wrote:
> On 25/04/17 19:49, Radim Krčmář wrote:
> >2017-04-24 11:10+0100, Suzuki K Poulose:
> >>The KVM uses mmu_notifier (wherever available) to keep track
> >>of the changes to the mm of the guest. The guest shadow page
> >>tables are rel
Fixing sparse warnings incorrect type assignment.
Signed-off-by: Karim Eshapa
---
drivers/staging/wlan-ng/hfa384x_usb.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/wlan-ng/hfa384x_usb.c
b/drivers/staging/wlan-ng/hfa384x_usb.c
in
61941e(bad)
[ 18.292271] Internal error: Oops: 80d [#1] SMP ARM
[ 18.297080] Modules linked in:
[ 18.471175] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G O
4.11.0-rc8-next-20170426 #3
[ 18.479909] Hardware name: Marvell Armada 380/385 (Device Tree)
[ 18.485850] task: c0a07000 task.stack
On 24 April 2017 at 22:14, Tejun Heo wrote:
> 09a43ace1f98 ("sched/fair: Propagate load during synchronous
> attach/detach") added immediate load propagation from cfs_rq to its
> sched_entity then to the parent cfs_rq; however, what gets propagated
> doesn't seem to make sense.
>
> It repeats the
On 26.04.2017 18:53, Oleg Nesterov wrote:
> On 04/17, Kirill Tkhai wrote:
>>
>> +struct pidns_ioc_req {
>> +/* Set vector of last pids in namespace hierarchy */
>> +#define PIDNS_REQ_SET_LAST_PID_VEC 0x1
>> +unsigned int req;
>> +void __user *data;
>> +unsigned int data_size;
>> +c
On 4/26/2017 8:48 AM, Daniel Jurgens wrote:
> On 4/26/2017 10:38 AM, Casey Schaufler wrote:
>> On 4/26/2017 8:02 AM, Sebastien Buisson wrote:
>>> From: Daniel Jurgens
>>>
>>> Add a generic notification mechanism in the LSM. Interested consumers
>>> can register a callback with the LSM and security
The sama5d2 has a mode were it is possible to cut power to the SoC while
keeping the RAM in self refresh.
Resuming from that mode needs support in the firmware/bootloader.
Signed-off-by: Alexandre Belloni
---
arch/arm/mach-at91/Makefile | 4 ++
arch/arm/mach-at91/generic.h |
On 04/21/2017 10:03 AM, Waiman Long wrote:
> This patchset incorporates the following 2 patchsets from Tejun Heo:
>
> 1) cgroup v2 thread mode patchset (5 patches)
> https://lkml.org/lkml/2017/2/2/592
> 2) CPU Controller on Control Group v2 (2 patches)
> https://lkml.org/lkml/2016/8/5/368
While we can only select between "standby" and "mem" states for power
management, the atmel platforms can actually support more modes.
For both standby and mem, allow selecting which mode will be used using the
atmel.pm_modes kernel parameter.
By default, keep the current modes.
Signed-off-by: Al
If the backup sram allocation fails, ensure we can suspend by falling back
to the usual slow clock mode.
Signed-off-by: Alexandre Belloni
---
arch/arm/mach-at91/pm.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
On Wed, Apr 26, 2017 at 11:53:19AM -0400, Vivien Didelot wrote:
> Some chips don't have a VLAN Table Unit, most of them do have a 4K
> table, some others as the 88E6390 family has a 13th bit for the VID.
>
> Add a new max_vid member to the info structure, used to check the
> presence of a VTU as w
On 25/04/17 19:49, Radim Krčmář wrote:
2017-04-24 11:10+0100, Suzuki K Poulose:
The KVM uses mmu_notifier (wherever available) to keep track
of the changes to the mm of the guest. The guest shadow page
tables are released when the VM exits via mmu_notifier->ops.release().
There is a rare chance
Add helpers to access the VTU VID register in the global1_vtu.c file.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/chip.c| 57 +
drivers/net/dsa/mv88e6xxx/global1.h | 4 +++
drivers/net/dsa/mv88e6xxx/global1_vtu.c | 29 +
2017-04-26 17:48 GMT+02:00 Daniel Jurgens :
> This was part of a larger patch set that hasn't been accepted yet. SELinux
> support for Inifiniband. Subsequent patches in that patch set will use it as
> well.
I revived this patch following Stephen Smalley's suggestion to base
the policy checksu
The 6390 family of chips use only 2 of the 3 VTU Data registers to pack
the MemberTag and PortState VLAN data. This means that they must be
written or read before or after each VTU/STU operations.
Implement this variant to add support for VTU with such chips. These
chips have a 13th bit for the VI
On Wed, Apr 26, 2017 at 05:49:59PM +0200, Mike Galbraith wrote:
> On Wed, 2017-04-26 at 08:44 -0700, Paul E. McKenney wrote:
> > On Wed, Apr 26, 2017 at 05:26:20PM +0200, Mike Galbraith wrote:
> > > On Wed, 2017-04-26 at 07:31 -0700, Paul E. McKenney wrote:
> > >
> > > > And a sneak preview, semi-
Newer chips such as the 88E6390 have a VTU Page bit in the VTU VID
register to specify a 13th bit for the VID. This can be used to support
8K VLANs.
When dumping the whole VTU, all VID bits must be set to one, including
this VTU Page bit. Add support for VID greater than 4095.
Signed-off-by: Vivi
Make the code which fetches or initializes a new VTU entry more concise.
This allows us the get rid of the old underscore prefix naming.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/chip.c | 64
1 file changed, 25 insertions(+), 39 deletion
Even though every switch model has a different way to access the VTU
Data bits, the base implementation of the VTU GetNext operation remains
the same: wait, write the first VID to iterate from, start the
operation, and read the next VID.
Move this generic implementation into global_vtu.c and abstr
Now that the code writes both VTU and STU data when loading a VTU entry,
load the corresponding STU entry at the same time.
This allows us to get rid of the STU management in the
_mv88e6xxx_vtu_new helper and thus remove the separate implementations
of STU Load/Purge and STU GetNext, as well as th
Add helpers to access the VTU SID register in the global1_vtu.c file.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/chip.c| 21 -
drivers/net/dsa/mv88e6xxx/global1.h | 4
drivers/net/dsa/mv88e6xxx/global1_vtu.c | 25 +
3
Add helpers to access the VTU FID register in the global1_vtu.c file.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/chip.c| 7 ++-
drivers/net/dsa/mv88e6xxx/global1.h | 4
drivers/net/dsa/mv88e6xxx/global1_vtu.c | 25 +
3 files changed
Now that we have chip operations for VTU accesses, mark all helpers from
global1_vtu.c as static. Only the various implementations of the
GetNext, LoadPurge and Flush operations need to be exposed.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/global1.h | 24 -
Add a new vtu_loadpurge operation to the chip info structure to differ
the various implementations of the VTU accesses.
Now that the STU handling is abstracted behind VTU operations, kill the
obsolete MV88E6XXX_FLAG_STU flag.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/chip.c
Move the helper functions to access the Global 1 VTU Operation register
to a new global1_vtu.c file, and get rid of the old underscore prefix
naming convention. This file will be extended will all VTU/STU related
code.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/Makefile |
Extract the generic portion of code to issue an STU GetNext operation,
which will be used in other implementations.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/chip.c| 14 +-
drivers/net/dsa/mv88e6xxx/global1.h | 2 ++
drivers/net/dsa/mv88e6xxx/global1_vt
Add a new vtu_getnext operation to the chip info structure to differ the
various implementations of the VTU accesses.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/chip.c| 82 ++---
drivers/net/dsa/mv88e6xxx/global1.h | 4 ++
drivers/net/dsa
The code to access the VTU Data registers currently only supports the
88E6185 family and alike: 2-bit membership adjacent to 2-bit port state.
Even though the 88E6352 family introduced an indirect table to program
the VLAN Spanning Tree states, the usage of the VTU Data registers
remains the same
Now that the code reads both VTU and STU data on VTU GetNext operation,
fetch the STU entry data of a VTU entry at the same time.
The STU data bits are masked with the VTU data bits and they are now all
read at the same time a VTU GetNext operation is issued.
Signed-off-by: Vivien Didelot
---
d
This patch series adds support for the VLAN Table Unit (a.k.a. the VTU)
to the 88E6390 family of Marvell Ethernet switch chips. The plumbing for
the per VLAN Spanning Tree support is added as a side effect of the
necessary refactoring.
The patchset is split up so that no duplication of code is int
VLAN aware Marvell chips can program 802.1Q VLAN membership as well as
802.1s per VLAN Spanning Tree state using the same 3 VTU Data registers.
Some chips such as 88E6185 use different Data registers offsets for
ports state and membership, and program them in a single operation.
Other chips such
Some chips don't have a VLAN Table Unit, most of them do have a 4K
table, some others as the 88E6390 family has a 13th bit for the VID.
Add a new max_vid member to the info structure, used to check the
presence of a VTU as well as the value used to iterate from in VTU
GetNext operations.
This mak
Move the VTU flush operation to global1_vtu.c and call it from a
mv88e6xxx_vtu_setup helper, similarly to the ATU and PVT setup.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/chip.c| 28
drivers/net/dsa/mv88e6xxx/global1.h | 1 +
drivers/ne
On Wed, Apr 26, 2017 at 05:09:42PM +0800, Jason Wang wrote:
>
>
> On 2017年04月25日 00:01, Michael S. Tsirkin wrote:
> > Applications that consume a batch of entries in one go
> > can benefit from ability to return some of them back
> > into the ring.
> >
> > Add an API for that - assuming there's
On 04/17, Kirill Tkhai wrote:
>
> +struct pidns_ioc_req {
> +/* Set vector of last pids in namespace hierarchy */
> +#define PIDNS_REQ_SET_LAST_PID_VEC 0x1
> + unsigned int req;
> + void __user *data;
> + unsigned int data_size;
> + char std_fields[0];
> +};
see below,
> +static
On Wed, Apr 26, 2017 at 12:35:08PM +0100, David Howells wrote:
> AT_EMPTY_PATH wasn't there back in 2010. I could eliminate the:
>
> statx(fd, NULL, 0, ...);
>
> option in favour of:
>
> statx(fd, "", AT_EMPTY_PATH, ...);
>
> Any thoughts either way, Al?
>
> It would seem that AT
The patch
ASoC: stm32: add SAI driver
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the ne
The patch
ASoC: stm32: add bindings for SAI
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
Hi Robert,
On Wed, Apr 26, 2017 at 04:38:13PM +0200, Robert Richter wrote:
> - pr_info("Adding device %s to group %d\n", dev_name(dev), group->id);
> + pr_info("Adding device %s to group %d, default domain type %d\n",
> + dev_name(dev), group->id,
> + group->default
On Wed, 2017-04-26 at 08:44 -0700, Paul E. McKenney wrote:
> On Wed, Apr 26, 2017 at 05:26:20PM +0200, Mike Galbraith wrote:
> > On Wed, 2017-04-26 at 07:31 -0700, Paul E. McKenney wrote:
> >
> > > And a sneak preview, semi-tested. If you get a chance to run this, please
> > > let me know now it
On Wed, Apr 26, 2017 at 07:39:21AM -0700, Guenter Roeck wrote:
> On Wed, Apr 26, 2017 at 10:31:56AM +0200, Greg Kroah-Hartman wrote:
> > On Tue, Apr 25, 2017 at 07:27:18PM -0700, Guenter Roeck wrote:
> > > On 04/25/2017 08:08 AM, Greg Kroah-Hartman wrote:
> > > > This is the start of the stable rev
On 4/26/2017 10:38 AM, Casey Schaufler wrote:
> On 4/26/2017 8:02 AM, Sebastien Buisson wrote:
>> From: Daniel Jurgens
>>
>> Add a generic notification mechanism in the LSM. Interested consumers
>> can register a callback with the LSM and security modules can produce
>> events.
> Why is this a gen
On Wed, Apr 26, 2017 at 07:51:32AM -0700, Adrian Salido wrote:
> > > The driver_override implementation is susceptible to race condition when
> > > different threads are reading vs storing a different driver override.
> > > Add locking to avoid race condition.
> > >
> > > Fixes: 3d713e0e382e ("driv
From: Joerg Roedel
The function is in no fast-path, there is no need for it to
be static inline in a header file. This also removes the
need to include iommu trace-points in iommu.h.
Signed-off-by: Joerg Roedel
---
drivers/iommu/iommu.c | 42 ++
include/
Hi,
here is a small patch-set to remove some header dependencies
from the IOMMU header files. The linux/iommu.h file does not
include linux/pci.h and the iommu trace-event headers
anymore.
For this the report_iommu_fault function was moved to
iommu.c and the place relying on above includes were f
From: Joerg Roedel
The include file does not need any PCI specifics, so remove
that include. Also fix the places that relied on it.
Signed-off-by: Joerg Roedel
---
arch/arm64/mm/dma-mapping.c| 1 +
drivers/iommu/fsl_pamu.h | 1 +
drivers/iommu/rockchip-iommu.c | 1 +
drivers/iommu/te
From: Joerg Roedel
It is not needed there anymore. All places needing it are
fixed.
Signed-off-by: Joerg Roedel
---
drivers/media/platform/mtk-vpu/mtk_vpu.c | 1 +
include/linux/iommu.h| 2 --
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/media/platf
From: Joerg Roedel
We make use of 'struct device' in iommu.h, so include
device.h to make it available explicitly.
Re-order the other headers while at it.
Signed-off-by: Joerg Roedel
---
include/linux/iommu.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/li
On Mon, Apr 24, 2017 at 3:24 PM, Lee Jones wrote:
> On Mon, 24 Apr 2017, Andy Shevchenko wrote:
>
>> On Mon, Apr 24, 2017 at 12:24 PM, Lee Jones wrote:
>> > On Sat, 22 Apr 2017, Andy Shevchenko wrote:
>> >
>> >> On Sat, Apr 22, 2017 at 1:34 AM, sathyanarayanan kuppuswamy
>> >> wrote:
>> >>
>> >>
On Wed, Apr 26, 2017 at 05:26:20PM +0200, Mike Galbraith wrote:
> On Wed, 2017-04-26 at 07:31 -0700, Paul E. McKenney wrote:
>
> > And a sneak preview, semi-tested. If you get a chance to run this, please
> > let me know now it goes.
>
> That took 'time stress-cpu-hotplug.sh' down to 48s, close
On Tue, 2017-04-25 at 16:10 +0200, Frederic Weisbecker wrote:
> irq_time_read() returns the irqtime minus the ksoftirqd time. This
> is necessary because irq_time_read() is used to substract the IRQ
> time
> from the sum_exec_runtime of a task. If we were to include the
> softirq
> time of ksoftirq
Hi,
On 26.04.2017 16:23, Pavel Machek wrote:
Hi!
I don't see why it would be hard to open files or have threads inside
a library. There are several libraries that do that already, specially
the ones designed to be used on multimidia apps.
Well, This is what the libv4l2 says:
This file im
From: Markus Elfring
Date: Wed, 26 Apr 2017 17:11:28 +0200
Add a missing character in this description for a function.
Signed-off-by: Markus Elfring
---
drivers/thermal/ti-soc-thermal/ti-bandgap.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/thermal/ti-soc-therma
On Mon, Apr 24, 2017 at 4:17 PM, Linus Walleij wrote:
> On Sat, Apr 15, 2017 at 1:25 AM,
> wrote:
>
>> From: Kuppuswamy Sathyanarayanan
>>
>> PMIC mfd driver only exports first level irq for GPIO device.
>> But currently we are reading the irqs from the second level irq
>> chip, So this patch fi
On 4/26/2017 8:02 AM, Sebastien Buisson wrote:
> From: Daniel Jurgens
>
> Add a generic notification mechanism in the LSM. Interested consumers
> can register a callback with the LSM and security modules can produce
> events.
Why is this a generic mechanism? Do you ever see anyone
other than SELi
From: Markus Elfring
Date: Wed, 26 Apr 2017 17:03:07 +0200
The script "checkpatch.pl" pointed information out like the following.
WARNING: Possible unnecessary 'out of memory' message
Thus remove such statements here.
Link:
http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Ref
From: Markus Elfring
Date: Wed, 26 Apr 2017 16:45:25 +0200
A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "devm_kcalloc".
This issue was detected by using the Coccinelle software.
On Wed, Apr 26, 2017 at 7:13 AM, Dan Williams wrote:
> On Tue, Apr 25, 2017 at 10:15 PM, Zheng, Lv wrote:
>> Hi,
>>
>>> From: Dan Williams [mailto:dan.j.willi...@intel.com]
>>> Subject: Re: [RFC PATCH] ACPICA: Tables: Fix regression introduced by a too
>>> early mechanism enabling
>>>
>>> On Tue
From: Markus Elfring
Date: Wed, 26 Apr 2017 17:24:56 +0200
Three update suggestions were taken into account
from static source code analysis.
Markus Elfring (3):
Use devm_kcalloc() in ti_bandgap_build()
Delete error messages for failed memory allocations in ti_bandgap_build()
Fix a typo in
On 26/04/17 17:47, Michal Hocko wrote:
> On Wed 26-04-17 16:35:49, Igor Stoppa wrote:
>> The bitmasks used for ___GFP_xxx can be defined in terms of an enum,
>> which doesn't require manual updates to its values.
>
> GFP masks are rarely updated so why is this worth doing?
I have plans for that
Add support of AXP803 regulators in the Pine64 device tree, in order to
enable many future functionalities, e.g. Wi-Fi.
Signed-off-by: Icenowy Zheng
---
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109 +
1 file changed, 109 insertions(+)
diff --git a/arch/arm64/boot
On Wed, 2017-04-26 at 07:31 -0700, Paul E. McKenney wrote:
> And a sneak preview, semi-tested. If you get a chance to run this, please
> let me know now it goes.
That took 'time stress-cpu-hotplug.sh' down to 48s, close to classic.
-Mike
Hi Jamie,
On 04/25, Jamie Iles wrote:
>
> Hi Oleg,
>
> I'm back looking at SIGNAL_UNKILLABLE and debugging child reapers again,
> and the current issue is when running code in the target process,
> SIGTRAP firing and that causing SIGNAL_UNKILLABLE protection to be
> removed in force_sig_info():
AXP803 PMIC also have a series of regulators (DCDCs and LDOs)
controllable via I2C/RSB bus.
Add support for them.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v4:
- Fixed somewhere which mention AXP806 before 803.
Changes in v2:
- Place AXP803 codes before AXP806/809 ones.
The Pine64 (including Pine64+) boards have an AXP803 PMIC, which is a PMIC
similar to AXP288, but tweaked to use with Allwinner SoCs rather than Intel
tablets (with DCIN and Vbus re-splitted like other AXP PMICs, and RSB bus
support added).
This patchset adds support for it and enabled it in Pine6
The Pine64 (including Pine64+) boards have an AXP803 as its main PMIC.
Add its device node.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
Allwinner A64 SoC features a R_INTC controller, which controls the NMI
line, and this interrupt line is usually connected to the AXP PMIC.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Changes it to use R_INTC binding and change node label to r_intc.
- Fixed MMIO region.
As axp20x-regulator now supports AXP803, add a cell for it.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v5:
- Removed wrong snippet.
Changes in v4:
- Added a trailing comma for new cell, for easier further cell addition.
Changes in v3:
- Make the new cell one-liner.
driv
The A31 NMI driver seems to be using wrong base address.
As we're going to convert to use a correct NMI base address (and
correctly name it to R_INTC as the datasheet suggests), add a new
compatible string for the "correct" R_INTC, which we will use for A64
SoC.
Signed-off-by: Icenowy Zheng
---
As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it,
like the old DTSI files for AXP20x/22x, for the common parts of the
PMIC.
Signed-off-by: Icenowy Zheng
Acked-by: Mark Brown
---
Changes in v5:
- Added Mark Brown's ACK.
Changes in v4:
- Re-sorted the nodes.
arch/arm64/boot
The Wi-Fi module of Pine64 is powered via DLDO4 and ELDO1 (the latter
one provides I/O voltage).
Add device node for it.
Although the Wi-Fi module is an external module which should be inserted
to a header, according to my personal talk with TL Lim, he does not want
this header to be used as GPIO
Allwinner A64 have a RSB controller like the one on A23/A33 SoCs.
Add it and its pinmux.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v2:
- Removed bonus properties in pio node.
- Added Chen-Yu's ACK.
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 19 +++
Add support for the newly imported compatible for the A64 R_INTC in
irq-sunxi-nmi driver.
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Fix A64 R_INTC compatible.
drivers/irqchip/irq-sunxi-nmi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/irqchip/irq-sunxi-nmi
Michael Kerrisk (man-pages) wrote:
> > This indicates what stx_attributes the VFS and filesystem actually support.
> >
> >>__s32 tv_nsec; /* Nanoseconds before or since tv_sec */
> >
> > If you're going to do Dmitry's suggestion, then this needs to be __u32 and
> > you
> > sh
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