[PATCH v2 1/4] net: macb: Add support for PTP timestamps in DMA descriptors

This patch adds support for PTP timestamps in DMA buffer descriptors. It checks capability at runtime and uses appropriate buffer descriptor. Signed-off-by: Rafal Ozieblo --- drivers/net/ethernet/cadence/Kconfig | 10 ++- drivers/net/ethernet/cadence/macb.c | 117

[PATCH v2 1/4] net: macb: Add support for PTP timestamps in DMA descriptors

This patch adds support for PTP timestamps in DMA buffer descriptors. It checks capability at runtime and uses appropriate buffer descriptor. Signed-off-by: Rafal Ozieblo --- drivers/net/ethernet/cadence/Kconfig | 10 ++- drivers/net/ethernet/cadence/macb.c | 117

[PATCH v2 01/11] pinctrl: dt-bindings: add documentation for AP806 pin controllers

Document the device tree binding for the pin controllers found on the Armada 7K and Armada 8K SoCs. Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 53

[PATCH v2 01/11] pinctrl: dt-bindings: add documentation for AP806 pin controllers

Document the device tree binding for the pin controllers found on the Armada 7K and Armada 8K SoCs. Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 53 ++--- 1

[PATCH v2 03/11] pinctrl: mvebu: remove the offset property for regmap

The offset property of the pinctrl node, when a regmap is used in the device tree, was never used nor documented in the binding. Moreover, the compatible string is enough to let the driver know which offset using. So this patch removes the property and move the information at the driver level.

[PATCH v2 03/11] pinctrl: mvebu: remove the offset property for regmap

The offset property of the pinctrl node, when a regmap is used in the device tree, was never used nor documented in the binding. Moreover, the compatible string is enough to let the driver know which offset using. So this patch removes the property and move the information at the driver level.

[PATCH v2 04/11] pinctrl: avoid PLAT_ORION dependency

From: Russell King Armada 8040 also needs orion pinctrl, and as these symbols are only selected, there's no need to make them depend on PLAT_ORION. Reviewed-by: Thomas Petazzoni Signed-off-by: Russell King

[PATCH v2 04/11] pinctrl: avoid PLAT_ORION dependency

From: Russell King Armada 8040 also needs orion pinctrl, and as these symbols are only selected, there's no need to make them depend on PLAT_ORION. Reviewed-by: Thomas Petazzoni Signed-off-by: Russell King Signed-off-by: Gregory CLEMENT --- drivers/pinctrl/mvebu/Kconfig | 4 1 file

[PATCH v2 05/11] arm64: marvell: enable the Armada 7K/8K pinctrl driver

This commit makes sure the drivers for the Armada 7K/8K pin controllers are enabled. Reviewed-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- arch/arm64/Kconfig.platforms | 2 ++ 1 file changed, 2 insertions(+)

[PATCH v2 05/11] arm64: marvell: enable the Armada 7K/8K pinctrl driver

This commit makes sure the drivers for the Armada 7K/8K pin controllers are enabled. Reviewed-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- arch/arm64/Kconfig.platforms | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms

[PATCH v2 08/11] arm64: dts: marvell: add pinctrl support for Armada 7K/8K

Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs. The CP master being different between Armada 7k and Armada 8k. This commit introduces the intermediates files armada-70x0.dtsi and armada-80x0.dtsi. These new files will provide different compatible strings depending of the SoC

[PATCH v2 08/11] arm64: dts: marvell: add pinctrl support for Armada 7K/8K

Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs. The CP master being different between Armada 7k and Armada 8k. This commit introduces the intermediates files armada-70x0.dtsi and armada-80x0.dtsi. These new files will provide different compatible strings depending of the SoC

[PATCH v2 07/11] pinctrl: mvebu: add driver for Armada CP110 pinctrl

From: Hanna Hawa This commit adds a pinctrl driver for the CP110 part of the Marvell Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all the MPP pins are available. On the other side, the Armada 8K has two CP110, and the available MPPs are split between

[PATCH v2 07/11] pinctrl: mvebu: add driver for Armada CP110 pinctrl

From: Hanna Hawa This commit adds a pinctrl driver for the CP110 part of the Marvell Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all the MPP pins are available. On the other side, the Armada 8K has two CP110, and the available MPPs are split between the master CP110

[PATCH v2 09/11] gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K

Document the device tree binding for the gpio controllers found on the Marvell Armada 7K and Armada 8K SoCs. Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 20

[PATCH v2 09/11] gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K

Document the device tree binding for the gpio controllers found on the Marvell Armada 7K and Armada 8K SoCs. Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 20

[PATCH v2 10/11] gpio: mvebu: Add support for the Armada 7K/8K SoCs

The Armada 7K and 8K SoCs use the same gpio controller as most of the other mvebu SoCs. However, the main difference is that the GPIO controller is part of a bigger system controller, and a syscon is used to control the overall system controller. Therefore, the driver needs to be adjusted to

[PATCH v2 10/11] gpio: mvebu: Add support for the Armada 7K/8K SoCs

The Armada 7K and 8K SoCs use the same gpio controller as most of the other mvebu SoCs. However, the main difference is that the GPIO controller is part of a bigger system controller, and a syscon is used to control the overall system controller. Therefore, the driver needs to be adjusted to

[PATCH v2 02/11] pinctrl: dt-bindings: add documentation for CP110 pin controllers

Document the device tree binding for the pin controllers found on the Armada 7K and Armada 8K SoCs. Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 101

[PATCH v2 02/11] pinctrl: dt-bindings: add documentation for CP110 pin controllers

Document the device tree binding for the pin controllers found on the Armada 7K and Armada 8K SoCs. Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 101

[PATCH v2 11/11] arm64: dts: marvell: add gpio support for Armada 7K/8K

Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs. The Armada 8K has two CP110 blocks, each having two GPIO controllers. However, in each CP110 block, one of the GPIO controller cannot be used: in the master CP110, only the second GPIO controller can be used, while on the slave

[PATCH v2 06/11] pinctrl: mvebu: add driver for Armada AP806 pinctrl

From: Hanna Hawa This commit adds a pinctrl driver for the pin-muxing controller found in the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register interface is compatible with the one used by previous mvebu pin controllers, so the common logic in

[PATCH v2 11/11] arm64: dts: marvell: add gpio support for Armada 7K/8K

Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs. The Armada 8K has two CP110 blocks, each having two GPIO controllers. However, in each CP110 block, one of the GPIO controller cannot be used: in the master CP110, only the second GPIO controller can be used, while on the slave

[PATCH v2 06/11] pinctrl: mvebu: add driver for Armada AP806 pinctrl

From: Hanna Hawa This commit adds a pinctrl driver for the pin-muxing controller found in the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register interface is compatible with the one used by previous mvebu pin controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c is

[PATCH v2 00/11] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K

Hi, As requested by Linus Walleij this series is a merge between the series "Add support for the pin controllers on the Marvell Armada 7K/8K" [1] and "Extend mvebu gpio driver to support the controllers of the Marvell Armada 7K/8K" [2]. The first part of the series is adding the support for the

[PATCH v2 00/11] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K

Hi, As requested by Linus Walleij this series is a merge between the series "Add support for the pin controllers on the Marvell Armada 7K/8K" [1] and "Extend mvebu gpio driver to support the controllers of the Marvell Armada 7K/8K" [2]. The first part of the series is adding the support for the

Re: sparc gcc 7.1 compile issue

From: John Paul Adrian Glaubitz Date: Fri, 2 Jun 2017 11:17:18 +0200 > On Wed, May 31, 2017 at 05:10:08PM -0400, David Miller wrote: >> A fix for this is in Linus's tree and was submitted to -stable last >> night: > > What remains to be fixed though is that the

Re: sparc gcc 7.1 compile issue

From: John Paul Adrian Glaubitz Date: Fri, 2 Jun 2017 11:17:18 +0200 > On Wed, May 31, 2017 at 05:10:08PM -0400, David Miller wrote: >> A fix for this is in Linus's tree and was submitted to -stable last >> night: > > What remains to be fixed though is that the gcc-7 testsuite > *reproducibly*

Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

From: Maxime Ripard Date: Fri, 2 Jun 2017 11:13:20 +0200 > On Fri, Jun 02, 2017 at 08:37:52AM +0200, Maxime Ripard wrote: >> On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote: >> > From: Corentin Labbe >> > Date: Wed, 31

Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

From: Maxime Ripard Date: Fri, 2 Jun 2017 11:13:20 +0200 > On Fri, Jun 02, 2017 at 08:37:52AM +0200, Maxime Ripard wrote: >> On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote: >> > From: Corentin Labbe >> > Date: Wed, 31 May 2017 09:18:31 +0200 >> > >> > > This patch series add the

Re: strange PAGE_ALLOC_COSTLY_ORDER usage in xgbe_map_rx_buffer

On 5/31/2017 11:04 AM, Michal Hocko wrote: Hi Tom, Hi Michal, I have stumbled over the following construct in xgbe_map_rx_buffer order = max_t(int, PAGE_ALLOC_COSTLY_ORDER - 1, 0); which looks quite suspicious. Why does it PAGE_ALLOC_COSTLY_ORDER - 1? And why do you depend on

Re: strange PAGE_ALLOC_COSTLY_ORDER usage in xgbe_map_rx_buffer

On 5/31/2017 11:04 AM, Michal Hocko wrote: Hi Tom, Hi Michal, I have stumbled over the following construct in xgbe_map_rx_buffer order = max_t(int, PAGE_ALLOC_COSTLY_ORDER - 1, 0); which looks quite suspicious. Why does it PAGE_ALLOC_COSTLY_ORDER - 1? And why do you depend on

Von Dr. Andrew Kitchen,

Von Dr. Andrew Kitchen,  Ich erwarte, dass mein Brief Sie bei guter Gesundheit und Ihrer schönsten Stimmung heute treffen wird. Mein Name ist Dr. Andrew Kitchen, UBS Investment Bank London, Financial Officer und Chief Operating Officer bei UBS Wealth Management UK, ich beschloss, eine

Von Dr. Andrew Kitchen,

Von Dr. Andrew Kitchen,  Ich erwarte, dass mein Brief Sie bei guter Gesundheit und Ihrer schönsten Stimmung heute treffen wird. Mein Name ist Dr. Andrew Kitchen, UBS Investment Bank London, Financial Officer und Chief Operating Officer bei UBS Wealth Management UK, ich beschloss, eine

Re: [PATCH 04/12] fs: ceph: CURRENT_TIME with ktime_get_real_ts()

On Fri, Jun 2, 2017 at 2:18 PM, Yan, Zheng wrote: > On Fri, Jun 2, 2017 at 7:33 PM, Arnd Bergmann wrote: >> On Fri, Jun 2, 2017 at 1:18 PM, Yan, Zheng wrote: >> What I meant is another related problem in ceph_mkdir() where the >> i_ctime

Re: [PATCH 04/12] fs: ceph: CURRENT_TIME with ktime_get_real_ts()

On Fri, Jun 2, 2017 at 2:18 PM, Yan, Zheng wrote: > On Fri, Jun 2, 2017 at 7:33 PM, Arnd Bergmann wrote: >> On Fri, Jun 2, 2017 at 1:18 PM, Yan, Zheng wrote: >> What I meant is another related problem in ceph_mkdir() where the >> i_ctime field of the parent inode is different between the

Re: [PATCH V17 02/11] ras: acpi/apei: cper: add support for generic data v3 structure

On Fri, May 19, 2017 at 02:32:04PM -0600, Tyler Baicar wrote: > The ACPI 6.1 spec adds a new revision of the generic error data > entry structure. Add support to handle the new structure as well > as properly verify and iterate through the generic data entries. > > Signed-off-by: Tyler Baicar

[PATCH][V2] net: phy: marvell: make some functions static

From: Colin Ian King functions m88e1510_get_temp_critical, m88e1510_set_temp_critical and m88e1510_get_temp_alarm can be made static as they not need to be in global scope. Cleans up sparse warnings: "symbol 'm88e1510_get_temp_alarm' was not declared. Should it be

Re: [PATCH V17 02/11] ras: acpi/apei: cper: add support for generic data v3 structure

On Fri, May 19, 2017 at 02:32:04PM -0600, Tyler Baicar wrote: > The ACPI 6.1 spec adds a new revision of the generic error data > entry structure. Add support to handle the new structure as well > as properly verify and iterate through the generic data entries. > > Signed-off-by: Tyler Baicar >

[PATCH][V2] net: phy: marvell: make some functions static

From: Colin Ian King functions m88e1510_get_temp_critical, m88e1510_set_temp_critical and m88e1510_get_temp_alarm can be made static as they not need to be in global scope. Cleans up sparse warnings: "symbol 'm88e1510_get_temp_alarm' was not declared. Should it be static?" "symbol

[PATCH v3 08/27] thunderbolt: Introduce thunderbolt bus and connection manager

Thunderbolt fabric consists of one or more switches. This fabric is called domain and it is controlled by an entity called connection manager. The connection manager can be either internal (driven by a firmware running on the host controller) or external (software driver). This driver currently

[PATCH v3 08/27] thunderbolt: Introduce thunderbolt bus and connection manager

Thunderbolt fabric consists of one or more switches. This fabric is called domain and it is controlled by an entity called connection manager. The connection manager can be either internal (driven by a firmware running on the host controller) or external (software driver). This driver currently

[PATCH v3 21/27] thunderbolt: Store Thunderbolt generation in the switch structure

In some cases it is useful to know what is the Thunderbolt generation the switch supports. This introduces a new field to struct switch that stores the generation of the switch based on the device ID. Unknown switches (there should be none) are assumed to be first generation to be on the safe

[PATCH v3 21/27] thunderbolt: Store Thunderbolt generation in the switch structure

In some cases it is useful to know what is the Thunderbolt generation the switch supports. This introduces a new field to struct switch that stores the generation of the switch based on the device ID. Unknown switches (there should be none) are assumed to be first generation to be on the safe

[PATCH v3 10/27] thunderbolt: Fail switch adding operation if reading DROM fails

All non-root switches are expected to have DROM so if the operation fails, it might be due the user unlugging the device. There is no point continuing adding the switch further in that case. Just bail out. For root switches (hosts) the DROM is either retrieved from a EFI variable, NVM or

[PATCH v3 14/27] thunderbolt: Move control channel messages to tb_msgs.h

We will be forwarding notifications received from the control channel to the connection manager implementations. This way they can decide what to do if anything when a notification is received. To be able to use control channel messages from other files, move them to tb_msgs.h. No functional

[PATCH v3 10/27] thunderbolt: Fail switch adding operation if reading DROM fails

All non-root switches are expected to have DROM so if the operation fails, it might be due the user unlugging the device. There is no point continuing adding the switch further in that case. Just bail out. For root switches (hosts) the DROM is either retrieved from a EFI variable, NVM or

[PATCH v3 14/27] thunderbolt: Move control channel messages to tb_msgs.h

We will be forwarding notifications received from the control channel to the connection manager implementations. This way they can decide what to do if anything when a notification is received. To be able to use control channel messages from other files, move them to tb_msgs.h. No functional

[PATCH v3 02/27] thunderbolt: No need to read UID of the root switch on resume

The root switch is part of the host controller and cannot be physically removed, so there is no point of reading UID again on resume in order to check if the root switch is still the same. Suggested-by: Andreas Noever Signed-off-by: Mika Westerberg

[PATCH v3 09/27] thunderbolt: Convert switch to a device

Thunderbolt domain consists of switches that are connected to each other, forming a bus. This will convert each switch into a real Linux device structure and adds them to the domain. The advantage here is that we get all the goodies from the driver core, like reference counting and sysfs hierarchy

[PATCH v3 02/27] thunderbolt: No need to read UID of the root switch on resume

The root switch is part of the host controller and cannot be physically removed, so there is no point of reading UID again on resume in order to check if the root switch is still the same. Suggested-by: Andreas Noever Signed-off-by: Mika Westerberg --- drivers/thunderbolt/switch.c | 29

[PATCH v3 09/27] thunderbolt: Convert switch to a device

Thunderbolt domain consists of switches that are connected to each other, forming a bus. This will convert each switch into a real Linux device structure and adds them to the domain. The advantage here is that we get all the goodies from the driver core, like reference counting and sysfs hierarchy

[PATCH v3 11/27] thunderbolt: Do not fail if DROM data CRC32 is invalid

There are devices out there where CRC32 of the DROM is not correct. One reason for this is that the ICM firmware does not validate it and it seems that neither does the Apple driver. To be able to support such devices we continue parsing the DROM contents regardless of whether CRC32 failed or not.

Re: [PATCH v3 00/19] Report power supply from hid-logitech-hidpp

On 06/02/2017 12:29 AM, Benjamin Tissoires wrote: > On Jun 01 2017 or thereabouts, Bastien Nocera wrote: >> On Thu, 2017-06-01 at 11:06 -0700, Dave Hansen wrote: >>> On 03/27/2017 07:59 AM, Benjamin Tissoires wrote: this is finally a rework of the series that provides kernel power_supply

Re: [PATCH] perf: fix perf test case 14 result reporting

Em Fri, Jun 02, 2017 at 11:09:36AM -0300, Arnaldo Carvalho de Melo escreveu: > Em Fri, Jun 02, 2017 at 11:58:46AM +0200, Thomas-Mich Richter escreveu: > > On 06/01/2017 11:04 PM, Jiri Olsa wrote: > > > On Thu, Jun 01, 2017 at 10:20:38AM -0300, Arnaldo Carvalho de Melo wrote: > > >> Em Thu, Jun 01,

[PATCH v3 11/27] thunderbolt: Do not fail if DROM data CRC32 is invalid

There are devices out there where CRC32 of the DROM is not correct. One reason for this is that the ICM firmware does not validate it and it seems that neither does the Apple driver. To be able to support such devices we continue parsing the DROM contents regardless of whether CRC32 failed or not.

Re: [PATCH v3 00/19] Report power supply from hid-logitech-hidpp

On 06/02/2017 12:29 AM, Benjamin Tissoires wrote: > On Jun 01 2017 or thereabouts, Bastien Nocera wrote: >> On Thu, 2017-06-01 at 11:06 -0700, Dave Hansen wrote: >>> On 03/27/2017 07:59 AM, Benjamin Tissoires wrote: this is finally a rework of the series that provides kernel power_supply

Re: [PATCH] perf: fix perf test case 14 result reporting

Em Fri, Jun 02, 2017 at 11:09:36AM -0300, Arnaldo Carvalho de Melo escreveu: > Em Fri, Jun 02, 2017 at 11:58:46AM +0200, Thomas-Mich Richter escreveu: > > On 06/01/2017 11:04 PM, Jiri Olsa wrote: > > > On Thu, Jun 01, 2017 at 10:20:38AM -0300, Arnaldo Carvalho de Melo wrote: > > >> Em Thu, Jun 01,

Re: [PATCH v3 0/4] make some special clk as critical_clocks

Am Dienstag, 2. Mai 2017, 15:34:02 CEST schrieb Elaine Zhang: > change in V3: > reword the commit message,explain why the specific clocks are need to be > critical. > > change in v2: > fix up some clks which have their own driver, not need to set as critical > clocks > > Elaine Zhang (4): >

Re: [PATCH v3 0/4] make some special clk as critical_clocks

Am Dienstag, 2. Mai 2017, 15:34:02 CEST schrieb Elaine Zhang: > change in V3: > reword the commit message,explain why the specific clocks are need to be > critical. > > change in v2: > fix up some clks which have their own driver, not need to set as critical > clocks > > Elaine Zhang (4): >

Re: [PATCH 08/10] KVM: arm/arm64: vgic: Handle unshared mapped interrupts

On 02/06/17 14:33, Christoffer Dall wrote: > On Wed, May 24, 2017 at 10:13:21PM +0200, Eric Auger wrote: >> Virtual interrupts directly mapped to physical interrupts require >> some special care. Their pending and active state must be observed >> at distributor level and not in the list register.

Re: [PATCH 08/10] KVM: arm/arm64: vgic: Handle unshared mapped interrupts

On 02/06/17 14:33, Christoffer Dall wrote: > On Wed, May 24, 2017 at 10:13:21PM +0200, Eric Auger wrote: >> Virtual interrupts directly mapped to physical interrupts require >> some special care. Their pending and active state must be observed >> at distributor level and not in the list register.

[PATCH v3 13/27] thunderbolt: Read vendor and device name from DROM

The device DROM contains name of the vendor and device among other things. Extract this information and expose it to the userspace via two new attributes. Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat Reviewed-by: Michael

Re: [PATCH] perf: fix perf test case 14 result reporting

Em Fri, Jun 02, 2017 at 11:58:46AM +0200, Thomas-Mich Richter escreveu: > On 06/01/2017 11:04 PM, Jiri Olsa wrote: > > On Thu, Jun 01, 2017 at 10:20:38AM -0300, Arnaldo Carvalho de Melo wrote: > >> Em Thu, Jun 01, 2017 at 02:34:41PM +0200, Thomas Richter escreveu: > >>> Command perf test -v 14

[PATCH v3 13/27] thunderbolt: Read vendor and device name from DROM

The device DROM contains name of the vendor and device among other things. Extract this information and expose it to the userspace via two new attributes. Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat Reviewed-by: Michael Jamet --- Documentation/ABI/testing/sysfs-bus-thunderbolt

Re: [PATCH] perf: fix perf test case 14 result reporting

Em Fri, Jun 02, 2017 at 11:58:46AM +0200, Thomas-Mich Richter escreveu: > On 06/01/2017 11:04 PM, Jiri Olsa wrote: > > On Thu, Jun 01, 2017 at 10:20:38AM -0300, Arnaldo Carvalho de Melo wrote: > >> Em Thu, Jun 01, 2017 at 02:34:41PM +0200, Thomas Richter escreveu: > >>> Command perf test -v 14

[PATCH v3 23/27] thunderbolt: Do not touch the hardware if the NHI is gone on resume

On PCs the NHI host controller is only present when there is a device connected. When the last device is disconnected the host controller will dissappear shortly (within 10s). Now if that happens when we are suspended we should not try to touch the hardware anymore, so add a flag for this and

[PATCH v3 23/27] thunderbolt: Do not touch the hardware if the NHI is gone on resume

On PCs the NHI host controller is only present when there is a device connected. When the last device is disconnected the host controller will dissappear shortly (within 10s). Now if that happens when we are suspended we should not try to touch the hardware anymore, so add a flag for this and

[PATCH v3 27/27] MAINTAINERS: Add maintainers for Thunderbolt driver

We will be helping Andreas to maintain the Thunderbolt driver. Signed-off-by: Michael Jamet Signed-off-by: Yehezkel Bernat Signed-off-by: Mika Westerberg Reviewed-by: Andy Shevchenko

[PATCH v3 03/27] thunderbolt: Do not try to read UID if DROM offset is read as 0

At least Falcon Ridge when in host mode does not have any kind of DROM available and reading DROM offset returns 0 for these. Do not try to read DROM any further in that case. Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat

[PATCH v3 27/27] MAINTAINERS: Add maintainers for Thunderbolt driver

We will be helping Andreas to maintain the Thunderbolt driver. Signed-off-by: Michael Jamet Signed-off-by: Yehezkel Bernat Signed-off-by: Mika Westerberg Reviewed-by: Andy Shevchenko --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index

[PATCH v3 03/27] thunderbolt: Do not try to read UID if DROM offset is read as 0

At least Falcon Ridge when in host mode does not have any kind of DROM available and reading DROM offset returns 0 for these. Do not try to read DROM any further in that case. Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat Reviewed-by: Michael Jamet Reviewed-by: Andy Shevchenko

[PATCH v3 26/27] thunderbolt: Add documentation how Thunderbolt bus can be used

Since there are no such tool yet that handles all the low-level details of connecting devices and upgrading their firmware, add a small document that shows how the Thunderbolt bus can be used directly from command line. Signed-off-by: Mika Westerberg Reviewed-by:

[PATCH v3 26/27] thunderbolt: Add documentation how Thunderbolt bus can be used

Since there are no such tool yet that handles all the low-level details of connecting devices and upgrading their firmware, add a small document that shows how the Thunderbolt bus can be used directly from command line. Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat Reviewed-by:

[PATCH v3 19/27] thunderbolt: Add new Thunderbolt PCI IDs

Add Intel Win Ridge (Thunderbolt 2) and Alpine Ridge (Thunderbolt 3) controller PCI IDs to the list of supported devices. This code is based on the work done by Amir Levy and Michael Jamet. Signed-off-by: Michael Jamet Signed-off-by: Mika Westerberg

[PATCH v3 19/27] thunderbolt: Add new Thunderbolt PCI IDs

Add Intel Win Ridge (Thunderbolt 2) and Alpine Ridge (Thunderbolt 3) controller PCI IDs to the list of supported devices. This code is based on the work done by Amir Levy and Michael Jamet. Signed-off-by: Michael Jamet Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat Reviewed-by:

[PATCH v3 12/27] thunderbolt: Refactor and fix parsing of port drom entries

From: Lukas Wunner Currently tb_drom_parse_entry() is only able to parse drom entries of type TB_DROM_ENTRY_PORT. Rename it to tb_drom_parse_entry_port(). Fold tb_drom_parse_port_entry() into it. Its return value is currently ignored. Evaluate it and abort parsing on error.

[PATCH v3 12/27] thunderbolt: Refactor and fix parsing of port drom entries

From: Lukas Wunner Currently tb_drom_parse_entry() is only able to parse drom entries of type TB_DROM_ENTRY_PORT. Rename it to tb_drom_parse_entry_port(). Fold tb_drom_parse_port_entry() into it. Its return value is currently ignored. Evaluate it and abort parsing on error. Change

[PATCH v3 22/27] thunderbolt: Add support for DMA configuration based mailbox

The DMA (NHI) port of a switch provides access to the NVM of the host controller (and devices starting from Intel Alpine Ridge). The NVM contains also more complete DROM for the root switch including vendor and device identification strings. This will look for the DMA port capability for each

Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

From: Maxime Ripard Date: Fri, 2 Jun 2017 08:37:52 +0200 > On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote: >> From: Corentin Labbe >> Date: Wed, 31 May 2017 09:18:31 +0200 >> >> > This patch series add the driver for

[PATCH v3 22/27] thunderbolt: Add support for DMA configuration based mailbox

The DMA (NHI) port of a switch provides access to the NVM of the host controller (and devices starting from Intel Alpine Ridge). The NVM contains also more complete DROM for the root switch including vendor and device identification strings. This will look for the DMA port capability for each

Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

From: Maxime Ripard Date: Fri, 2 Jun 2017 08:37:52 +0200 > On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote: >> From: Corentin Labbe >> Date: Wed, 31 May 2017 09:18:31 +0200 >> >> > This patch series add the driver for dwmac-sun8i which handle the Ethernet >> > MAC >> > present on

[PATCH v3 20/27] thunderbolt: Add support for NHI mailbox

The host controller includes two sets of registers that are used to communicate with the firmware. Add functions that can be used to access these registers. This code is based on the work done by Amir Levy and Michael Jamet. Signed-off-by: Michael Jamet Signed-off-by:

[PATCH v3 17/27] thunderbolt: Let the connection manager handle all notifications

Currently the control channel (ctl.c) handles the one supported notification (PLUG_EVENT) and sends back ACK accordingly. However, we are going to add support for the internal connection manager (ICM) that needs to handle a different notifications. So instead of dealing everything in the control

[PATCH v3 17/27] thunderbolt: Let the connection manager handle all notifications

Currently the control channel (ctl.c) handles the one supported notification (PLUG_EVENT) and sends back ACK accordingly. However, we are going to add support for the internal connection manager (ICM) that needs to handle a different notifications. So instead of dealing everything in the control

[PATCH v3 20/27] thunderbolt: Add support for NHI mailbox

The host controller includes two sets of registers that are used to communicate with the firmware. Add functions that can be used to access these registers. This code is based on the work done by Amir Levy and Michael Jamet. Signed-off-by: Michael Jamet Signed-off-by: Mika Westerberg

[PATCH v3 01/27] thunderbolt: Use const buffer pointer in write operations

These functions should not (and do not) modify the argument in any way so make it const. Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat Reviewed-by: Michael Jamet Reviewed-by: Greg Kroah-Hartman

[PATCH v3 25/27] thunderbolt: Add support for host and device NVM firmware upgrade

Starting from Intel Falcon Ridge the NVM firmware can be upgraded by using DMA configuration based mailbox commands. If we detect that the host or device (device support starts from Intel Alpine Ridge) has the DMA configuration based mailbox we expose NVM information to the userspace as two

[PATCH v3 01/27] thunderbolt: Use const buffer pointer in write operations

These functions should not (and do not) modify the argument in any way so make it const. Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat Reviewed-by: Michael Jamet Reviewed-by: Greg Kroah-Hartman Reviewed-by: Andy Shevchenko --- drivers/thunderbolt/ctl.c | 8

[PATCH v3 25/27] thunderbolt: Add support for host and device NVM firmware upgrade

Starting from Intel Falcon Ridge the NVM firmware can be upgraded by using DMA configuration based mailbox commands. If we detect that the host or device (device support starts from Intel Alpine Ridge) has the DMA configuration based mailbox we expose NVM information to the userspace as two

[PATCH v3 04/27] thunderbolt: Do not warn about newer DROM versions

DROM version 2 is compatible with the previous generation so no need to warn about that. Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat Reviewed-by: Michael Jamet Reviewed-by: Andy Shevchenko

[PATCH v3 06/27] thunderbolt: Rework capability handling

Organization of the capabilities in switches and ports is not so random after all. Rework the capability handling functionality so that it follows how capabilities are organized and provide two new functions (tb_switch_find_vsec_cap() and tb_port_find_cap()) which can be used to extract

[PATCH v3 04/27] thunderbolt: Do not warn about newer DROM versions

DROM version 2 is compatible with the previous generation so no need to warn about that. Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat Reviewed-by: Michael Jamet Reviewed-by: Andy Shevchenko --- drivers/thunderbolt/eeprom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH v3 06/27] thunderbolt: Rework capability handling

Organization of the capabilities in switches and ports is not so random after all. Rework the capability handling functionality so that it follows how capabilities are organized and provide two new functions (tb_switch_find_vsec_cap() and tb_port_find_cap()) which can be used to extract

[PATCH v3 24/27] thunderbolt: Add support for Internal Connection Manager (ICM)

Starting from Intel Falcon Ridge the internal connection manager running on the Thunderbolt host controller has been supporting 4 security levels. One reason for this is to prevent DMA attacks and only allow connecting devices the user trusts. The internal connection manager (ICM) is the

[PATCH v3 24/27] thunderbolt: Add support for Internal Connection Manager (ICM)

Starting from Intel Falcon Ridge the internal connection manager running on the Thunderbolt host controller has been supporting 4 security levels. One reason for this is to prevent DMA attacks and only allow connecting devices the user trusts. The internal connection manager (ICM) is the

[PATCH v3 07/27] thunderbolt: Allow passing NULL to tb_ctl_free()

Following the usual pattern used in many places, we allow passing NULL pointer to tb_ctl_free(). Then the user can call the function regardless if it has allocated control channel or not making the code bit simpler. Suggested-by: Andy Shevchenko Signed-off-by:

[PATCH v3 07/27] thunderbolt: Allow passing NULL to tb_ctl_free()

Following the usual pattern used in many places, we allow passing NULL pointer to tb_ctl_free(). Then the user can call the function regardless if it has allocated control channel or not making the code bit simpler. Suggested-by: Andy Shevchenko Signed-off-by: Mika Westerberg ---

[PATCH v3 15/27] thunderbolt: Expose get_route() to other files

We are going to use it when we change the connection manager to handle events itself. Also rename it to follow naming convention used in functions exposed in ctl.h. Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat

[PATCH v3 15/27] thunderbolt: Expose get_route() to other files

We are going to use it when we change the connection manager to handle events itself. Also rename it to follow naming convention used in functions exposed in ctl.h. Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat Reviewed-by: Michael Jamet Reviewed-by: Andy Shevchenko ---

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