It's not safe to use weak random data here, especially for the challenge
response randomness. Since we're always in process context, it's safe to
simply wait until we have enough randomness to carry out the
authentication correctly.
While we're at it, we clean up a small memleak during an error
It's not safe to use weak random data here, especially for the challenge
response randomness. Since we're always in process context, it's safe to
simply wait until we have enough randomness to carry out the
authentication correctly.
While we're at it, we clean up a small memleak during an error
This protocol uses lots of complex cryptography that relies on securely
generated random numbers. Thus, it's important that the RNG is actually
seeded before use. Fortuantely, it appears we're always operating in
process context (there are many GFP_KERNEL allocations and other
sleeping
This protocol uses lots of complex cryptography that relies on securely
generated random numbers. Thus, it's important that the RNG is actually
seeded before use. Fortuantely, it appears we're always operating in
process context (there are many GFP_KERNEL allocations and other
sleeping
Using get_random_int here is faster, more fitting of the use case, and
just as cryptographically secure. It also has the benefit of providing
better randomness at early boot, which is when many of these structures
are assigned.
Also, semantically, it's not really proper to have been assigning an
This is much faster and just as secure. It also has the added benefit of
probably returning better randomness at early-boot on systems with
architectural RNGs.
Signed-off-by: Jason A. Donenfeld
Cc: Thomas Graf
Cc: Herbert Xu
---
Using get_random_int here is faster, more fitting of the use case, and
just as cryptographically secure. It also has the benefit of providing
better randomness at early boot, which is when many of these structures
are assigned.
Also, semantically, it's not really proper to have been assigning an
This is much faster and just as secure. It also has the added benefit of
probably returning better randomness at early-boot on systems with
architectural RNGs.
Signed-off-by: Jason A. Donenfeld
Cc: Thomas Graf
Cc: Herbert Xu
---
lib/rhashtable.c | 2 +-
1 file changed, 1 insertion(+), 1
Using get_random_u32 here is faster, more fitting of the use case, and
just as cryptographically secure. It also has the benefit of providing
better randomness at early boot, which is when many of these structures
are assigned.
Signed-off-by: Jason A. Donenfeld
Cc: David Miller
Using get_random_u32 here is faster, more fitting of the use case, and
just as cryptographically secure. It also has the benefit of providing
better randomness at early boot, which is when many of these structures
are assigned.
Signed-off-by: Jason A. Donenfeld
Cc: David Miller
---
This enables an important dmesg notification about when drivers have
used the crng without it being seeded first. Prior, these errors would
occur silently, and so there hasn't been a great way of diagnosing these
types of bugs for obscure setups. By adding this as a config option, we
can leave it
Otherwise, we might be seeding the RNG using bad randomness, which is
dangerous.
Cc: Herbert Xu
Signed-off-by: Jason A. Donenfeld
---
crypto/rng.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/crypto/rng.c b/crypto/rng.c
Using get_random_u32 here is faster, more fitting of the use case, and
just as cryptographically secure. It also has the benefit of providing
better randomness at early boot, which is sometimes when this is used.
Signed-off-by: Jason A. Donenfeld
Cc: Steve French
It's possible that get_random_{u32,u64} is used before the crng has
initialized, in which case, its output might not be cryptographically
secure. For this problem, directly, this patch set is introducing the
*_wait variety of functions, but even with that, there's a subtle issue:
what happens to
These functions are simple convenience wrappers that call
wait_for_random_bytes before calling the respective get_random_*
function.
Signed-off-by: Jason A. Donenfeld
---
include/linux/net.h| 2 ++
include/linux/once.h | 2 ++
include/linux/random.h | 25
Otherwise, we might be seeding the RNG using bad randomness, which is
dangerous.
Cc: Herbert Xu
Signed-off-by: Jason A. Donenfeld
---
crypto/rng.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/crypto/rng.c b/crypto/rng.c
index f46dac5288b9..e042437e64b4 100644
---
Using get_random_u32 here is faster, more fitting of the use case, and
just as cryptographically secure. It also has the benefit of providing
better randomness at early boot, which is sometimes when this is used.
Signed-off-by: Jason A. Donenfeld
Cc: Steve French
---
fs/cifs/cifsfs.c | 2 +-
1
It's possible that get_random_{u32,u64} is used before the crng has
initialized, in which case, its output might not be cryptographically
secure. For this problem, directly, this patch set is introducing the
*_wait variety of functions, but even with that, there's a subtle issue:
what happens to
This enables an important dmesg notification about when drivers have
used the crng without it being seeded first. Prior, these errors would
occur silently, and so there hasn't been a great way of diagnosing these
types of bugs for obscure setups. By adding this as a config option, we
can leave it
These functions are simple convenience wrappers that call
wait_for_random_bytes before calling the respective get_random_*
function.
Signed-off-by: Jason A. Donenfeld
---
include/linux/net.h| 2 ++
include/linux/once.h | 2 ++
include/linux/random.h | 25 +
3
Ceph uses the RNG for various nonce generations, and it shouldn't accept
using bad randomness. So, we wait for the RNG to be properly seeded. We
do this by calling wait_for_random_bytes() in a function that is
certainly called in process context, early on, so that all subsequent
calls to
Ceph uses the RNG for various nonce generations, and it shouldn't accept
using bad randomness. So, we wait for the RNG to be properly seeded. We
do this by calling wait_for_random_bytes() in a function that is
certainly called in process context, early on, so that all subsequent
calls to
Otherwise, we might use bad random numbers which, particularly in the
case of IV generation, could be quite bad. It makes sense to use the
synchronous API here, because we're always in process context (as the
code is littered with GFP_KERNEL and the like). However, we can't change
to using a
Otherwise, we might use bad random numbers which, particularly in the
case of IV generation, could be quite bad. It makes sense to use the
synchronous API here, because we're always in process context (as the
code is littered with GFP_KERNEL and the like). However, we can't change
to using a
This enables users of get_random_{bytes,u32,u64,int,long} to wait until
the pool is ready before using this function, in case they actually want
to have reliable randomness.
Signed-off-by: Jason A. Donenfeld
---
drivers/char/random.c | 41
As discussed in [1], there is a problem with get_random_bytes being
used before the RNG has actually been seeded. The solution for fixing
this appears to be multi-pronged. One of those prongs involves adding
a simple blocking API so that modules that use the RNG in process
context can just sleep
As discussed in [1], there is a problem with get_random_bytes being
used before the RNG has actually been seeded. The solution for fixing
this appears to be multi-pronged. One of those prongs involves adding
a simple blocking API so that modules that use the RNG in process
context can just sleep
This enables users of get_random_{bytes,u32,u64,int,long} to wait until
the pool is ready before using this function, in case they actually want
to have reliable randomness.
Signed-off-by: Jason A. Donenfeld
---
drivers/char/random.c | 41 +++--
Corentin,
> Instead of rewriting write/readq, use linux/io-64-nonatomic-lo-hi.h
> which already have them.
Applied to 4.13/scsi-queue, thank you!
--
Martin K. Petersen Oracle Linux Engineering
Corentin,
> Instead of rewriting write/readq, use linux/io-64-nonatomic-lo-hi.h
> which already have them.
Applied to 4.13/scsi-queue, thank you!
--
Martin K. Petersen Oracle Linux Engineering
On Mon, Jun 05, 2017 at 10:44:11PM +0200, Rafael J. Wysocki wrote:
> On Mon, Jun 5, 2017 at 9:50 PM, Ross Zwisler
> wrote:
> > Import HMAT table definitions from the ACPICA codebase.
> >
> > This kernel patch was generated using an ACPICA patch from "Zheng, Lv"
> >
On Mon, Jun 05, 2017 at 10:44:11PM +0200, Rafael J. Wysocki wrote:
> On Mon, Jun 5, 2017 at 9:50 PM, Ross Zwisler
> wrote:
> > Import HMAT table definitions from the ACPICA codebase.
> >
> > This kernel patch was generated using an ACPICA patch from "Zheng, Lv"
> > . The actual upstream patch
On Mon, Jun 5, 2017 at 6:33 AM, Ding Tianhong wrote:
>
>
> On 2017/6/4 2:19, Alexander Duyck wrote:
>> On Fri, Jun 2, 2017 at 9:04 PM, Ding Tianhong
>> wrote:
>>> The PCIe Device Control Register use the bit 4 to indicate that
>>> whether the
On Mon, Jun 5, 2017 at 6:33 AM, Ding Tianhong wrote:
>
>
> On 2017/6/4 2:19, Alexander Duyck wrote:
>> On Fri, Jun 2, 2017 at 9:04 PM, Ding Tianhong
>> wrote:
>>> The PCIe Device Control Register use the bit 4 to indicate that
>>> whether the device is permitted to enable relaxed ordering or
2017-05-19 20:42 GMT+09:00 Masahiro Yamada :
> This allows to detect -s (--silent) option without checking GNU Make
> version.
>
> As commit e36aaea28972 ("kbuild: Fix silent builds with make-4")
> pointed out, GNU Make 4.x changed the way/order it presents the
>
2017-05-19 20:42 GMT+09:00 Masahiro Yamada :
> This allows to detect -s (--silent) option without checking GNU Make
> version.
>
> As commit e36aaea28972 ("kbuild: Fix silent builds with make-4")
> pointed out, GNU Make 4.x changed the way/order it presents the
> command line options into
Hi David,
David Miller wrote,
> From: Waldemar Brodkorb
> Date: Mon, 5 Jun 2017 11:19:41 +0200
>
> > I get a compile/linking error with gcc 7.1 when targeting qemu system
> > sparc64.
>
> This should fix the problem, please let me know if it works for you:
Yes, that works
Hi David,
David Miller wrote,
> From: Waldemar Brodkorb
> Date: Mon, 5 Jun 2017 11:19:41 +0200
>
> > I get a compile/linking error with gcc 7.1 when targeting qemu system
> > sparc64.
>
> This should fix the problem, please let me know if it works for you:
Yes, that works fine for me. Thanks
Hi Robert,
I wanted you to update the log.
2017-06-05 20:59 GMT+09:00 Robert Jarzmik :
> When the kernel is compiled with an "O=" argument, the object files are
> not necessarily in the source tree, and more probably in another tree.
Always in another tree.
> In this
Hi Robert,
I wanted you to update the log.
2017-06-05 20:59 GMT+09:00 Robert Jarzmik :
> When the kernel is compiled with an "O=" argument, the object files are
> not necessarily in the source tree, and more probably in another tree.
Always in another tree.
> In this situation, the current
2017-05-20 20:27 GMT+09:00 Nicolas Iooss :
> When compiling with -Wsuggest-attribute=format in HOSTCFLAGS, gcc
> complains that error_with_pos() may be declared with a printf format
> attribute:
>
> scripts/genksyms/genksyms.c:726:3: warning: function might be
>
2017-05-20 20:27 GMT+09:00 Nicolas Iooss :
> When compiling with -Wsuggest-attribute=format in HOSTCFLAGS, gcc
> complains that error_with_pos() may be declared with a printf format
> attribute:
>
> scripts/genksyms/genksyms.c:726:3: warning: function might be
> possible candidate for
As this RFC series matures, all the changes are in this branch here, to look at:
https://git.zx2c4.com/linux-dev/log/?h=jd/rng-blocker
Ted -- there's one, in particular, that should probably be picked up
regardless of the rest, and that's "random: invalidate batched entropy
after crng init".
As this RFC series matures, all the changes are in this branch here, to look at:
https://git.zx2c4.com/linux-dev/log/?h=jd/rng-blocker
Ted -- there's one, in particular, that should probably be picked up
regardless of the rest, and that's "random: invalidate batched entropy
after crng init".
Add two compatible strings for UniPhier SoC family.
"socionext,uniphier-denali-nand-v5a" is used on UniPhier sLD3, LD4,
Pro4, sLD8.
"socionext,uniphier-denali-nand-v5b" is used on UniPhier Pro5, PXs2,
LD6b, LD11, LD20.
Signed-off-by: Masahiro Yamada
---
Changes
Add two compatible strings for UniPhier SoC family.
"socionext,uniphier-denali-nand-v5a" is used on UniPhier sLD3, LD4,
Pro4, sLD8.
"socionext,uniphier-denali-nand-v5b" is used on UniPhier Pro5, PXs2,
LD6b, LD11, LD20.
Signed-off-by: Masahiro Yamada
---
Changes in v4:
- Adjusted to generic
The current bank reset implementation polls the INTR_STATUS register
until interested bits are set. This is not good because:
- polling simply wastes time-slice of the thread
- The while() loop may continue eternally if no bit is set, for
example, due to the controller problem. The
The current bank reset implementation polls the INTR_STATUS register
until interested bits are set. This is not good because:
- polling simply wastes time-slice of the thread
- The while() loop may continue eternally if no bit is set, for
example, due to the controller problem. The
NAND_CMD_PARAM is not working at all due to multiple bugs.
[1] The command 0x90 issued instead of 0xec
The command code 0x90 is hard-code as
index_addr(denali, addr | 0, 0x90)
So, Read ID (0x90) command is sent to the device instead of Read
Parameter Page (0xec).
[2] only first 8 bytes are
NAND_CMD_PARAM is not working at all due to multiple bugs.
[1] The command 0x90 issued instead of 0xec
The command code 0x90 is hard-code as
index_addr(denali, addr | 0, 0x90)
So, Read ID (0x90) command is sent to the device instead of Read
Parameter Page (0xec).
[2] only first 8 bytes are
The denali_cmdfunc() actually does nothing valuable for
NAND_CMD_{PAGEPROG,READ0,SEQIN}.
For NAND_CMD_{READ0,SEQIN}, it copies "page" to "denali->page", then
denali_read_page() and denali_read_page_raw() compare them to check
if the NAND framework called the callbacks in correct order.
This driver stores the currently addressed page into denali->page,
which is later read out by helper functions. While I am tackling on
this driver, I often missed to insert "denali->page = page;" where
needed. This makes page_read/write callbacks to get access to a
wrong page, which is a bug
The denali_cmdfunc() actually does nothing valuable for
NAND_CMD_{PAGEPROG,READ0,SEQIN}.
For NAND_CMD_{READ0,SEQIN}, it copies "page" to "denali->page", then
denali_read_page() and denali_read_page_raw() compare them to check
if the NAND framework called the callbacks in correct order.
This driver stores the currently addressed page into denali->page,
which is later read out by helper functions. While I am tackling on
this driver, I often missed to insert "denali->page = page;" where
needed. This makes page_read/write callbacks to get access to a
wrong page, which is a bug
The Denali IP can automatically detect device parameters such as
page size, oob size, device width, etc. and this driver currently
relies on it. However, this hardware function is known to be
problematic.
[1] Due to a hardware bug, various misdetected cases were reported.
That is why
No need to use two struct resource pointers. Just reuse one.
Signed-off-by: Masahiro Yamada
---
Changes in v4:
- Newly added
Changes in v3: None
Changes in v2: None
drivers/mtd/nand/denali_dt.c | 12 +---
1 file changed, 5 insertions(+), 7
The Denali IP can automatically detect device parameters such as
page size, oob size, device width, etc. and this driver currently
relies on it. However, this hardware function is known to be
problematic.
[1] Due to a hardware bug, various misdetected cases were reported.
That is why
No need to use two struct resource pointers. Just reuse one.
Signed-off-by: Masahiro Yamada
---
Changes in v4:
- Newly added
Changes in v3: None
Changes in v2: None
drivers/mtd/nand/denali_dt.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git
Handling timing parameters in a driver's own way should be avoided
because it duplicates efforts of drivers/mtd/nand/nand_timings.c
Besides, this driver hard-codes Intel specific parameters such as
CLK_X=5, CLK_MULTI=4. Taking a certain device (Samsung K9WAG08U1A)
into account by
It is not a good idea to re-use macros that represent a specific
register bit field for the transfer direction.
It is true that bit 8 indicates the direction for the MAP10 pipeline
operation and the data DMA operation, but this is not valid across
the IP.
Use a simple flag (write: 1, read: 0)
Handling timing parameters in a driver's own way should be avoided
because it duplicates efforts of drivers/mtd/nand/nand_timings.c
Besides, this driver hard-codes Intel specific parameters such as
CLK_X=5, CLK_MULTI=4. Taking a certain device (Samsung K9WAG08U1A)
into account by
It is not a good idea to re-use macros that represent a specific
register bit field for the transfer direction.
It is true that bit 8 indicates the direction for the MAP10 pipeline
operation and the data DMA operation, but this is not valid across
the IP.
Use a simple flag (write: 1, read: 0)
Currently, the error handling of denali_write_page(_raw) is a bit
complicated. If the program command fails, NAND_STATUS_FAIL is set
to the driver internal denali->status, then read out later by
denali_waitfunc().
We can avoid it by exploiting the nand_write_page() implementation.
If
Currently, the error handling of denali_write_page(_raw) is a bit
complicated. If the program command fails, NAND_STATUS_FAIL is set
to the driver internal denali->status, then read out later by
denali_waitfunc().
We can avoid it by exploiting the nand_write_page() implementation.
If
Use BIT() and GENMASK() for register field macros. This will make
it easier to compare the macros with the register description in the
Denali User's Guide.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Newly added
On Mon, Jun 05, 2017 at 04:10:30PM -0700, Joe Perches wrote:
> On Mon, 2017-06-05 at 18:27 -0400, John Brooks wrote:
> > The boolean --color argument did not offer the ability to force colourized
> > output even if stdout is not a terminal.
>
> OK, but why is colorizing output not to terminals
On Mon, Jun 05, 2017 at 04:10:30PM -0700, Joe Perches wrote:
> On Mon, 2017-06-05 at 18:27 -0400, John Brooks wrote:
> > The boolean --color argument did not offer the ability to force colourized
> > output even if stdout is not a terminal.
>
> OK, but why is colorizing output not to terminals
Use BIT() and GENMASK() for register field macros. This will make
it easier to compare the macros with the register description in the
Denali User's Guide.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Newly added
drivers/mtd/nand/denali.h |
This patch series intends to solve various problems.
[1] The driver just retrieves the OOB area as-is
whereas the controller uses syndrome page layout.
[2] Many NAND chip specific parameters are hard-coded in the driver.
[3] ONFi devices are not working
[4] It can not read Bad Block Marker
The nand_scan_ident() iterates over maxchips, and calls nand_reset()
for each. This driver currently passes the maximum number of banks
(=chip selects) supported by the controller as maxchips. So, maxchips
is typically 4 or 8. Usually, less number of NAND chips are connected
to the controller.
The function find_valid_banks() issues the Read ID (0x90) command,
then compares the first byte (Manufacturer ID) of each bank with
the one of bank0.
This is equivalent to what nand_scan_ident() does. The number of
chips is detected there, so this is unneeded.
What is worse for
This patch series intends to solve various problems.
[1] The driver just retrieves the OOB area as-is
whereas the controller uses syndrome page layout.
[2] Many NAND chip specific parameters are hard-coded in the driver.
[3] ONFi devices are not working
[4] It can not read Bad Block Marker
The nand_scan_ident() iterates over maxchips, and calls nand_reset()
for each. This driver currently passes the maximum number of banks
(=chip selects) supported by the controller as maxchips. So, maxchips
is typically 4 or 8. Usually, less number of NAND chips are connected
to the controller.
The function find_valid_banks() issues the Read ID (0x90) command,
then compares the first byte (Manufacturer ID) of each bank with
the one of bank0.
This is equivalent to what nand_scan_ident() does. The number of
chips is detected there, so this is unneeded.
What is worse for
This driver was originally written for the Intel MRST platform with
several platform-specific parameters hard-coded.
Currently, the ECC settings are hard-coded as follows:
#define ECC_SECTOR_SIZE 512
#define ECC_8BITS 14
#define ECC_15BITS 26
Therefore, the driver can only
This driver was originally written for the Intel MRST platform with
several platform-specific parameters hard-coded.
Currently, the ECC settings are hard-coded as follows:
#define ECC_SECTOR_SIZE 512
#define ECC_8BITS 14
#define ECC_15BITS 26
Therefore, the driver can only
The current NAND_CMD_STATUS handling is weird; it just reads the
WRITE_PROTECT register, and returns NAND_STATUS_WP if it is set.
It does not send Read Status (0x70) command, so it is not helpful
for checking the current device status.
Signed-off-by: Masahiro Yamada
Now this driver is ready to remove NAND_SKIP_BBTSCAN.
The BBT descriptors in denali.c are equivalent to the ones in
nand_bbt.c. There is no need to duplicate the equivalent structures.
The with-oob decriptors do not work for this driver anyway.
The bbt_pattern (offs = 8) and the version
The current NAND_CMD_STATUS handling is weird; it just reads the
WRITE_PROTECT register, and returns NAND_STATUS_WP if it is set.
It does not send Read Status (0x70) command, so it is not helpful
for checking the current device status.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Now this driver is ready to remove NAND_SKIP_BBTSCAN.
The BBT descriptors in denali.c are equivalent to the ones in
nand_bbt.c. There is no need to duplicate the equivalent structures.
The with-oob decriptors do not work for this driver anyway.
The bbt_pattern (offs = 8) and the version
Driver are responsible for setting up ECC parameters correctly.
Those include:
- Check if ECC parameters specified (usually by DT) are valid
- Meet the chip's ECC requirement
- Maximize ECC strength if NAND_ECC_MAXIMIZE flag is set
The logic can be generalized by factoring out common code.
Driver are responsible for setting up ECC parameters correctly.
Those include:
- Check if ECC parameters specified (usually by DT) are valid
- Meet the chip's ECC requirement
- Maximize ECC strength if NAND_ECC_MAXIMIZE flag is set
The logic can be generalized by factoring out common code.
For ecc->read_page() and ecc->write_page(), it is possible to call
dma_map_single() against the given buffer. This bypasses the driver
internal bounce buffer and save the memcpy().
Signed-off-by: Masahiro Yamada
---
Changes in v4:
- Remove dma_unmap_single()
Simplify the interrupt handling and fix issues:
- The register field view of INTR_EN / INTR_STATUS is different
among IP versions. The global macro DENALI_IRQ_ALL is hard-coded
for Intel platforms. The interrupt mask should be determined at
run-time depending on the running platform.
-
Now struct nand_buf has only two members, so I see no reason for the
separation.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Newly added
drivers/mtd/nand/denali.c | 29 ++---
Simplify the interrupt handling and fix issues:
- The register field view of INTR_EN / INTR_STATUS is different
among IP versions. The global macro DENALI_IRQ_ALL is hard-coded
for Intel platforms. The interrupt mask should be determined at
run-time depending on the running platform.
-
Now struct nand_buf has only two members, so I see no reason for the
separation.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Newly added
drivers/mtd/nand/denali.c | 29 ++---
drivers/mtd/nand/denali.h | 8 ++--
2
For ecc->read_page() and ecc->write_page(), it is possible to call
dma_map_single() against the given buffer. This bypasses the driver
internal bounce buffer and save the memcpy().
Signed-off-by: Masahiro Yamada
---
Changes in v4:
- Remove dma_unmap_single() from denali_remove()
Changes in
The Denali IP adopts the syndrome page layout; payload and ECC are
interleaved, with BBM area always placed at the beginning of OOB.
The figure below shows the page organization for ecc->steps == 2:
|||---|
||| |
||
The Denali IP adopts the syndrome page layout; payload and ECC are
interleaved, with BBM area always placed at the beginning of OOB.
The figure below shows the page organization for ecc->steps == 2:
|||---|
||| |
||
As Russell and Lars stated in the discussion [1], using
devm_k*alloc() with DMA is not a good idea.
Let's use kmalloc (not kzalloc because no need for zero-out).
Also, allocate the buffer as late as possible because it must be
freed for any error that follows.
[1]
As Russell and Lars stated in the discussion [1], using
devm_k*alloc() with DMA is not a good idea.
Let's use kmalloc (not kzalloc because no need for zero-out).
Also, allocate the buffer as late as possible because it must be
freed for any error that follows.
[1]
The NAND_CMD_SET_FEATURES support is missing from denali_cmdfunc().
This is needed for nand_onfi_set_features().
Besides, we see /* TODO: Read OOB data */ comment line.
It would be possible to add more commands along with the current
implementation, but having ->cmd_ctrl() seems a better
The NAND_CMD_SET_FEATURES support is missing from denali_cmdfunc().
This is needed for nand_onfi_set_features().
Besides, we see /* TODO: Read OOB data */ comment line.
It would be possible to add more commands along with the current
implementation, but having ->cmd_ctrl() seems a better
CPSW driver does not handle this interrupt, so there are no reasons to enable
it in hardware.
Signed-off-by: Grygorii Strashko
---
drivers/net/ethernet/ti/davinci_cpdma.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git
CPSW driver does not handle this interrupt, so there are no reasons to enable
it in hardware.
Signed-off-by: Grygorii Strashko
---
drivers/net/ethernet/ti/davinci_cpdma.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c
CPSW driver supports PTP v1 messages, but for unknown reasons this filter
is not advertised. As result,
./tools/testing/selftests/networking/timestamping/timestamping utility
can't be used for testing of CPSW RX timestamping with option
SOF_TIMESTAMPING_RX_HARDWARE, because it uses
CPSW driver supports PTP v1 messages, but for unknown reasons this filter
is not advertised. As result,
./tools/testing/selftests/networking/timestamping/timestamping utility
can't be used for testing of CPSW RX timestamping with option
SOF_TIMESTAMPING_RX_HARDWARE, because it uses
On Mon, Jun 5, 2017 at 5:47 AM, Jason A. Donenfeld wrote:
> - get_random_bytes(>serial, sizeof(key->serial));
> + ret = get_random_bytes_wait(>serial,
> sizeof(key->serial));
This actually isn't okay at bootup, but I've got a different change
for
On Mon, Jun 5, 2017 at 5:47 AM, Jason A. Donenfeld wrote:
> - get_random_bytes(>serial, sizeof(key->serial));
> + ret = get_random_bytes_wait(>serial,
> sizeof(key->serial));
This actually isn't okay at bootup, but I've got a different change
for this section that
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