[PATCH v2 8/8] sched/rt: make it configurable

On most small systems where user space is tightly controlled, the realtime scheduling class can often be dispensed with to reduce the kernel footprint. Let's make it configurable. The code that makes explicit assumptions about actual RT mutexes (i.e where the compatibility wrappers don't make

[PATCH v2 7/8] rtmutex: compatibility wrappers when no RT support is configured

Prepare the code for the next patch making RT task support optional. With no actual RT task, there is no priority inversion issues to care about. We can therefore map RT mutexes to regular mutexes in that case and remain compatible with most users. The code that makes explicit assumptions about

[PATCH v2 2/8] sched: omit stop_sched_class when !SMP

The stop class is invoked through stop_machine only. This is dead code on UP builds. Signed-off-by: Nicolas Pitre --- kernel/sched/Makefile | 4 ++-- kernel/sched/core.c | 60 +-- kernel/sched/sched.h | 4 3 files

[PATCH v2 2/8] sched: omit stop_sched_class when !SMP

The stop class is invoked through stop_machine only. This is dead code on UP builds. Signed-off-by: Nicolas Pitre --- kernel/sched/Makefile | 4 ++-- kernel/sched/core.c | 60 +-- kernel/sched/sched.h | 4 3 files changed, 36

[PATCH v2 0/8] scheduler tinification

Many embedded systems don't need the full scheduler support. Most of the time, user space is tightly controlled and many of the scheduler facilities are simply unused. This patch series makes it possible to configure out some parts of the scheduler such as the deadline and realtime scheduler

[PATCH v2 0/8] scheduler tinification

Many embedded systems don't need the full scheduler support. Most of the time, user space is tightly controlled and many of the scheduler facilities are simply unused. This patch series makes it possible to configure out some parts of the scheduler such as the deadline and realtime scheduler

Re: [PATCH v2] X86: don't report PAT on CPUs that don't support it

On Tue, 6 Jun 2017, Andy Lutomirski wrote: > On Tue, Jun 6, 2017 at 3:49 PM, Mikulas Patocka wrote: > > > > > > On Sun, 28 May 2017, Andy Lutomirski wrote: > > > >> On Sun, May 28, 2017 at 11:18 AM, Bernhard Held wrote: > >> > Hi, > >> > > >> > this patch

Re: [PATCH v2] X86: don't report PAT on CPUs that don't support it

On Tue, 6 Jun 2017, Andy Lutomirski wrote: > On Tue, Jun 6, 2017 at 3:49 PM, Mikulas Patocka wrote: > > > > > > On Sun, 28 May 2017, Andy Lutomirski wrote: > > > >> On Sun, May 28, 2017 at 11:18 AM, Bernhard Held wrote: > >> > Hi, > >> > > >> > this patch breaks the boot of my kernel. The

[PATCH] net: wireless: intel: iwlwifi: dvm: remove unused defines

Those constants have been unused for quite some time now. Signed-off-by: Seraphime Kirkovski --- I've compile-tested it. drivers/net/wireless/intel/iwlwifi/dvm/commands.h | 7 --- 1 file changed, 7 deletions(-) diff --git

[PATCH] net: wireless: intel: iwlwifi: dvm: remove unused defines

Those constants have been unused for quite some time now. Signed-off-by: Seraphime Kirkovski --- I've compile-tested it. drivers/net/wireless/intel/iwlwifi/dvm/commands.h | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/commands.h

Re: [RFC 11/55] KVM: arm64: Emulate taking an exception to the guest hypervisor

On Tue, Jun 6, 2017 at 6:07 PM, Bandan Das wrote: > Hi Jintack, > > Jintack Lim writes: > >> Hi Bandan, >> >> On Tue, Jun 6, 2017 at 4:21 PM, Bandan Das wrote: >>> Jintack Lim writes: >>> Emulate taking an

Re: [RFC 11/55] KVM: arm64: Emulate taking an exception to the guest hypervisor

On Tue, Jun 6, 2017 at 6:07 PM, Bandan Das wrote: > Hi Jintack, > > Jintack Lim writes: > >> Hi Bandan, >> >> On Tue, Jun 6, 2017 at 4:21 PM, Bandan Das wrote: >>> Jintack Lim writes: >>> Emulate taking an exception to the guest hypervisor running in the virtual EL2 as described in

Re: [kernel-hardening] Re: [PATCH v3 04/13] crypto/rng: ensure that the RNG is ready before using

On Tue, Jun 06, 2017 at 07:19:10PM -0300, Henrique de Moraes Holschuh wrote: > On that same idea, one could add an early_initramfs handler for entropy > data. > > One could also ensure the kernel command line is used to feed some > entropy for the CRNG init (for all I know, this is already being

Re: [kernel-hardening] Re: [PATCH v3 04/13] crypto/rng: ensure that the RNG is ready before using

On Tue, Jun 06, 2017 at 07:19:10PM -0300, Henrique de Moraes Holschuh wrote: > On that same idea, one could add an early_initramfs handler for entropy > data. > > One could also ensure the kernel command line is used to feed some > entropy for the CRNG init (for all I know, this is already being

[PATCH 01/17] drivers: support PCIe in RISCV

From: "Wesley W. Terpstra" There are RISC-V systems that have been mapped to Xilinx FPGAs that have their PCIe controllers on chip. These build system changes allow RISC-V systems to enable the Xilinx PCIe controller, and to setup PCIe IRQs. Signed-off-by: Palmer Dabbelt

[PATCH 01/17] drivers: support PCIe in RISCV

From: "Wesley W. Terpstra" There are RISC-V systems that have been mapped to Xilinx FPGAs that have their PCIe controllers on chip. These build system changes allow RISC-V systems to enable the Xilinx PCIe controller, and to setup PCIe IRQs. Signed-off-by: Palmer Dabbelt ---

[PATCH 03/17] base: fix order of OF initialization

From: "Wesley W. Terpstra" This fixes: [0.01] cpu cpu0: Error -2 creating of_node link ... which you get for every CPU on all architectures with a OF cpu/ node. This affects riscv, nios, etc. Signed-off-by: Palmer Dabbelt --- drivers/base/init.c

Re: [PATCH 2/3] fs/locks: Remove fl_nspid

On Tue, 2017-06-06 at 14:57 -0400, Benjamin Coddington wrote: > On 6 Jun 2017, at 14:25, Jeff Layton wrote: > > > On Tue, 2017-06-06 at 14:00 -0400, Jeff Layton wrote: > > > On Tue, 2017-06-06 at 13:19 -0400, Benjamin Coddington wrote: > > > > Since commit c69899a17ca4 "NFSv4: Update of VFS byte

Re: [PATCH 10/16] powerpc: vio: use dev_groups and not dev_attrs for bus_type

On Tue, 2017-06-06 at 21:30 +0200, Greg Kroah-Hartman wrote: > >   > >   static struct device_attribute vio_dev_attrs[] = { > >    __ATTR_RO(name), > > @@ -1573,6 +1576,13 @@ static struct device_attribute vio_dev_attrs[] = { > >    __ATTR_RO(modalias), > >    __ATTR_NULL > >   }; > >

Re: [PATCH 10/16] powerpc: vio: use dev_groups and not dev_attrs for bus_type

On Tue, 2017-06-06 at 21:30 +0200, Greg Kroah-Hartman wrote: > >   > >   static struct device_attribute vio_dev_attrs[] = { > >    __ATTR_RO(name), > > @@ -1573,6 +1576,13 @@ static struct device_attribute vio_dev_attrs[] = { > >    __ATTR_RO(modalias), > >    __ATTR_NULL > >   }; > >

[PATCH 03/17] base: fix order of OF initialization

From: "Wesley W. Terpstra" This fixes: [0.01] cpu cpu0: Error -2 creating of_node link ... which you get for every CPU on all architectures with a OF cpu/ node. This affects riscv, nios, etc. Signed-off-by: Palmer Dabbelt --- drivers/base/init.c | 2 +- 1 file changed, 1

Re: [PATCH 2/3] fs/locks: Remove fl_nspid

On Tue, 2017-06-06 at 14:57 -0400, Benjamin Coddington wrote: > On 6 Jun 2017, at 14:25, Jeff Layton wrote: > > > On Tue, 2017-06-06 at 14:00 -0400, Jeff Layton wrote: > > > On Tue, 2017-06-06 at 13:19 -0400, Benjamin Coddington wrote: > > > > Since commit c69899a17ca4 "NFSv4: Update of VFS byte

RISC-V Linux Port v2

Thanks to everyone who has participated in the review process so far. We've made a lot of changes since the v1 and while this isn't ready to go yet, I finally managed to get through everything in my inbox so I thought it would be a good time to submit a v2 so everyone is on the same page. A

RISC-V Linux Port v2

Thanks to everyone who has participated in the review process so far. We've made a lot of changes since the v1 and while this isn't ready to go yet, I finally managed to get through everything in my inbox so I thought it would be a good time to submit a v2 so everyone is on the same page. A

[PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers

From: "Wesley W. Terpstra" Signed-off-by: Palmer Dabbelt --- .../interrupt-controller/riscv,cpu-intc.txt| 46 ++ .../bindings/interrupt-controller/riscv,plic0.txt | 44 + 2 files changed, 90 insertions(+)

[PATCH 11/17] irqchip: RISC-V Local Interrupt Controller Driver

This patch adds a driver that manages the local interrupts on each RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual. The local interrupt controller manages software interrupts, timer interrupts, and hardware interrupts (which are routed via the platform level interrupt

[PATCH 07/17] lib: Add shared copies of some GCC library routines

Many ports (m32r, microblaze, mips, parisc, score, and sparc) use functionally identical copies of various GCC library routine files, which came up as we were submitting the RISC-V port (which also uses some of these). This patch adds a new copy of these library routine files, which are

[PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers

From: "Wesley W. Terpstra" Signed-off-by: Palmer Dabbelt --- .../interrupt-controller/riscv,cpu-intc.txt| 46 ++ .../bindings/interrupt-controller/riscv,plic0.txt | 44 + 2 files changed, 90 insertions(+) create mode 100644

[PATCH 11/17] irqchip: RISC-V Local Interrupt Controller Driver

This patch adds a driver that manages the local interrupts on each RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual. The local interrupt controller manages software interrupts, timer interrupts, and hardware interrupts (which are routed via the platform level interrupt

[PATCH 07/17] lib: Add shared copies of some GCC library routines

Many ports (m32r, microblaze, mips, parisc, score, and sparc) use functionally identical copies of various GCC library routine files, which came up as we were submitting the RISC-V port (which also uses some of these). This patch adds a new copy of these library routine files, which are

[PATCH 12/17] tty: New RISC-V SBI Console Driver

This patch adds a new driver for the console availiable via the RISC-V SBI. This console is specified to be used for early boot messages, and is designed to be a very simple (albiet somewhat slow) console that is always availiable. All RISC-V systems have an SBI console. The SBI console is made

[PATCH 12/17] tty: New RISC-V SBI Console Driver

This patch adds a new driver for the console availiable via the RISC-V SBI. This console is specified to be used for early boot messages, and is designed to be a very simple (albiet somewhat slow) console that is always availiable. All RISC-V systems have an SBI console. The SBI console is made

Re: [PATCH 2/2] amd: uncore: Get correct number of cores sharing last level cache

On 06/06/2017 12:45 PM, Borislav Petkov wrote: On Tue, Jun 06, 2017 at 12:15:30PM +0200, Peter Zijlstra wrote: Maybe something like: for (cache_level = 0; cache_level < 3; cache_level++) { cpuid_count(0x801d, cache_level, , , , ); if ((eax & 0x1f)

Re: [PATCH 2/2] amd: uncore: Get correct number of cores sharing last level cache

On 06/06/2017 12:45 PM, Borislav Petkov wrote: On Tue, Jun 06, 2017 at 12:15:30PM +0200, Peter Zijlstra wrote: Maybe something like: for (cache_level = 0; cache_level < 3; cache_level++) { cpuid_count(0x801d, cache_level, , , , ); if ((eax & 0x1f)

[PATCH 15/17] RISC-V: Add mm subdirectory

These files are mostly based on the score port, but as all the non-stub functions are very ISA specific they've been heavily modified. Signed-off-by: Palmer Dabbelt --- arch/riscv/mm/Makefile | 1 + arch/riscv/mm/extable.c | 37 +++ arch/riscv/mm/fault.c | 280

[PATCH 05/17] MAINTAINERS: Add RISC-V

From: Jonathan Neuschäfer RISC-V needs a MAINTAINERS entry. Let's add one. Signed-off-by: Jonathan Neuschäfer Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git

[PATCH 15/17] RISC-V: Add mm subdirectory

These files are mostly based on the score port, but as all the non-stub functions are very ISA specific they've been heavily modified. Signed-off-by: Palmer Dabbelt --- arch/riscv/mm/Makefile | 1 + arch/riscv/mm/extable.c | 37 +++ arch/riscv/mm/fault.c | 280

[PATCH 05/17] MAINTAINERS: Add RISC-V

From: Jonathan Neuschäfer RISC-V needs a MAINTAINERS entry. Let's add one. Signed-off-by: Jonathan Neuschäfer Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7a28acd7f525..50b18dad8c22 100644 ---

[PATCH 14/17] RISC-V: lib files

Most of these files are based off code in GCC, but the delay code is mostly from ARM. Signed-off-by: Palmer Dabbelt --- arch/riscv/lib/Makefile | 5 ++ arch/riscv/lib/delay.c | 107 arch/riscv/lib/memcpy.S | 98

[PATCH 16/17] RISC-V: Add kernel subdirectory

These files were mostly based on the score port, but many of them are very ISA specific. Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/.gitignore | 1 + arch/riscv/kernel/Makefile | 16 ++ arch/riscv/kernel/asm-offsets.c| 316

[PATCH 14/17] RISC-V: lib files

Most of these files are based off code in GCC, but the delay code is mostly from ARM. Signed-off-by: Palmer Dabbelt --- arch/riscv/lib/Makefile | 5 ++ arch/riscv/lib/delay.c | 107 arch/riscv/lib/memcpy.S | 98

[PATCH 16/17] RISC-V: Add kernel subdirectory

These files were mostly based on the score port, but many of them are very ISA specific. Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/.gitignore | 1 + arch/riscv/kernel/Makefile | 16 ++ arch/riscv/kernel/asm-offsets.c| 316 +++

[PATCH 17/17] RISC-V: Makefile and Kconfig

This patch adds RISC-V support to the build infastructure. Signed-off-by: Palmer Dabbelt --- Makefile | 3 +- arch/riscv/Kconfig| 318 ++ arch/riscv/Makefile | 64

[PATCH 17/17] RISC-V: Makefile and Kconfig

This patch adds RISC-V support to the build infastructure. Signed-off-by: Palmer Dabbelt --- Makefile | 3 +- arch/riscv/Kconfig| 318 ++ arch/riscv/Makefile | 64 ++

[PATCH 10/17] irqchip: New RISC-V PLIC Driver

This patch adds a driver for the Platform Level Interrupt Controller (PLIC) specified as part of the RISC-V supervisor level ISA manual. The PLIC connocts global interrupt sources to the local interrupt controller on each hart. A PLIC is present on all RISC-V systems. Signed-off-by: Palmer

[PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource}

While upstreaming the RISC-V port, it was pointed out that multiple architectures (arc, arm64, cris, microblaze, sh, tile) have copied the mostly empty versions of at least one of these functions. This defines weakly bound versions of the common functions so other architetures can use them.

[PATCH 10/17] irqchip: New RISC-V PLIC Driver

This patch adds a driver for the Platform Level Interrupt Controller (PLIC) specified as part of the RISC-V supervisor level ISA manual. The PLIC connocts global interrupt sources to the local interrupt controller on each hart. A PLIC is present on all RISC-V systems. Signed-off-by: Palmer

[PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource}

While upstreaming the RISC-V port, it was pointed out that multiple architectures (arc, arm64, cris, microblaze, sh, tile) have copied the mostly empty versions of at least one of these functions. This defines weakly bound versions of the common functions so other architetures can use them.

[PATCH 02/17] pcie-xilinx: add missing 5th legacy interrupt

From: "Wesley W. Terpstra" These are numbered from 1. Signed-off-by: Palmer Dabbelt --- drivers/pci/host/pcie-xilinx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c

[PATCH 09/17] clocksource/timer-riscv: New RISC-V Clocksource

The RISC-V ISA defines a single RTC as well as an SBI oneshot timer. This timer is present on all RISC-V systems. Signed-off-by: Palmer Dabbelt --- drivers/clocksource/Kconfig | 8 +++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-riscv.c | 118

[PATCH 02/17] pcie-xilinx: add missing 5th legacy interrupt

From: "Wesley W. Terpstra" These are numbered from 1. Signed-off-by: Palmer Dabbelt --- drivers/pci/host/pcie-xilinx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 2fe2df51f9f8..8804145d399a

[PATCH 09/17] clocksource/timer-riscv: New RISC-V Clocksource

The RISC-V ISA defines a single RTC as well as an SBI oneshot timer. This timer is present on all RISC-V systems. Signed-off-by: Palmer Dabbelt --- drivers/clocksource/Kconfig | 8 +++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-riscv.c | 118

[PATCH] thermal: int340x: check for sensor when PTYP is missing

For INT3403 sensor PTYP field is mandatory. But some platforms didn't have this field for sensors. This cause load failure for int3403 driver. This change checks for the presence of _TMP method and if present, then treats this device as a sensor. Signed-off-by: Srinivas Pandruvada

[PATCH] thermal: int340x: check for sensor when PTYP is missing

For INT3403 sensor PTYP field is mandatory. But some platforms didn't have this field for sensors. This cause load failure for int3403 driver. This change checks for the presence of _TMP method and if present, then treats this device as a sensor. Signed-off-by: Srinivas Pandruvada ---

[PATCH 04/17] Documentation: atomic_ops.txt is core-api/atomic_ops.rst

I was reading the memory barries documentation in order to make sure the RISC-V barries were correct, and I found a broken link to the atomic operations documentation. Signed-off-by: Palmer Dabbelt --- Documentation/memory-barriers.txt | 10 +- 1 file changed, 5

[PATCH 04/17] Documentation: atomic_ops.txt is core-api/atomic_ops.rst

I was reading the memory barries documentation in order to make sure the RISC-V barries were correct, and I found a broken link to the atomic operations documentation. Signed-off-by: Palmer Dabbelt --- Documentation/memory-barriers.txt | 10 +- 1 file changed, 5 insertions(+), 5

Re: [PATCH v2] X86: don't report PAT on CPUs that don't support it

On Tue, Jun 6, 2017 at 3:49 PM, Mikulas Patocka wrote: > > > On Sun, 28 May 2017, Andy Lutomirski wrote: > >> On Sun, May 28, 2017 at 11:18 AM, Bernhard Held wrote: >> > Hi, >> > >> > this patch breaks the boot of my kernel. The last message is "Booting >> >

Re: [PATCH v2] X86: don't report PAT on CPUs that don't support it

On Tue, Jun 6, 2017 at 3:49 PM, Mikulas Patocka wrote: > > > On Sun, 28 May 2017, Andy Lutomirski wrote: > >> On Sun, May 28, 2017 at 11:18 AM, Bernhard Held wrote: >> > Hi, >> > >> > this patch breaks the boot of my kernel. The last message is "Booting >> > the kernel.". >> > >> > My setup

[PATCH v2] X86: don't report PAT on CPUs that don't support it

On Sun, 28 May 2017, Andy Lutomirski wrote: > On Sun, May 28, 2017 at 11:18 AM, Bernhard Held wrote: > > Hi, > > > > this patch breaks the boot of my kernel. The last message is "Booting > > the kernel.". > > > > My setup might be unusual: I'm running a Xenon E5450 (LGA 771)

[PATCH v2] X86: don't report PAT on CPUs that don't support it

On Sun, 28 May 2017, Andy Lutomirski wrote: > On Sun, May 28, 2017 at 11:18 AM, Bernhard Held wrote: > > Hi, > > > > this patch breaks the boot of my kernel. The last message is "Booting > > the kernel.". > > > > My setup might be unusual: I'm running a Xenon E5450 (LGA 771) in a > > Gigbayte

Re: WARNING: CPU: 0 PID: 1752 at arch/x86/kernel/traps.c:788

On Thu, Jun 1, 2017 at 3:46 PM, Richard Weinberger wrote: > Hi! > > UserModeLinux hits the following warning on the host. > I've extracted the evil ptrace() command sequence, please see attached > program, > it triggers the warning too. This sounds like a known QEMU bug. Paolo,

Re: WARNING: CPU: 0 PID: 1752 at arch/x86/kernel/traps.c:788

On Thu, Jun 1, 2017 at 3:46 PM, Richard Weinberger wrote: > Hi! > > UserModeLinux hits the following warning on the host. > I've extracted the evil ptrace() command sequence, please see attached > program, > it triggers the warning too. This sounds like a known QEMU bug. Paolo, did this get

Re: next build: 113 warnings 0 failures (next/next-20170605)

> > 2 drivers/i2c/i2c-stub.c:18:0: warning: "DEBUG" redefined > > Caused by 6c42778780c4 ("i2c: stub: use pr_fmt"): "#define DEBUG" > now conflicts with "ccflags-$(CONFIG_I2C_DEBUG_CORE) := -DDEBUG" > in the Makefile. I'll fix it tomorrow! signature.asc Description: PGP signature

Re: next build: 113 warnings 0 failures (next/next-20170605)

> > 2 drivers/i2c/i2c-stub.c:18:0: warning: "DEBUG" redefined > > Caused by 6c42778780c4 ("i2c: stub: use pr_fmt"): "#define DEBUG" > now conflicts with "ccflags-$(CONFIG_I2C_DEBUG_CORE) := -DDEBUG" > in the Makefile. I'll fix it tomorrow! signature.asc Description: PGP signature

Re: [PATCH 13/16] hid: intel-ish-hid: use dev_groups and not dev_attrs for bus_type

On Tue, 2017-06-06 at 21:22 +0200, Greg Kroah-Hartman wrote: > The dev_attrs field has long been "depreciated" and is finally being > removed, so move the driver to use the "correct" dev_groups field > instead for struct bus_type. > > Cc: Srinivas Pandruvada

Re: [PATCH 13/16] hid: intel-ish-hid: use dev_groups and not dev_attrs for bus_type

On Tue, 2017-06-06 at 21:22 +0200, Greg Kroah-Hartman wrote: > The dev_attrs field has long been "depreciated" and is finally being > removed, so move the driver to use the "correct" dev_groups field > instead for struct bus_type. > > Cc: Srinivas Pandruvada > Cc: Jiri Kosina > Cc: Benjamin

Re: [PATCH v2] platform/x86: wmi-bmof: New driver to expose embedded Binary WMI MOF metadata

On Mon, Jun 5, 2017 at 8:16 PM, Andy Lutomirski wrote: > +static ssize_t > +read_bmof(struct file *filp, struct kobject *kobj, > +struct bin_attribute *attr, > +char *buf, loff_t off, size_t count) > +{ > + struct bmof_priv *priv = > +

Re: [PATCH v2] platform/x86: wmi-bmof: New driver to expose embedded Binary WMI MOF metadata

On Mon, Jun 5, 2017 at 8:16 PM, Andy Lutomirski wrote: > +static ssize_t > +read_bmof(struct file *filp, struct kobject *kobj, > +struct bin_attribute *attr, > +char *buf, loff_t off, size_t count) > +{ > + struct bmof_priv *priv = > + container_of(attr, struct

Re: [PATCH v6 00/11] Broadcom Stingray SOC Initial Support

On 06/05, Florian Fainelli wrote: > > > On 06/05/2017 09:51 AM, Florian Fainelli wrote: > > On 06/01/2017 11:34 PM, Anup Patel wrote: > >> This patchset adds initial support of Broadcom Stingray SOC > >> by reusing existing Broadcom iProc device drivers. > >> > >> Most of the patches in this

Re: [PATCH v6 00/11] Broadcom Stingray SOC Initial Support

On 06/05, Florian Fainelli wrote: > > > On 06/05/2017 09:51 AM, Florian Fainelli wrote: > > On 06/01/2017 11:34 PM, Anup Patel wrote: > >> This patchset adds initial support of Broadcom Stingray SOC > >> by reusing existing Broadcom iProc device drivers. > >> > >> Most of the patches in this

Re: [PATCH] x86/ldt: Rename ldr_struct.size to .n_entries

On Tue, Jun 6, 2017 at 10:31 AM, Borislav Petkov wrote: > From: Borislav Petkov > > ... because this is exactly what it is: the number of entries in the > LDT. Calling it "size" is simply confusing and it is actually begging > to be called "n_entries" or somesuch,

Re: [PATCH] x86/ldt: Rename ldr_struct.size to .n_entries

On Tue, Jun 6, 2017 at 10:31 AM, Borislav Petkov wrote: > From: Borislav Petkov > > ... because this is exactly what it is: the number of entries in the > LDT. Calling it "size" is simply confusing and it is actually begging > to be called "n_entries" or somesuch, especially if you see

Re: [kernel-hardening] Re: [PATCH v3 04/13] crypto/rng: ensure that the RNG is ready before using

On Tue, 06 Jun 2017, Theodore Ts'o wrote: > It might be possible, for example, to store a cryptographic key in a > UEFI boot-services variable, where the key becomes inaccessible after > the boot-time services terminate. But you also need either a reliable > time-of-day clock, or a reliable

Re: [kernel-hardening] Re: [PATCH v3 04/13] crypto/rng: ensure that the RNG is ready before using

On Tue, 06 Jun 2017, Theodore Ts'o wrote: > It might be possible, for example, to store a cryptographic key in a > UEFI boot-services variable, where the key becomes inaccessible after > the boot-time services terminate. But you also need either a reliable > time-of-day clock, or a reliable

Re: [PATCH v2] firmware: fix sending -ERESTARTSYS due to signal on fallback

On Tue, Jun 06, 2017 at 06:47:34PM +0200, Luis R. Rodriguez wrote: > On Tue, Jun 06, 2017 at 03:53:16PM +0100, Alan Cox wrote: > > Yep everyone codes > > > > write(disk_file, "foo", 3); > > > > not while(..) blah around it. In general I/O to tty devices and other character mode devices was

Re: [PATCH v4] hsdk: initial port for HSDK board

On 06/05/2017 12:50 PM, Alexey Brodkin wrote: This initial port adds support of ARC HS Development Kit board with some basic features such serial port, USB, SD/MMC and Ethernet. Essentially we run Linux kernel on all 4 cores (i.e. utilize SMP) and heavily use IO Coherency for speeding-up

Re: [PATCH v2] firmware: fix sending -ERESTARTSYS due to signal on fallback

On Tue, Jun 06, 2017 at 06:47:34PM +0200, Luis R. Rodriguez wrote: > On Tue, Jun 06, 2017 at 03:53:16PM +0100, Alan Cox wrote: > > Yep everyone codes > > > > write(disk_file, "foo", 3); > > > > not while(..) blah around it. In general I/O to tty devices and other character mode devices was

Re: [PATCH v4] hsdk: initial port for HSDK board

On 06/05/2017 12:50 PM, Alexey Brodkin wrote: This initial port adds support of ARC HS Development Kit board with some basic features such serial port, USB, SD/MMC and Ethernet. Essentially we run Linux kernel on all 4 cores (i.e. utilize SMP) and heavily use IO Coherency for speeding-up

[PATCH] m68k: remove ptrace_signal_deliver

This fixes debugger syscall restart interactions. A debugger that modifies the tracee's program counter is expected to set the orig_d0 pseudo register to -1, to disable a possible syscall restart. This removes the last user of the ptrace_signal_deliver hook in the ptrace signal handling, so

[PATCH] m68k: remove ptrace_signal_deliver

This fixes debugger syscall restart interactions. A debugger that modifies the tracee's program counter is expected to set the orig_d0 pseudo register to -1, to disable a possible syscall restart. This removes the last user of the ptrace_signal_deliver hook in the ptrace signal handling, so

Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

On 05/27/2017 11:52 PM, Noam Camus wrote: From: Noam Camus This commit adds the configuration CONFIG_EZNPS_MEM_ERROR. If set, it will cause the kernel to handle user memory error as a machine check exception. It is required in order to align the NPS simulator memory error

Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

On 05/27/2017 11:52 PM, Noam Camus wrote: From: Noam Camus This commit adds the configuration CONFIG_EZNPS_MEM_ERROR. If set, it will cause the kernel to handle user memory error as a machine check exception. It is required in order to align the NPS simulator memory error handling to the one

Re: [PATCH v4 00/23] mtd: nand: denali: Denali NAND IP patch bomb

Hi Masahiro, On Tue, 6 Jun 2017 08:21:39 +0900 Masahiro Yamada wrote: > This patch series intends to solve various problems. > > [1] The driver just retrieves the OOB area as-is > whereas the controller uses syndrome page layout. > [2] Many NAND chip

Re: [PATCH v4 00/23] mtd: nand: denali: Denali NAND IP patch bomb

Hi Masahiro, On Tue, 6 Jun 2017 08:21:39 +0900 Masahiro Yamada wrote: > This patch series intends to solve various problems. > > [1] The driver just retrieves the OOB area as-is > whereas the controller uses syndrome page layout. > [2] Many NAND chip specific parameters are hard-coded in

Re: [PATCH] clk: sunxi-ng: Move all clock types to a library

On 06/06, Arnd Bergmann wrote: > On Mon, Jun 5, 2017 at 4:45 PM, Maxime Ripard > wrote: > > Hi, > > > > On Sat, Jun 03, 2017 at 12:22:32PM +0800, kbuild test robot wrote: > >> Hi Stephen, > >> > >> [auto build test ERROR on sunxi/sunxi/for-next] > >> [also build

Re: [PATCH] clk: sunxi-ng: Move all clock types to a library

On 06/06, Arnd Bergmann wrote: > On Mon, Jun 5, 2017 at 4:45 PM, Maxime Ripard > wrote: > > Hi, > > > > On Sat, Jun 03, 2017 at 12:22:32PM +0800, kbuild test robot wrote: > >> Hi Stephen, > >> > >> [auto build test ERROR on sunxi/sunxi/for-next] > >> [also build test ERROR on next-20170602] > >>

Re: [xfstests PATCH v3 1/5] generic: add a writeback error handling test

On Tue, Jun 06, 2017 at 04:12:58PM -0400, Jeff Layton wrote: > On Tue, 2017-06-06 at 10:17 -0700, Darrick J. Wong wrote: > > On Tue, Jun 06, 2017 at 08:23:25PM +0800, Eryu Guan wrote: > > > On Tue, Jun 06, 2017 at 06:15:57AM -0400, Jeff Layton wrote: > > > > On Tue, 2017-06-06 at 16:58 +0800, Eryu

Re: [xfstests PATCH v3 1/5] generic: add a writeback error handling test

On Tue, Jun 06, 2017 at 04:12:58PM -0400, Jeff Layton wrote: > On Tue, 2017-06-06 at 10:17 -0700, Darrick J. Wong wrote: > > On Tue, Jun 06, 2017 at 08:23:25PM +0800, Eryu Guan wrote: > > > On Tue, Jun 06, 2017 at 06:15:57AM -0400, Jeff Layton wrote: > > > > On Tue, 2017-06-06 at 16:58 +0800, Eryu

Re: [RFC 11/55] KVM: arm64: Emulate taking an exception to the guest hypervisor

Hi Jintack, Jintack Lim writes: > Hi Bandan, > > On Tue, Jun 6, 2017 at 4:21 PM, Bandan Das wrote: >> Jintack Lim writes: >> >>> Emulate taking an exception to the guest hypervisor running in the >>> virtual EL2 as described in

Re: [RFC 11/55] KVM: arm64: Emulate taking an exception to the guest hypervisor

Hi Jintack, Jintack Lim writes: > Hi Bandan, > > On Tue, Jun 6, 2017 at 4:21 PM, Bandan Das wrote: >> Jintack Lim writes: >> >>> Emulate taking an exception to the guest hypervisor running in the >>> virtual EL2 as described in ARM ARM AArch64.TakeException(). >> >> ARM newbie here, I keep

Re: [PATCH] external references for device tree overlays

On Tue, Jun 6, 2017 at 2:17 PM, Stefani Seibold wrote: > Hi Pantelis, > > thanks for the suggestion. This feature is not very well documented. I > tried this on my rasp1 running 4.12.0-rc3 and it doesn't work. My > source is: > > // rapsi example > /dts-v1/; > /plugin/; > > /

Re: [PATCH] external references for device tree overlays

On Tue, Jun 6, 2017 at 2:17 PM, Stefani Seibold wrote: > Hi Pantelis, > > thanks for the suggestion. This feature is not very well documented. I > tried this on my rasp1 running 4.12.0-rc3 and it doesn't work. My > source is: > > // rapsi example > /dts-v1/; > /plugin/; > > / { > compatible =

Re: [xfs] 63db7c815b: XFS: Assertion failed: spin_is_locked(>b_lock), file: fs/xfs/xfs_buf.c, line: 120

> Tested-by: Libor Pechacek <lpecha...@suse.com> > > Reviewed-by: Darrick J. Wong <darrick.w...@oracle.com> > > Signed-off-by: Darrick J. Wong

Re: [xfs] 63db7c815b: XFS: Assertion failed: spin_is_locked(>b_lock), file: fs/xfs/xfs_buf.c, line: 120

; > > > a54fba8f5a xfs: Move handling of missing page into one place in > > xfs_find_get_desired_pgoff() > > 63db7c815b xfs: use ->b_state to fix buffer I/O accounting release race > > ba7b2

Re: [PATCH v4 04/23] mtd: nand: denali: avoid hard-coding ECC step, strength, bytes

On Tue, 6 Jun 2017 08:21:43 +0900 Masahiro Yamada wrote: > This driver was originally written for the Intel MRST platform with > several platform-specific parameters hard-coded. > > Currently, the ECC settings are hard-coded as follows: > > #define

Re: [PATCH v4 04/23] mtd: nand: denali: avoid hard-coding ECC step, strength, bytes

On Tue, 6 Jun 2017 08:21:43 +0900 Masahiro Yamada wrote: > This driver was originally written for the Intel MRST platform with > several platform-specific parameters hard-coded. > > Currently, the ECC settings are hard-coded as follows: > > #define ECC_SECTOR_SIZE 512 > #define ECC_8BITS

[PATCH] acpi: acpica: dsutils: fix an off-by-one index

This was detected by UBSAN. Fix it by checking whether there are any arguments prior to indexing the array. [0.222775] UBSAN: Undefined behaviour in drivers/acpi/acpica/dsutils.c:640:16 [0.222778] index -1 is out of range for type 'acpi_operand_object*[9]' [0.222781] CPU: 0 PID: 1

[PATCH] acpi: acpica: dsutils: fix an off-by-one index

This was detected by UBSAN. Fix it by checking whether there are any arguments prior to indexing the array. [0.222775] UBSAN: Undefined behaviour in drivers/acpi/acpica/dsutils.c:640:16 [0.222778] index -1 is out of range for type 'acpi_operand_object*[9]' [0.222781] CPU: 0 PID: 1

Re: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

On 05/25/2017 04:30 AM, Alexey Brodkin wrote: Hi Noam, On Thu, 2017-05-25 at 11:26 +, Noam Camus wrote: From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com] Sent: Thursday, May 25, 2017 14:15 PM diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S index

Re: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

On 05/25/2017 04:30 AM, Alexey Brodkin wrote: Hi Noam, On Thu, 2017-05-25 at 11:26 +, Noam Camus wrote: From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com] Sent: Thursday, May 25, 2017 14:15 PM diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S index

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