Hi all,
This patch set adds xxhash, zstd compression, and zstd decompression
modules. It also adds zstd support to BtrFS and SquashFS.
Each patch has relevant summaries, benchmarks, and tests.
Best,
Nick Terrell
Changelog:
v1 -> v2:
- Make pointer in lib/xxhash.c:394 non-const (1/5)
- Use div_
| From: Raj, Ashok
| Sent: Thursday, August 3, 2017 1:31 AM
|
| I don't understand this completely.. So your driver would know not to send
| RO TLP's to root complex. But you want to send RO to the NVMe device? This
| is the peer-2-peer case correct?
Yes, this is the "heavy hammer" issue which yo
Add devicetree binding documentation for the Anarion QSPI controller.
Signed-off-by: Alexandru Gagniuc
---
.../devicetree/bindings/mtd/anarion-quadspi.txt| 22 ++
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/anarion-quadspi.tx
Add support for the QSPI controller found in Adaptrum Anarion SOCs.
This controller is designed specifically to handle SPI NOR chips, and
the driver is modeled as such.
Because the system is emulated on an FPGA, we don't have a way to test
all the hardware adjustemts, so only basic features are im
On Thu, Aug 03, 2017 at 07:28:35PM -0700, Dan Williams wrote:
> After validating the state of the file as not having holes, shared
> extents, or active mappings try to commit the
> XFS_DIFLAG2_IOMAP_IMMUTABLE flag to the on-disk inode metadata. If that
> succeeds then allow the S_IOMAP_IMMUTABLE to
On 2017-08-03 20:40, Boris Brezillon wrote:
On Wed, 2 Aug 2017 18:03:05 +0530
Abhishek Sahu wrote:
All the MTD block write requests are failing with
following error messages
mkfs.ext4 /dev/mtdblock0
print_req_error: I/O error, dev mtdblock0, sector 0
Buffer I/O error on dev mtd
On Thu, Aug 03, 2017 at 07:28:23PM -0700, Dan Williams wrote:
> Provide an explicit fallocate operation type for clearing the
> S_IOMAP_IMMUTABLE flag. Like the enable case it requires CAP_IMMUTABLE
> and it can only be performed while no process has the file mapped.
>
> Cc: Jan Kara
> Cc: Jeff M
Signed-off-by: Alexandru Gagniuc
---
Changes since v1:
* Updated CPU core clock to 24 MHz to match HW changes.
arch/arc/boot/dts/adaptrum_anarion.dtsi | 108
arch/arc/boot/dts/adaptrum_anarion_fpga.dts | 49 +
2 files changed, 157 insertions(+)
cre
An ARC, the interrupts are enabled globally, rather than per-line, as
drivers request it. Thus, we need to make sure that peripherals don't
generate any before the respective drivers are probed.
The GMAC is infamous for spamming interrupts, so it must be kept in
reset until the driver is probed and
On Thu, Aug 03, 2017 at 07:28:10PM -0700, Dan Williams wrote:
> An inode with this flag set indicates that the file's block map cannot
> be changed from the currently allocated set.
>
> The implementation of toggling the flag and sealing the state of the
> extent map is saved for a later patch. Th
Adds a new driver to support the SMMU v3 PMU and add it into the
perf events framework.
Each SMMU node may have multiple PMUs associated with it, each of
which may support different events.
PMUs are named smmu_0_ where
is the physical page address of the SMMU PMCG.
For example, the SMMU PMCG at
On Tue, Aug 01, 2017 at 01:22:54AM +0300, Jarkko Sakkinen wrote:
> On Fri, Jul 28, 2017 at 03:42:18PM -0700, Greg Kroah-Hartman wrote:
> > On Wed, Jul 26, 2017 at 02:03:06PM -0600, Jason Gunthorpe wrote:
> > > On Wed, Jul 26, 2017 at 12:56:37PM -0700, Greg Kroah-Hartman wrote:
> > > > On Tue, Jul 2
Add support for the SMMU Performance Monitor Counter Group
information from ACPI. This is in preparation for its use
in the SMMU v3 PMU driver.
Signed-off-by: Neil Leeder
---
drivers/acpi/arm64/iort.c | 54 +++
include/acpi/actbl2.h | 9 +++-
This adds a driver for the SMMUv3 PMU into the perf framework.
It includes an IORT update to support PM Counter Groups.
IORT has no mechanism for determining device names so PMUs
are named based on their physical address.
Tested on Qualcomm QDF2400. perf_fuzzer ran for 4+ hours
with no failures.
Hi Arvind,
Thanks for the patch.
On 08/04/2017 08:25 AM, Arvind Yadav wrote:
> attribute_group are not supposed to change at runtime. All functions
> working with attribute_group provided by work with
> const attribute_group. So mark the non-const structs as const.
>
> Signed-off-by: Arvind Yad
On Wed, Aug 02, 2017 at 06:46:46PM +0200, Paolo Bonzini wrote:
> On 02/08/2017 18:36, Andres Oportus wrote:
> > +Paolo Bonzini
> >
> > On Mon, Jul 31, 2017 at 9:18 PM, Andres Oportus
> > mailto:andresopor...@android.com>> wrote:
> >
> > commit 3d89e5478bf550a50c99e93adf659369798263b0 upstream
On Fri, Aug 4, 2017 at 12:46 PM, Darrick J. Wong
wrote:
> On Thu, Aug 03, 2017 at 07:28:17PM -0700, Dan Williams wrote:
>> >From falloc.h:
>>
>> FALLOC_FL_SEAL_BLOCK_MAP is used to seal (make immutable) all of the
>> file logical-to-physical extent offset mappings in the file. The
>> p
On Sun, Jul 30, 2017 at 11:48:39PM +0800, Leo Yan wrote:
> Hi Willy,
>
> On Fri, Jul 28, 2017 at 11:47:52PM +0200, Willy Tarreau wrote:
> > On Fri, Jul 28, 2017 at 02:52:15PM +0800, Leo Yan wrote:
> > > On Fri, Jul 28, 2017 at 06:25:55AM +0200, Willy Tarreau wrote:
> > > > Hi Leo,
> > > >
> > > >
On Thu, Aug 03, 2017 at 07:28:17PM -0700, Dan Williams wrote:
> >From falloc.h:
>
> FALLOC_FL_SEAL_BLOCK_MAP is used to seal (make immutable) all of the
> file logical-to-physical extent offset mappings in the file. The
> purpose is to allow an application to assume that there are no h
Hi David,
On Friday 04 Aug 2017 10:51:37 David Lechner wrote:
> On 08/04/2017 09:54 AM, Laurent Pinchart wrote:
> > On Thursday 03 Aug 2017 17:33:47 David Lechner wrote:
> >> This adds a new binding for Sitronix ST7586 display panels.
> >>
> >> Using lego as the vendor prefix in the compatible st
On 08/04/2017 07:36 AM, Juergen Gross wrote:
> There are some Xen specific trace functions defined in
> include/trace/events/xen.h. Remove them.
>
> Signed-off-by: Juergen Gross
(Again, adding Ingo and Steven)
Reviewed-by: Boris Ostrovsky
although I think "s/some Xen/some unused Xen/" in the c
On Fri, Aug 04, 2017 at 03:31:42PM +0100, Sudeep Holla wrote:
> Create a driver to add support for SoC sensors exported by the System
> Control Processor (SCP) via the System Control and Management Interface
> (SCMI). The supported sensor types is one of voltage, temperature,
> current, and power.
On 08/04/2017 12:07 PM, r...@redhat.com wrote:
> MPX only seems to be available on 64 bit CPUs, starting with Skylake
> and Goldmont. Move VM_MPX into the 64 bit only portion of vma->vm_flags,
> in order to free up a VMA flag.
Makes me a little sad. But, seems worth it.
Acked-by: Dave Hansen
On 08/04/2017 07:36 AM, Juergen Gross wrote:
> The function xen_set_domain_pte() is used nowhere in the kernel.
> Remove it.
>
> Signed-off-by: Juergen Gross
Reviewed-by: Boris Ostrovsky
(+ Ingo and Steven who are maintainers of include/trace/events/xen.h)
> ---
> arch/x86/include/asm/xen/pag
On 08/04/2017 07:36 AM, Juergen Gross wrote:
> Remove the last tests for XENFEAT_auto_translated_physmap in pure
> PV-domain specific paths. PVH V1 is gone and the feature will always
> be "false" in PV guests.
>
> Signed-off-by: Juergen Gross
Reviewed-by: Boris Ostrovsky
I wonder whether the r
[resend because half the recipients got dropped due to IPv6 firewall issues]
Introduce MADV_WIPEONFORK semantics, which result in a VMA being
empty in the child process after fork. This differs from MADV_DONTFORK
in one important way.
If a child process accesses memory that was MADV_WIPEONFORK, i
From: Rik van Riel
Introduce MADV_WIPEONFORK semantics, which result in a VMA being
empty in the child process after fork. This differs from MADV_DONTFORK
in one important way.
If a child process accesses memory that was MADV_WIPEONFORK, it
will get zeroes. The address ranges are still valid, th
From: Rik van Riel
MPX only seems to be available on 64 bit CPUs, starting with Skylake
and Goldmont. Move VM_MPX into the 64 bit only portion of vma->vm_flags,
in order to free up a VMA flag.
Signed-off-by: Rik van Riel
---
arch/x86/Kconfig | 4 +++-
include/linux/mm.h | 8 ++--
2 files
Hi Thomas,
On 08/04/2017 08:40 AM, Thomas Richter wrote:
Commit 18f3d6be6be1 ("selftests/bpf: Add test cases to test narrower ctx field
loads")
introduced new eBPF test cases. One of them (test_pkt_md_access.c)
fails on s390x. The BPF verifier error message is:
Could you submit the fix to: ne
From: Rik van Riel
Introduce MADV_WIPEONFORK semantics, which result in a VMA being
empty in the child process after fork. This differs from MADV_DONTFORK
in one important way.
If a child process accesses memory that was MADV_WIPEONFORK, it
will get zeroes. The address ranges are still valid, th
From: Rik van Riel
MPX only seems to be available on 64 bit CPUs, starting with Skylake
and Goldmont. Move VM_MPX into the 64 bit only portion of vma->vm_flags,
in order to free up a VMA flag.
Signed-off-by: Rik van Riel
---
arch/x86/Kconfig | 4 +++-
include/linux/mm.h | 8 ++--
2 files
Introduce MADV_WIPEONFORK semantics, which result in a VMA being
empty in the child process after fork. This differs from MADV_DONTFORK
in one important way.
If a child process accesses memory that was MADV_WIPEONFORK, it
will get zeroes. The address ranges are still valid, they are just empty
On Wed, 2017-08-02 at 14:17 -0700, Andrew Morton wrote:
> On Wed, 2 Aug 2017 13:44:57 -0400 Jonathan Toppins com> wrote:
>
> > The RDMA subsystem can generate several thousand of these messages
> > per
> > second eventually leading to a kernel crash. Ratelimit these
> > messages
> > to prevent t
On 08/04/2017 08:33 PM, Joel Fernandes wrote:
On Fri, Aug 4, 2017 at 6:58 AM, Daniel Borkmann wrote:
On 08/04/2017 07:46 AM, Joel Fernandes wrote:
When cross-compiling the bpf sample map_perf_test for aarch64, I find that
__NR_getpgrp is undefined. This causes build errors. Fix it by allowing
On Fri, Aug 4, 2017 at 6:58 AM, Daniel Borkmann wrote:
> On 08/04/2017 07:46 AM, Joel Fernandes wrote:
>>
>> When cross-compiling the bpf sample map_perf_test for aarch64, I find that
>> __NR_getpgrp is undefined. This causes build errors. Fix it by allowing
>> the
>> deprecated syscall in the sam
From: Kevin Brodsky
Make it possible to disable the kuser helpers by adding a KUSER_HELPERS
config option (enabled by default). When disabled, all kuser
helpers-related code is removed from the kernel and no mapping is done
at the fixed high address (0x); any attempt to use a kuser
helper
From: Kevin Brodsky
AArch32 processes are currently installed a special [vectors] page that
contains the sigreturn trampolines and the kuser helpers, at the fixed
address mandated by the kuser helpers ABI.
Having both functionalities in the same page has become problematic,
because:
* It makes
Hi Linus,
Here are some more arm64 fixes for 4.13. The main one is the PTE race
with the hardware walker, but there are a couple of other things too.
Please pull,
Will
--->8
The following changes since commit 16f73eb02d7e1765ccab3d2018e0bd98eb93d973:
Linux 4.13-rc3 (2017-07-30 12:40:36 -070
From: Thomas Bogendoerfer
Date: Thu, 3 Aug 2017 15:43:14 +0200
> From: Thomas Bogendoerfer
>
> Even the driver doesn't do anything with the clk source for SGMII
> ports it needs to be enabled by doing a devm_clk_get(), if there is
> a clk source in DT.
>
> Fixes: 0db01097cabd ('xgene: Don't fa
On Fri, Aug 4, 2017 at 11:21 AM, Ross Zwisler
wrote:
> On Fri, Aug 04, 2017 at 11:01:08AM -0700, Dan Williams wrote:
>> [ adding Dave who is working on a blk-mq + dma offload version of the
>> pmem driver ]
>>
>> On Fri, Aug 4, 2017 at 1:17 AM, Minchan Kim wrote:
>> > On Fri, Aug 04, 2017 at 12:5
From: Daniel Borkmann
Date: Fri, 04 Aug 2017 15:05:19 +0200
> On 08/04/2017 02:10 AM, David Daney wrote:
>> Inexplicably, commit f381bf6d82f0 ("MIPS: Add support for eBPF JIT.")
>> lost a file somewhere on its path to Linus' tree. Add back the
>> missing ebpf_jit.c so that we can build with CONF
On Fri, Aug 04, 2017 at 11:01:08AM -0700, Dan Williams wrote:
> [ adding Dave who is working on a blk-mq + dma offload version of the
> pmem driver ]
>
> On Fri, Aug 4, 2017 at 1:17 AM, Minchan Kim wrote:
> > On Fri, Aug 04, 2017 at 12:54:41PM +0900, Minchan Kim wrote:
> [..]
> >> Thanks for the
On 07/24/2017 04:52 PM, Victor Aoqui wrote:
> Implemented default hugepage size verification (default_hugepagesz=)
> in order to allow allocation of defined number of pages (hugepages=)
> only for supported hugepage sizes.
>
> Signed-off-by: Victor Aoqui
> ---
> v2:
>
> - Renamed default_hugepag
On 2017/08/04 12:59PM, Peter Zijlstra wrote:
> On Tue, Aug 01, 2017 at 08:14:04PM +0530, Naveen N. Rao wrote:
> > @@ -5974,19 +5976,8 @@ void perf_output_sample(struct perf_output_handle
> > *handle,
> > }
> > }
> >
> > + if (!event->attr.count_sb_events)
> > + rb_han
Changing the card voltage on the cc is not instantaneous, especially
when switching from 3.3v to 1.8v.
It take at least 30ms for the regulator to go from 3.3v to 1.8v. Add
margin to that to make sure we don't upset the sdcard during the voltage
switch
Fixes: 61ff2af9b278 ("ARM64: dts: fixup libre
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
index 6b7495dc6014..5d59fd75ca
It does not make much sense to define cap-sd-highspeed in the emmc nodes
Just remove it.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi| 1 -
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 1 -
arch/arm64/boot/dts/amlogic/meson-
Add the pinctrl to switch mmc clk pins in gpio (pulled down) mode. This
is necessary to be able to gate the clk outside of the SoC while
keeping it running in the controller
Signed-off-by: Jerome Brunet
---
.../arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 9 --
.../boot/dts/amlogic/meso
The patchset feature update around mmc. It is linked to this series [0]
but does not strictly depends on it. It adds:
* The regulator settling times for the gpio regulator of nanopi-k2 and
the libretech-cc.
* UHS modes for the p20x and nanopi-k2. SDR104 is left out because the
p20x does not su
Changing the card voltage on the nanopi-k2 is not instantaneous,
especially when switching from 3.3v to 1.8v.
It take at least 3ms for the regulator to go from 3.3v to 1.8v. Add
margin to that to make sure we don't upset the sdcard during the voltage
switch
Fixes: 9bc7ffb08daf ("arm64: dts: amlog
Enable sdcard Ultra High Speed mode on the p20x. While the s905 should
support sdr104, the pcb of the p200 does not and is limited to an sdcard
clock rate of 100Mhz (SDR50)
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 3 +++
1 file changed, 3 insertions(+)
Distributions may wish to provide kernels that permit loading of
unsigned modules based on certain policy decisions. Right now that
results in the kernel being tainted whenever an unsigned module is
loaded, which may not be desirable. Add a config option to disable that.
Signed-off-by: Matthew Gar
From: Yunsheng Lin
Date: Fri, 4 Aug 2017 17:24:59 +0800
> This patch fixes the __udivdi3 undefined error reported by
> test robot.
>
> Fixes: b8c17f708831 ("net: hns: Add self-adaptive interrupt coalesce support
> in hns driver")
> Signed-off-by: Yunsheng Lin
Applied, thank you.
On Thu, Aug 3, 2017 at 4:25 PM, Linus Torvalds
wrote:
> On Thu, Aug 3, 2017 at 4:11 PM, Andrew Morton
> wrote:
>>
>> Where is this INIT_LIST_HEAD()?
>
> I think it's this one:
>
> list_del_init(&info->shrinklist);
>
> in shmem_unused_huge_shrink().
Yes, this is correct. Sorry about con
Den 04.08.2017 18.51, skrev David Lechner:
On 08/04/2017 04:48 AM, Noralf Trønnes wrote:
Den 04.08.2017 00.33, skrev David Lechner:
This adds a new binding for Sitronix ST7586 display panels.
Using lego as the vendor prefix in the compatible string because the
display
panel I am working wi
[ adding Dave who is working on a blk-mq + dma offload version of the
pmem driver ]
On Fri, Aug 4, 2017 at 1:17 AM, Minchan Kim wrote:
> On Fri, Aug 04, 2017 at 12:54:41PM +0900, Minchan Kim wrote:
[..]
>> Thanks for the testing. Your testing number is within noise level?
>>
>> I cannot understan
On Thu, Aug 3, 2017 at 4:53 PM, Andrew Morton wrote:
> On Thu, 3 Aug 2017 16:25:46 -0700 Linus Torvalds
> wrote:
>
>> On Thu, Aug 3, 2017 at 4:11 PM, Andrew Morton
>> wrote:
>> >
>> > Where is this INIT_LIST_HEAD()?
>>
>> I think it's this one:
>>
>> list_del_init(&info->shrinklist);
>
David Hildenbrand writes:
...
>> v1:
>> https://lkml.org/lkml/2017/6/29/958
>>
>> Bandan Das (3):
>> KVM: vmx: Enable VMFUNCs
>> KVM: nVMX: Enable VMFUNC for the L1 hypervisor
>> KVM: nVMX: Emulate EPTP switching for the L1 hypervisor
>>
>> arch/x86/include/asm/vmx.h | 9 +++
>> arch/x
On 04.08.2017 18:31, Helge Deller wrote:
> In addition there is a conflict with some the common/generic MADV_* constants
> between kernel headers and glibc headers.
Please ignore this patch.
I was wrong: kernel and glibc are in sync.
Nevertheless, maybe adjusting the parisc values to the defaul
Declare snd_akm4xxx structures as const as they are only passed
to the function snd_ice1712_akm4xxx_init. This argument is of type
const, so make the structures const.
Done using Coccinelle:
@match disable optional_qualifier@
identifier s;
position p;
@@
static struct snd_akm4xxx s@p={...};
@goo
CCF generic mux will shift the mask using the value defined in shift
Define the mask accordingly
Signed-off-by: Jerome Brunet
---
drivers/mmc/host/meson-gx-mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
On Fri, Aug 04, 2017 at 10:44:31AM -0700, Junio C Hamano wrote:
> Linus Torvalds writes:
>
> > On Wed, Aug 2, 2017 at 5:28 PM, Stephen Rothwell
> > wrote:
> >>
> >> I would say that if you rebase someone's commit(s), then you are on the
> >> "patch's delivery path" and so should add a Signed-of
Remove useless clock rate defines. These should not be defined but
equested from the clock framework.
Also correct typo on the DELAY register
Signed-off-by: Jerome Brunet
---
drivers/mmc/host/meson-gx-mmc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/mmc/host/
The patchset features several bugfixes, rework and upgrade for the
meson-gx MMC driver.
The main goal is to improve readability and enable new high speed
modes, such as eMMC DDR52 and sdcard UHS modes up to SDR50 (100Mhz)
While full speed SDR104 is stable with most cards, a few seems to
require a
spinlock used in interrupt handler should use the _irqsave variant
Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms")
Signed-off-by: Jerome Brunet
---
drivers/mmc/host/meson-gx-mmc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/meson
Remove conditional write of cfg register. Warn if set_clk fails for some
reason. Consistently use host->dev instead of mixing with mmc_dev(mmc)
Signed-off-by: Jerome Brunet
---
drivers/mmc/host/meson-gx-mmc.c | 22 +-
1 file changed, 9 insertions(+), 13 deletions(-)
diff --g
In DDR modes, meson mmc controller requires an input rate twice as fast
as the output rate
Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms")
Signed-off-by: Jerome Brunet
---
drivers/mmc/host/meson-gx-mmc.c | 41 +
1 file changed, 29 inse
Rework tuning function of the rx phase, with the addition of rx delay.
This allow a more fine setting of the rx phase, which allows to use
new modes such as SDR50.
Also, use 270 degree Tx phase as it make eMMC DDR52 mode functional on
the libretech-cc, without any regression so far.
Signed-off-by
Clean-up clk_set function to prepare the next changes (DDR and clk-stop)
Signed-off-by: Jerome Brunet
---
drivers/mmc/host/meson-gx-mmc.c | 30 +-
1 file changed, 9 insertions(+), 21 deletions(-)
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-g
It seems that the signal clock is also used and required, somehow, by
the controller it self.
It is shown during init, when writing to CFG while the divider is set
to 0 will crash the SoC. During voltage switch, the controller may crash
and the card may then fail to exit busy state if the clock is
Implement voltage switch callback (shamelessly copied from sunxi mmc
driver). This allow, with the appropriate tuning function, to use
SD ultra high speed modes.
Signed-off-by: Jerome Brunet
---
drivers/mmc/host/meson-gx-mmc.c | 25 +
1 file changed, 25 insertions(+)
dif
Perform basic initialisation of the clk register before providing it to
the CCF.
Thanks to devm, carrying the clock structure around after init is not
necessary. Rework the function to remove these from the controller host
data.
Finally, set initial mmc clock rate before enabling it, simplifying
Linus Torvalds writes:
> On Wed, Aug 2, 2017 at 5:28 PM, Stephen Rothwell
> wrote:
>>
>> I would say that if you rebase someone's commit(s), then you are on the
>> "patch's delivery path" and so should add a Signed-off-by tag.
>
> Yeah, I agree. Rebasing really is pretty much the exact same thi
No functional change, just improve interrupt handler readability
Signed-off-by: Jerome Brunet
---
drivers/mmc/host/meson-gx-mmc.c | 93 +
1 file changed, 39 insertions(+), 54 deletions(-)
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/mes
cfg init function overwrite values set in the clk init function
Remove the cfg pokes from the clk init. Actually, trying to use
the CLK_AUTO, like initially tried in clk_init, would break
the card initialization
BEWARE not to poke the cfg register while the divider value in clk
register is 0. It c
The card_busy callback is important to then add the voltage switch
callback as it allow to verify that the card is done dealing with
the voltage switch
Signed-off-by: Jerome Brunet
---
drivers/mmc/host/meson-gx-mmc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/mmc/
Remove CLK_DIVIDER_ALLOW_ZERO. This flag means that a 1 based divider
with a 0 value will behave as a bypass clock
The mmc divider does not behave like this, a 0 value disables the clock
Remove this flag so CCF never allows a 0 value on this clock
Fixes: 51c5d8447bd7 ("MMC: meson: initial support
On Fri, 2017-08-04 at 10:11 -0700, Eric Dumazet wrote:
> You could add a debug version of u64_stats_update_begin()
>
> doing
>
> int ret = atomic_inc((atomic_t *)syncp);
I meant atomic_inc_return() of course.
>
> BUG_ON(ret & 1);
>
>
> And u64_stats_update_end()
>
> int ret = atomic_inc((
Dear RT folks!
I'm pleased to announce the v4.11.12-rt9 patch set.
Changes since v4.11.12-rt8:
- CPU hotplug could be rock solid now. Yes. The rewrite of the hotplug
related parts for RT including rwlock's implementation over the last
few weeks looks good. 'good' means that Steven's C
Hi Rafael,
On 27/07/17 20:33, Dietmar Eggemann wrote:
[...]
> Patch high level description:
>
>[ 01/10] Fix to free cpumask cpus_to_visit
>[ 02/10] Default (empty, weak) arch_set_freq_scale() implementation
>[03,04/10] Call arch_set_freq_scale() from two cpufreq drivers
>
On Wed, Aug 02, 2017 at 08:29:40PM +0300, Yury Norov wrote:
> On Wed, Aug 02, 2017 at 05:39:01PM +0100, Catalin Marinas wrote:
> > On Mon, Jul 31, 2017 at 05:48:25PM +0300, Yury Norov wrote:
> > > In patch 06beb72fbe23e ("arm64: introduce mm context flag to keep 32 bit
> > > task
> > > information
Hi Laurent,
Den 04.08.2017 16.54, skrev Laurent Pinchart:
Hi David,
Thank you for the patch.
On Thursday 03 Aug 2017 17:33:47 David Lechner wrote:
This adds a new binding for Sitronix ST7586 display panels.
Using lego as the vendor prefix in the compatible string because the display
panel I
Hi Peter,
On 2017/08/04 12:20PM, Peter Zijlstra wrote:
> On Tue, Aug 01, 2017 at 08:14:03PM +0530, Naveen N. Rao wrote:
> > Add a new option 'signal_on_wakeup' to request for a signal to be
> > delivered on ring buffer wakeup controlled through watermark and
> > {wakeup_events, wakeup_watermark}.
On Fri, Aug 04, 2017 at 12:00:06PM -0500, Mario Limonciello wrote:
> This fixes a problem where the system gets stuck in a loop
> unable to wakeup via power button in s2idle.
>
> The problem happens because:
> - press power button:
>- system emits 0xc0 (power press), event ignored
>- syst
From: Kevin Brodsky
Commit a1d5ebaf8ccd ("arm64: big-endian: don't treat code as data when
copying sigret code") moved the 32-bit sigreturn trampoline code from
the aarch32_sigret_code array to kuser32.S. The commit removed the
array definition from signal32.c, but not its declaration in
signal32
On Fri, Aug 4, 2017 at 3:56 AM, Michal Hocko wrote:
> On Thu 03-08-17 14:17:26, Paul Moore wrote:
>> On Thu, Aug 3, 2017 at 7:05 AM, Michal Hocko wrote:
>> > On Thu 03-08-17 19:44:46, Tetsuo Handa wrote:
> [...]
>> >> When allocating thread is selected as an OOM victim, it gets TIF_MEMDIE.
>> >>
On Fri, 2017-08-04 at 08:51 -0700, Florian Fainelli wrote:
> On 08/03/2017 10:36 PM, Eric Dumazet wrote:
> > On Thu, 2017-08-03 at 21:33 -0700, Florian Fainelli wrote:
> >> During testing with a background iperf pushing 1Gbit/sec worth of
> >> traffic and having both ifconfig and ethtool collect st
Please pull to get these Sparc bug fixes:
1) Block interrupts properly across the entire MMU context change
(both the hw MMU context change and the TSB table change) so
that we don't get a perf event interrupt in the middle. From
Rob Gardner.
2) Be sure to register hugepages early enou
Hi Franklin,
On 8/2/2017 1:18 PM, Franklin S Cooper Jr wrote:
Add D CAN nodes to 66AK2G based SoC dtsi.
Franklin S Cooper Jr (2):
dt-bindings: net: c_can: Update binding for clock and power-domains
property
ARM: configs: keystone: Enable D_CAN driver
Lokesh Vutla (1):
ARM: dts: k
On 03/08/17 06:35, Vivek Gautam wrote:
> Hi Robin,
>
>
>
> On 08/02/2017 05:47 PM, Robin Murphy wrote:
>> On 02/08/17 10:53, Vivek Gautam wrote:
>>> We don't want to touch the TLB when smmu is suspended.
>>> Defer it until resume.
>>>
>>> Signed-off-by: Vivek Gautam
>>> ---
>>>
>>> Hi all,
>>>
> -Original Message-
> From: Rafael J. Wysocki [mailto:r...@rjwysocki.net]
> Sent: Monday, July 31, 2017 4:43 PM
> To: Linux ACPI
> Cc: LKML ; Len Brown ;
> Linux PM ; Srinivas Pandruvada
> ; Limonciello, Mario
>
> Subject: [PATCH] ACPI / PM: Prefer suspend-to-idle over S3 on some systems
On Fri, Aug 04, 2017 at 12:34:22PM +0530, Gautham R. Shenoy wrote:
> From: "Gautham R. Shenoy"
>
> Currently, we use the opal call opal_slw_set_reg() to inform the
> Sleep-Winkle Engine (SLW) to restore the contents of some of the
> Hypervisor state on wakeup from deep idle states that lose full
This fixes a problem where the system gets stuck in a loop
unable to wakeup via power button in s2idle.
The problem happens because:
- press power button:
- system emits 0xc0 (power press), event ignored
- system emits 0xc1 (power release), event processed,
emited as KEY_POWER
- set
The latest feature release Git v2.14.0 is now available at the
usual places. It is comprised of 727 non-merge commits since
v2.13.0, contributed by 66 people, 18 of which are new faces.
The tarballs are found at:
https://www.kernel.org/pub/software/scm/git/
when kernel.org mirrors catch up.
On 08/03/2017 12:17 PM, SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Thu, 3 Aug 2017 20:34:00 +0200
>
> The local variable "rc" will eventually be set only to an error code.
> Thus omit the explicit initialisation at the beginning.
>
> Signed-off-by: Markus Elfring
> ---
> arch/powe
On 08/04/2017 04:48 AM, Noralf Trønnes wrote:
Den 04.08.2017 00.33, skrev David Lechner:
This adds a new binding for Sitronix ST7586 display panels.
Using lego as the vendor prefix in the compatible string because the
display
panel I am working with is an integral part of the LEGO MINDSTORMS
Michal Hocko wrote:
> And that's why we still see the corruption. That, however, means that
> the MMF_UNSTABLE implementation has to be more complex and we have to
> hook into all anonymous memory fault paths which I hoped I could avoid
> previously.
I don't understand mm internals including pte/p
From: Mikael Pettersson
Date: Fri, 4 Aug 2017 10:02:25 +0200
> David Miller writes:
> > From: Mikael Pettersson
> > Date: Thu, 3 Aug 2017 22:02:57 +0200
> >
> > > With that in place the kernel booted fine.
> > > When I then ran the `poll' strace test binary, the OOPS was replaced by:
> >
On 08/03/2017 06:18 PM, Prarit Bhargava wrote:
+ /*
+* Only allow enabling and disabling of the current printk_time
+* setting. Changing it from one setting to another confuses
+* userspace.
+*/
We should allow a debug option to permit this (but that can be
When a PCI device has DMA quirks, we need to ensure that an upstream
IOMMU knows about all possible aliases, since the presence of a DMA
quirk does not preclude the device still also emitting transactions
(e.g. MSIs) on its 'real' RID. Similarly, the rules for bridge aliasing
are relatively complex
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