Re: [PATCH v2 1/5] KVM: x86: Add return value to kvm_cpuid().

On 17/08/2017 21:52, Yu Zhang wrote: > diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h > index ac15193..3e759cf 100644 > --- a/arch/x86/kvm/cpuid.h > +++ b/arch/x86/kvm/cpuid.h > @@ -21,7 +21,14 @@ int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, > int kvm_vcpu_ioctl_get_cpuid2(struct

[PATCH V6 17/21] net-next/hinic: Add cmdq completion handler

Add cmdq completion handler for getting a notification about the completion of cmdq commands. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c | 297 +- drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h | 12 + 2 f

[PATCH V6 16/21] net-next/hinic: Add cmdq commands

Add cmdq commands for setting queue pair contexts in the nic. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_common.c | 25 ++ drivers/net/ethernet/huawei/hinic/hinic_common.h | 9 + drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c | 282

[PATCH V6 19/21] net-next/hinic: Add Tx operation

Add transmit operation for sending data by qp operations. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_dev.h| 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c | 47 +++ drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h | 22 ++ d

[PATCH V6 18/21] net-next/hinic: Add Rx handler

Set the io resources in the nic and handle rx events by qp operations. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_dev.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_csr.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.

[PATCH V6 21/21] net-next/hinic: Add netpoll

Add more netdev operation - netpoll. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- MAINTAINERS| 7 +++ drivers/net/ethernet/huawei/hinic/hinic_main.c | 20 2 files changed, 27 insertions(+) diff --git a/MAINTAINERS b/MA

[PATCH V6 15/21] net-next/hinic: Add ceqs

Initialize the completion event queues and handle ceq events by calling the registered handlers. Used for cmdq command completion. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c | 16 ++ drivers/net/ethernet/huawei/hinic/hinic_hw_cs

[PATCH V6 20/21] net-next/hinic: Add ethtool and stats

Add ethtool operations and statistics operations. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_dev.h | 3 + drivers/net/ethernet/huawei/hinic/hinic_main.c | 218 - drivers/net/ethernet/huawei/hinic/hinic_port.c |

[PATCH V6 14/21] net-next/hinic: Initialize cmdq

Create the work queues for cmdq and update the nic about the work queue contexts. cmdq commands are used for updating the nic about the qp contexts. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c | 282 +- drivers

[PATCH V6 08/21] net-next/hinic: Add port management commands

Add the port management commands that are sent as management messages. The port management commands are used for netdev operations. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/Makefile | 4 +- drivers/net/ethernet/huawei/hinic/hinic_dev.h

[PATCH V6 01/21] net-next/hinic: Initialize hw interface

Initialize hw interface as part of the nic initialization for accessing hw. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- Documentation/networking/hinic.txt | 125 ++ drivers/net/ethernet/Kconfig | 1 + drivers/net/ethernet/Makefile

[PATCH V6 02/21] net-next/hinic: Initialize hw device components

Initialize hw device by calling the initialization functions of aeqs and management channel. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/Makefile| 3 +- drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c | 172 -- dri

Re: [Nouveau] [PATCH] drm/nouveau: remove redundant null check on array mstm->msto

On 17 August 2017 at 11:37, Colin King wrote: > From: Colin Ian King > > The check to see if mstm->msto is null is redundant because it is > an array and hence can never be null. Remove the redundant check. > > Detected by CoverityScan, CID#1375915 ("Array compared against 0") > > Signed-off-by:

Re: [v5 4/4] mm, oom, docs: describe the cgroup-aware OOM killer

Hi David! Please, find an updated version of docs patch below. Thanks! Roman -- >From 97805b3dcccb9420d2c4380e88e202164ead0e45 Mon Sep 17 00:00:00 2001 From: Roman Gushchin Date: Fri, 2 Jun 2017 11:29:14 +0100 Subject: [PATCH 4/4] mm, oom, docs: describe the cgroup-aware OOM killer Update cg

[PATCH] staginig: pi433: replace INVALID_PARAM macro with inline code

The following macro: \#define INVALID_PARAM { \ dev_dbg(&spi->dev, "set: illegal input param"); \ return -EINVAL; \ } affects control flow by having return statement. This is against Linux Kernel Coding Style and should be avoided and therefore this m

Re: [PATCH v1 4/4] KVM: MMU: Expose the LA57 feature to VM.

On 8/17/2017 7:57 PM, Paolo Bonzini wrote: On 12/08/2017 15:35, Yu Zhang wrote: index a98b88a..50107ae 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -694,7 +694,7 @@ static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, switch (mode) { cas

Re: [PATCH] kvm: x86: disable KVM_FAST_MMIO_BUS

On 17/08/2017 11:00, Paolo Bonzini wrote: > On 17/08/2017 00:31, Michael S. Tsirkin wrote: >> On Wed, Aug 16, 2017 at 11:25:35PM +0200, Paolo Bonzini wrote: >>> Yes, I agree. EMULTYPE_SKIP is fine because failed decoding still >>> causes an exception to be injected. Maybe it's better to gate the

RE: [PATCH RFC] fpga: add FPGA Bus device framework

> On Mon, Aug 14, 2017 at 5:59 AM, Wu, Hao wrote: > >> On Tue, Aug 8, 2017 at 1:25 PM, Wu, Hao wrote: > >> >> On Thu, Aug 3, 2017 at 2:53 AM, Wu Hao wrote: > >> >> > On Wed, Aug 02, 2017 at 04:16:32PM -0500, Alan Tull wrote: > >> >> >> On Wed, Aug 2, 2017 at 7:19 AM, Wu Hao wrote: > >> >> >> >

[PATCH v5 01/16] mtd: nand: qcom: DMA mapping support for register read buffer

The EBI2 NAND controller directly remaps register read buffer with dma_map_sg and DMA address of this buffer will be passed to DMA API’s. While, on QPIC NAND controller, which uses BAM DMA, we read the controller registers by preparing a BAM command descriptor. This command descriptor requires the

[PATCH v5 02/16] mtd: nand: qcom: allocate BAM transaction

- The BAM transaction is the core data structure which will be used for all the data transfers in QPIC NAND. Since the core framework in nand_base.c is serializing all the NAND requests so allocating BAM transaction before every transfer will be overhead. The memory for it be allocated duri

Re: Race between release_tty() and vt_disallocate()

> It seems that part of the problem is the lack of tty_port_put/tty_port_get > calls in the VT code. Yes > > The only easy way I can think to keep the current semantics would instead > > be to keep the tty port resources around and indexed somewhere but > > blackhole input to/output from that po

[PATCH v5 05/16] mtd: nand: qcom: support for read location registers

In EBI2, all codeword data will be read in FLASH_BUF_ACC buffer and ADM will copy the data from source (FLASH_BUF_ACC) to destination (memory for data read). In QPIC, there is no FLASH_BUF_ACC and all the codeword data will held in QPIC BAM FIFO buffers. It provides multiple READ_LOCATION register

Re: [RFC PATCH] media: vb2: add bidirectional flag in vb2_queue

Hi Laurent, On 08/16/2017 03:28 PM, Laurent Pinchart wrote: > Hi Stan, > > On Wednesday 16 Aug 2017 14:46:50 Stanimir Varbanov wrote: >> On 08/15/2017 01:04 PM, Hans Verkuil wrote: >>> On 08/14/17 10:41, Stanimir Varbanov wrote: Hi, This RFC patch is intended to give to the drivers

[PATCH v5 04/16] mtd: nand: qcom: support for passing flags in DMA helper functions

The QPIC NAND BAM has multiple flags to control the transfer. This patch adds flags parameter in register and data transfer DMA helper functions and modifies all these functions call with appropriate flags using following rule 1. Read and write can’t go in single command descriptor so separate

[PATCH v5 09/16] mtd: nand: qcom: support for different DEV_CMD register offsets

The FLASH_DEV_CMD registers starting offset is not same in different QPIC NAND controller versions. This patch adds the starting offset in NAND controller properties and uses the same for calculating the actual offset of these registers. Reviewed-by: Archit Taneja Signed-off-by: Abhishek Sahu --

[PATCH v5 08/16] mtd: nand: qcom: QPIC data descriptors handling

1. Add the data descriptor preparation function which will be used only by BAM DMA for forming the data SGL’s 2. Add clear BAM transaction and call it before every new request 3. Check DMA mode for ADM or BAM and call the appropriate descriptor formation function. Reviewed-by: Archit Taneja

[PATCH v5 10/16] mtd: nand: qcom: add command elements in BAM transaction

All the QPIC register read/write through BAM DMA requires command descriptor which contains the array of command elements. Reviewed-by: Archit Taneja Signed-off-by: Abhishek Sahu --- * Changes from v4: None * BUILD DEPENDENCY: This PATCH has build dependency over following BAM command descr

[PATCH v5 15/16] mtd: nand: qcom: support for IPQ4019 QPIC NAND controller

Add the compatible string for IPQ4019 QPIC NAND controller version 1.4.0 which uses BAM DMA. Reviewed-by: Archit Taneja Signed-off-by: Abhishek Sahu --- * Changes from v4: None drivers/mtd/nand/qcom_nandc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/mtd/nand/qcom_

Re: [PATCH 3/3] cgroup: Implement cgroup2 basic CPU usage accounting

Hi Tejun! On Fri, Aug 11, 2017 at 09:37:54AM -0700, Tejun Heo wrote: > In cgroup1, while cpuacct isn't actually controlling any resources, it > is a separate controller due to combinaton of two factors - s/combinaton/combination > @@ -4466,6 +4470,8 @@ static void css_free_work_fn(struct work_st

[PATCH v5 12/16] dt-bindings: qcom_nandc: fix the ipq806x device tree example

1. Correct the compatible string for IPQ806x 2. Change the NAND controller and NAND chip nodes name for more clarity. Acked-by: Rob Herring Signed-off-by: Abhishek Sahu --- * Changes from v4: None Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 6 +++--- 1 file changed, 3 insertions

[PATCH v5 16/16] mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller

Add the compatible string for IPQ8074 QPIC NAND controller version 1.5.0 which uses BAM DMA and its FLASH_DEV_CMD registers starting offset is 0x7000. Reviewed-by: Archit Taneja Signed-off-by: Abhishek Sahu --- * Changes from v4: None drivers/mtd/nand/qcom_nandc.c | 10 ++ 1 file chan

[PATCH v5 11/16] mtd: nand: qcom: support for command descriptor formation

1. Add the function for command descriptor preparation which will be used only by BAM DMA and it will form the DMA descriptors containing command elements 2. DMA_PREP_CMD flag should be used for forming command DMA descriptors Reviewed-by: Archit Taneja Signed-off-by: Abhishek Sahu ---

[PATCH v5 14/16] dt-bindings: qcom_nandc: IPQ8074 QPIC NAND documentation

Qualcom IPQ8074 SoC uses QPIC NAND controller version 1.5.0 which uses BAM DMA Engine. Signed-off-by: Abhishek Sahu --- * Changes from v4: None Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/qcom_

[PATCH v5 13/16] dt-bindings: qcom_nandc: IPQ4019 QPIC NAND documentation

1. Qualcom IPQ4019 SoC uses QPIC NAND controller version 1.4.0 which uses BAM DMA Engine while IPQ806x uses EBI2 NAND which uses ADM DMA Engine. 2. QPIC NAND will 3 BAM channels: command, data tx and data rx while EBI2 NAND uses only single ADM channel. 3. CRCI is only required for ADM DMA

[PATCH v5 06/16] mtd: nand: qcom: erased codeword detection configuration

The NAND controller returns ECC failure during read of completely erased codeword. The NAND controller has hardware functionality to detect erased codeword in case of BCH ECC algorithm. The NAND_ERASED_CW_DETECT_CFG register controls the erased codeword/page detection controller. This register shou

[PATCH v5 07/16] mtd: nand: qcom: enable BAM or ADM mode

1. DM_EN is only required for EBI2 NAND controller which uses ADM 2. BAM mode will be disabled after power on reset which needs to be enabled before starting any BAM transfers. Reviewed-by: Archit Taneja Signed-off-by: Abhishek Sahu --- * Changes from v4: None drivers/mtd/nand/qcom_nandc.c

[PATCH v5 00/16] Add QCOM QPIC NAND support

* v5: 1. Removed the patches already applied to linux-next and rebased the remaining patches on [3] 2. Addressed the review comments in v4 and Added Archit Reviewed by tag. [3] http://git.infradead.org/l2-mtd.git/shortlog/refs/heads/nand/next * v4: 1. Added Acked-by from Rob for DT docume

[PATCH v5 03/16] mtd: nand: qcom: add BAM DMA descriptor handling

1. prepare_bam_async_desc is the function which will call all the DMA API’s. It will fetch the outstanding scatter gather list for passed channel and will do the DMA descriptor formation. The DMA flag is dependent upon the type of channel. 2. For ADM DMA, the descriptor is being formed fo

[PATCH V5 net-next 02/21] net-next/hinic: Initialize hw device components

Initialize hw device by calling the initialization functions of aeqs and management channel. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/Makefile| 3 +- drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c | 172 -- dri

[PATCH] i2c: taos-evm: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/i2c/busses/i2c-taos-evm.c | 2 +- 1 file changed, 1 insertion(+), 1 dele

[RFC PATCH v2 1/3] PCI: rockchip: Add support for pcie wake irq

Add support for PCIE_WAKE pin in rockchip pcie driver. Signed-off-by: Jeffy Chen --- Changes in v2: Use dev_pm_set_dedicated_wake_irq -- Suggested by Brian Norris drivers/pci/host/pcie-rockchip.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers

[PATCH] cpufreq: Don't send callback pointer to cpufreq_add_update_util_hook()

The callers already have the structure (struct update_util_data) where the function pointer is saved by cpufreq_add_update_util_hook(). And its better if the callers fill it themselves, as they can do it from the governor->init() callback then, which is called only once per policy lifetime rather t

[RFC PATCH v2 0/3] PCI: rockchip: Move PCIE_WAKE handling into rockchip pcie driver

Currently we are handling pcie wake in mrvl wifi driver. But Brian suggests to move it into rockchip pcie driver. Tested on my chromebook bob(with cros 4.4 kernel and mrvl wifi). Changes in v2: Use dev_pm_set_dedicated_wake_irq -- Suggested by Brian Norris Jeffy Chen (3): PCI: rockc

[RFC PATCH v2 2/3] dt-bindings: PCI: rockchip: Add support for pcie wake irq

Add an optional interrupt for PCIE_WAKE pin. Signed-off-by: Jeffy Chen --- Changes in v2: None .../devicetree/bindings/pci/rockchip-pcie.txt| 20 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt

[RFC PATCH v2 3/3] arm64: dts: rockchip: Handle pcie wake in pcie driver for Gru

Currently we are handling pcie wake irq in mrvl wifi driver. Move it to rockchip pcie driver for Gru boards. Signed-off-by: Jeffy Chen --- Changes in v2: None arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/a

Re: [PATCH v2 1/2] usb: dwc3: keystone: Add PM_RUNTIME Support to DWC3 Keystone USB driver

Hi, Franklin S Cooper Jr writes: > For 66AK2Gx there is a requirement to use PM Runtime to properly manage > clocks and the power domains. Therefore, add PM runtime support. Remove > legacy clock api's calls since other users of this driver worked without > these clock apis calls. > > Signed-off

[PATCH V5 net-next 06/21] net-next/hinic: Add api cmd commands

Add the api cmd commands for sending management messages to the nic. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- .../net/ethernet/huawei/hinic/hinic_hw_api_cmd.c | 329 - .../net/ethernet/huawei/hinic/hinic_hw_api_cmd.h | 65 drivers/net/ethernet/hua

[PATCH V5 net-next 05/21] net-next/hinic: Add management messages

Add the management messages for sending to api cmd and add the asynchronous event handler for the completion of the messages. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- .../net/ethernet/huawei/hinic/hinic_hw_api_cmd.c | 35 ++ .../net/ethernet/huawei/hinic/hinic_hw_api_cmd.h

Re: [RFC PATCH 1/3] PCI: rockchip: Add support for pcie wake irq

Hi Brian, i've tried dev_pm_set_dedicated_wake_irq, it doesn't work well on upstream kernel(for level irq). it looks like we would delay real set trigger type to request irq after this commit: 1e2a7d78499e irqdomain: Don't set type when mapping an IRQ so calling irq_set_status_flags before

[PATCH V5 net-next 07/21] net-next/hinic: Add aeqs

Handle aeq elements that are accumulated on the aeq by calling the registered handler for the specific event. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_hw_csr.h | 49 +++ drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c | 464 +++

[PATCH V5 net-next 08/21] net-next/hinic: Add port management commands

Add the port management commands that are sent as management messages. The port management commands are used for netdev operations. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/Makefile | 4 +- drivers/net/ethernet/huawei/hinic/hinic_dev.h

[PATCH V5 net-next 10/21] net-next/hinic: Add logical Txq and Rxq

Create the logical queues of the nic. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/Makefile | 5 +- drivers/net/ethernet/huawei/hinic/hinic_dev.h| 5 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c | 131 + drivers

[PATCH V5 net-next 09/21] net-next/hinic: Add Rx mode and link event handler

Add port management message for setting Rx mode in the card, used for rx_mode netdev operation. The link event handler is used for getting a notification about the link state. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_dev.h | 17 ++

[PATCH V5 net-next 14/21] net-next/hinic: Initialize cmdq

Create the work queues for cmdq and update the nic about the work queue contexts. cmdq commands are used for updating the nic about the qp contexts. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c | 282 +- drivers

[PATCH V5 net-next 12/21] net-next/hinic: Add qp resources

Create the resources for queue pair operations: doorbell area, consumer index address and producer index address. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/Makefile | 4 +- drivers/net/ethernet/huawei/hinic/hinic_hw_if.h | 1 + drivers

[PATCH V5 net-next 13/21] net-next/hinic: Set qp context

Update the nic about the resources of the queue pairs. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/Makefile | 5 +- drivers/net/ethernet/huawei/hinic/hinic_common.c | 55 ++ drivers/net/ethernet/huawei/hinic/hinic_common.h |

[PATCH v2 0/5] KVM: MMU: 5 level EPT/shadow support

Intel's existing processors limit the maximum linear address width to 48 bits, and the maximum physical address width to 46 bits. And the upcoming processors will extend maximum linear address width to 57 bits and maximum physical address width can go upto 52 bits in practical. With linear address

[PATCH v2 2/5] KVM: MMU: check guest CR3 reserved bits based on its physical address width.

Currently, KVM uses CR3_L_MODE_RESERVED_BITS to check the reserved bits in CR3. Yet the length of reserved bits in guest CR3 should be based on the physical address width exposed to the VM. This patch changes CR3 check logic to calculate the reserved bits at runtime. Signed-off-by: Yu Zhang ---

[PATCH v2 5/5] KVM: MMU: Expose the LA57 feature to VM.

This patch exposes 5 level page table feature to the VM, at the same time, the canonical virtual address checking is extended to support both 48-bits and 57-bits address width. Signed-off-by: Yu Zhang --- arch/x86/include/asm/kvm_host.h | 18 ++ arch/x86/kvm/cpuid.c|

[PATCH v2 4/5] KVM: MMU: Add 5 level EPT & Shadow page table support.

Extends the shadow paging code, so that 5 level shadow page table can be constructed if VM is running in 5 level paging mode. Also extends the ept code, so that 5 level ept table can be constructed if maxphysaddr of VM exceeds 48 bits. Unlike the shadow logic, KVM should still use 4 level ept tabl

[PATCH V5 net-next 16/21] net-next/hinic: Add cmdq commands

Add cmdq commands for setting queue pair contexts in the nic. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_common.c | 25 ++ drivers/net/ethernet/huawei/hinic/hinic_common.h | 9 + drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c | 282

[PATCH v2 1/5] KVM: x86: Add return value to kvm_cpuid().

Return false in kvm_cpuid() when it fails to find the cpuid entry. Also, this routine(and its caller) is optimized with a new argument - check_limit, so that the check_cpuid_limit() fall back can be avoided. Signed-off-by: Yu Zhang --- arch/x86/include/asm/kvm_emulate.h | 4 ++-- arch/x86/kvm/c

[PATCH v2 3/5] KVM: MMU: Rename PT64_ROOT_LEVEL to PT64_ROOT_4LEVEL.

Now we have 4 level page table and 5 level page table in 64 bits long mode, let's rename the PT64_ROOT_LEVEL to PT64_ROOT_4LEVEL, then we can use PT64_ROOT_5LEVEL for 5 level page table, it's helpful to make the code more clear. Also PT64_ROOT_MAX_LEVEL is defined as 4, so that we can just redefin

[PATCH V5 net-next 19/21] net-next/hinic: Add Tx operation

Add transmit operation for sending data by qp operations. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_dev.h| 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c | 47 +++ drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h | 22 ++ d

[PATCH V5 net-next 17/21] net-next/hinic: Add cmdq completion handler

Add cmdq completion handler for getting a notification about the completion of cmdq commands. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c | 297 +- drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h | 12 + 2 f

Re: [PATCH v1 4/4] KVM: MMU: Expose the LA57 feature to VM.

On 12/08/2017 15:35, Yu Zhang wrote: > index a98b88a..50107ae 100644 > --- a/arch/x86/kvm/emulate.c > +++ b/arch/x86/kvm/emulate.c > @@ -694,7 +694,7 @@ static __always_inline int __linearize(struct > x86_emulate_ctxt *ctxt, > switch (mode) { > case X86EMUL_MODE_PROT64: >

[PATCH V5 net-next 18/21] net-next/hinic: Add Rx handler

Set the io resources in the nic and handle rx events by qp operations. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_dev.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_csr.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.

[PATCH V5 net-next 15/21] net-next/hinic: Add ceqs

Initialize the completion event queues and handle ceq events by calling the registered handlers. Used for cmdq command completion. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c | 16 ++ drivers/net/ethernet/huawei/hinic/hinic_hw_cs

Re: [PATCH v4] acpi: apei: fix the wrong iteration of generic error status block

On Thu, Aug 17, 2017 at 08:07:18PM +0800, Dongjiu Geng wrote: > The revision 0x300 generic error data entry is different > from the old version, but currently iterating through the > GHES estatus blocks does not take into account this difference. > This will lead to failure to get the right data en

[PATCH] [media] usb: rainshadow-cec: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/media/usb/rainshadow-cec/rainshadow-cec.c | 2 +- 1 file changed, 1 inse

[PATCH] [media] usb: pulse8-cec: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/media/usb/pulse8-cec/pulse8-cec.c | 2 +- 1 file changed, 1 insertion(+)

[PATCH V5 net-next 20/21] net-next/hinic: Add ethtool and stats

Add ethtool operations and statistics operations. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/hinic_dev.h | 3 + drivers/net/ethernet/huawei/hinic/hinic_main.c | 218 - drivers/net/ethernet/huawei/hinic/hinic_port.c |

Re: [PATCH] iio: accel: mma8452: Bugfix to enbale and allow different events to work parallely.

This patch fixes by detaching the event related information from chip_info struct, and based on channel type and event direction the corresponding event configuration registers are picked dynamically. Hence multiple events can be handled in read/write callbacks. which chip can have which even

[PATCH] staging: fsl-mc: be consistent when checking strcmp() returns

From: Laurentiu Tudor Throughout the driver we use == 0 / != 0 to check strcmp() returns except this place, so fix it. Signed-off-by: Laurentiu Tudor --- drivers/staging/fsl-mc/bus/dprc-driver.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/fsl-mc/bus/dprc

[PATCH V5 net-next 21/21] net-next/hinic: Add netpoll

Add more netdev operation - netpoll. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- MAINTAINERS| 7 +++ drivers/net/ethernet/huawei/hinic/hinic_main.c | 20 2 files changed, 27 insertions(+) diff --git a/MAINTAINERS b/MA

[PATCH V5 net-next 11/21] net-next/hinic: Add wq

Create work queues for being used by the queue pairs. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/Makefile | 4 +- drivers/net/ethernet/huawei/hinic/hinic_common.h | 25 ++ drivers/net/ethernet/huawei/hinic/hinic_hw_io.c | 69 ++- driv

[PATCH] lib/string.c: check for kmalloc() failure

This is mostly to keep the number of static checker warnings down so we can spot new bugs instead of them being drowned in noise. This function doesn't return normal kernel error codes but instead the return value is used to display exactly which memory failed. I chose -1 as hopefully that's a he

[PATCH V5 net-next 04/21] net-next/hinic: Initialize api cmd hw

Update the hardware about api cmd resources and initialize it. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- .../net/ethernet/huawei/hinic/hinic_hw_api_cmd.c | 173 - .../net/ethernet/huawei/hinic/hinic_hw_api_cmd.h | 38 + drivers/net/ethernet/huawei/h

[PATCH V5 net-next 03/21] net-next/hinic: Initialize api cmd resources

Initialize api cmd resources as part of management initialization. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- drivers/net/ethernet/huawei/hinic/Makefile | 4 +- .../net/ethernet/huawei/hinic/hinic_hw_api_cmd.c | 446 + .../net/ethernet/huawei/hini

[PATCH V5 net-next 01/21] net-next/hinic: Initialize hw interface

Initialize hw interface as part of the nic initialization for accessing hw. Signed-off-by: Aviad Krawczyk Signed-off-by: Zhao Chen --- Documentation/networking/hinic.txt | 125 ++ drivers/net/ethernet/Kconfig | 1 + drivers/net/ethernet/Makefile

Re: [PATCH v8 3/3] PCI: dwc: qcom: Add support for IPQ8074 PCIe controller

Varada, On 08/17/2017 02:20 PM, Varadarajan Narayanan wrote: > Add support for the IPQ8074 PCIe controller. IPQ8074 supports > Gen 1/2, one lane, two PCIe root complex with support for MSI and > legacy interrupts, and it conforms to PCI Express Base 2.1 > specification. > > The core init is the

[PATCH V5 net-next 00/21] Huawei HiNIC Ethernet Driver

The patch-set contains the support of the HiNIC Ethernet driver for hinic family of PCIE Network Interface Cards. The Huawei's PCIE HiNIC card is a new Ethernet card and hence there was a need of a new driver. The current driver is meant to be used for the Physical Function and there would soon b

Re: [PATCH] btrfs: remove redundant check on ret being non-zero

On Tue, Aug 15, 2017 at 08:51:02AM +0100, Colin King wrote: > From: Colin Ian King > > The error return variable ret is initialized to zero and then is > checked to see if it is non-zero in the if-block that follows it. > It is therefore impossible for ret to be non-zero after the if-block > henc

[PATCH] mmc: tegra: suppress errors when probe is deferred

Don't print error message when clk_get() returns -EPROBE_DEFER. On recent Tegra chips (t186 onwards), the clocks are provided by auxiliary microprocessor (bpmp) and until the driver for it is probed clocks are not available. While at it, change the real error message more meaningful. Signed-off-b

Re: [PATCH] Coccinelle: add atomic_as_refcounter script

> +identifier fname =~ ".*free.*"; > +identifier fname2 =~ ".*destroy.*"; > +identifier fname3 =~ ".*del.*"; > +identifier fname4 =~ ".*queue_work.*"; > +identifier fname5 =~ ".*schedule_work.*"; > +identifier fname6 =~ ".*call_rcu.*"; Personally, I find the above regular expressions much easier t

Re: [PATCH v2] bpf: Update sysctl documentation to list all supported architectures

On 08/17/2017 12:30 PM, Michael Ellerman wrote: The sysctl documentation states that the JIT is only available on x86_64, which is no longer correct. Update the list, and break it out to indicate which architectures support the cBPF JIT (via HAVE_CBPF_JIT) or the eBPF JIT (HAVE_EBPF_JIT). Signe

[PATCH V5 net-next 00/21] Huawei HiNIC Ethernet Driver

The patch-set contains the support of the HiNIC Ethernet driver for hinic family of PCIE Network Interface Cards. The Huawei's PCIE HiNIC card is a new Ethernet card and hence there was a need of a new driver. The current driver is meant to be used for the Physical Function and there would soon b

[PATCH 00/30] constify input serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Arvind Yadav (30): [PATCH 01/30] Input: iforce: constify serio_device_id [PATCH 02/30] Input: magellan: consti

[PATCH 01/30] Input: iforce: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/input/joystick/iforce/iforce-serio.c | 2 +- 1 file changed, 1 insertion

Re: [PATCH v8 1/3] PCI: dwc: qcom: Use block IP version for operations

Hi Varada, On 08/17/2017 02:20 PM, Varadarajan Narayanan wrote: > Presently, when support for a new SoC is added, the driver ops > structures and functions are versioned with plain 1, 2, 3 etc. > Instead use the block IP version number. > > Signed-off-by: Varadarajan Narayanan > --- > drivers/p

[PATCH 03/30] Input: spaceball: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/input/joystick/spaceball.c | 2 +- 1 file changed, 1 insertion(+), 1 del

[PATCH 05/30] Input: stinger: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/input/joystick/stinger.c | 2 +- 1 file changed, 1 insertion(+), 1 delet

[PATCH 02/30] Input: magellan: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/input/joystick/magellan.c | 2 +- 1 file changed, 1 insertion(+), 1 dele

[PATCH 07/30] Input: warrior: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/input/joystick/warrior.c | 2 +- 1 file changed, 1 insertion(+), 1 delet

[PATCH 08/30] Input: zhenhua: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/input/joystick/zhenhua.c | 2 +- 1 file changed, 1 insertion(+), 1 delet

[PATCH 09/30] Input: iatkbd: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/input/keyboard/atkbd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletio

[PATCH 10/30] Input: hil_kbd: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/input/keyboard/hil_kbd.c | 2 +- 1 file changed, 1 insertion(+), 1 delet

[PATCH 11/30] Input: lkkbd: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/input/keyboard/lkkbd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletio

[PATCH 12/30] Input: newtonkbd: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/input/keyboard/newtonkbd.c | 2 +- 1 file changed, 1 insertion(+), 1 del

[PATCH 14/30] Input: sunkbd: constify serio_device_id

serio_device_id are not supposed to change at runtime. All functions working with serio_device_id provided by work with const serio_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav --- drivers/input/keyboard/sunkbd.c | 2 +- 1 file changed, 1 insertion(+), 1 deleti

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