On Sat, Nov 25, 2017 at 05:59:54PM -0800, Alexei Starovoitov wrote:
> If we were poking into 'struct perf_event_attr __user *uptr'
> directly like get|put_user(.., >config)
> then 32-bit user space with 4-byte aligned u64s would cause
> 64-bit kernel to trap on archs like sparc.
But surely archs
On Sat, Nov 25, 2017 at 05:59:54PM -0800, Alexei Starovoitov wrote:
> If we were poking into 'struct perf_event_attr __user *uptr'
> directly like get|put_user(.., >config)
> then 32-bit user space with 4-byte aligned u64s would cause
> 64-bit kernel to trap on archs like sparc.
But surely archs
On Sun, Nov 26, 2017 at 12:28:49PM +0100, Philippe Ombredanne wrote:
> Greg, Martin:
>
> On Sun, Nov 26, 2017 at 9:59 AM, Greg Kroah-Hartman
> wrote:
> > On Sat, Nov 25, 2017 at 04:42:59PM -0800, Dmitry Torokhov wrote:
> >> Hi Martin,
> >>
> >> On Sat, Nov 18, 2017 at
On Sun, Nov 26, 2017 at 12:28:49PM +0100, Philippe Ombredanne wrote:
> Greg, Martin:
>
> On Sun, Nov 26, 2017 at 9:59 AM, Greg Kroah-Hartman
> wrote:
> > On Sat, Nov 25, 2017 at 04:42:59PM -0800, Dmitry Torokhov wrote:
> >> Hi Martin,
> >>
> >> On Sat, Nov 18, 2017 at 09:45:18AM +0100, Martin
There is no real need for the users of timecounters to define cyclecounter
and timecounter variables separately. Since timecounter will always be
based on cyclecounter, have cyclecounter struct as member of timecounter
struct.
Suggested-by: Chris Wilson
Signed-off-by:
There is no real need for the users of timecounters to define cyclecounter
and timecounter variables separately. Since timecounter will always be
based on cyclecounter, have cyclecounter struct as member of timecounter
struct.
Suggested-by: Chris Wilson
Signed-off-by: Sagar Arun Kamble
Cc: John
On Mon, Nov 27, 2017 at 08:44:01AM +0100, Martin Kepplinger wrote:
> This adds an SPDX license identifier to this driver I wrote some time back.
>
> Signed-off-by: Martin Kepplinger
> ---
>
> Thanks for the feedback. GPL2+ was what I had in mind. My bad. And as I
> already
On Mon, Nov 27, 2017 at 08:44:01AM +0100, Martin Kepplinger wrote:
> This adds an SPDX license identifier to this driver I wrote some time back.
>
> Signed-off-by: Martin Kepplinger
> ---
>
> Thanks for the feedback. GPL2+ was what I had in mind. My bad. And as I
> already see a lot of SPDX
FYI, we noticed the following commit (built with gcc-7):
commit: d17a1d97dc208d664c91cc387ffb752c7f85dc61 ("x86/mm/kasan: don't use
vmemmap_populate() to initialize shadow")
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git master
in testcase: trinity
with following parameters:
FYI, we noticed the following commit (built with gcc-7):
commit: d17a1d97dc208d664c91cc387ffb752c7f85dc61 ("x86/mm/kasan: don't use
vmemmap_populate() to initialize shadow")
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git master
in testcase: trinity
with following parameters:
If something calls ioremap with an address not aligned to PAGE_SIZE, the
returned address might be not aligned as well. This led to a probe
registered on exactly the returned address, but the entire page was armed
for mmiotracing.
On calling iounmap the address passed to unregister_kmmio_probe
If something calls ioremap with an address not aligned to PAGE_SIZE, the
returned address might be not aligned as well. This led to a probe
registered on exactly the returned address, but the entire page was armed
for mmiotracing.
On calling iounmap the address passed to unregister_kmmio_probe
From: "Edgar E. Iglesias"
Currently, we only use the first receive queue and leave the
remaining DMA descriptor pointers pointing at 0.
Disable unused queues by connecting them to a looped descriptor
chain without free slots.
Signed-off-by: Edgar E. Iglesias
From: "Edgar E. Iglesias"
Currently, we only use the first receive queue and leave the
remaining DMA descriptor pointers pointing at 0.
Disable unused queues by connecting them to a looped descriptor
chain without free slots.
Signed-off-by: Edgar E. Iglesias
Signed-off-by: Harini Katakam
Hi Peter,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on mmotm/master]
[also build test ERROR on v4.15-rc1 next-20171127]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
Hi Peter,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on mmotm/master]
[also build test ERROR on v4.15-rc1 next-20171127]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
This adds an SPDX license identifier to this driver I wrote some time back.
Signed-off-by: Martin Kepplinger
---
Thanks for the feedback. GPL2+ was what I had in mind. My bad. And as I
already see a lot of SPDX tags using /**/ comments, I'll use that too.
I think if it is
This adds an SPDX license identifier to this driver I wrote some time back.
Signed-off-by: Martin Kepplinger
---
Thanks for the feedback. GPL2+ was what I had in mind. My bad. And as I
already see a lot of SPDX tags using /**/ comments, I'll use that too.
I think if it is hand-written, it
From: "Edgar E. Iglesias"
Add RX queue pointer to macb queues to make it accessible for the
multiple queues available. Currently the first RX queue is used.
Signed-off-by: Edgar E. Iglesias
Signed-off-by: Harini Katakam
From: Harini Katakam
Handle HRESP error by doing a SW reset of RX and TX and
re-initializing the descriptors, RX and TX queue pointers.
Signed-off-by: Harini Katakam
Signed-off-by: Michal Simek
---
From: "Edgar E. Iglesias"
Add RX queue pointer to macb queues to make it accessible for the
multiple queues available. Currently the first RX queue is used.
Signed-off-by: Edgar E. Iglesias
Signed-off-by: Harini Katakam
Signed-off-by: Michal Simek
---
drivers/net/ethernet/cadence/macb.h
From: Harini Katakam
Handle HRESP error by doing a SW reset of RX and TX and
re-initializing the descriptors, RX and TX queue pointers.
Signed-off-by: Harini Katakam
Signed-off-by: Michal Simek
---
drivers/net/ethernet/cadence/macb.h | 2 +
drivers/net/ethernet/cadence/macb_main.c | 65
This series fixes the following:
-> Ties off unused RX queues
-> Handles RX HRESP error
Edgar E. Iglesias (2):
net: macb: Add RBQP to the macb queues
net: macb: Tie-off unused RX queues
Harini Katakam (1):
net: macb: Handle HRESP error
drivers/net/ethernet/cadence/macb.h | 5 ++
This series fixes the following:
-> Ties off unused RX queues
-> Handles RX HRESP error
Edgar E. Iglesias (2):
net: macb: Add RBQP to the macb queues
net: macb: Tie-off unused RX queues
Harini Katakam (1):
net: macb: Handle HRESP error
drivers/net/ethernet/cadence/macb.h | 5 ++
Hi,
Please ignore this series.
I'm sending another updated one.
Sorry for the inconvenience.
Regards,
Harini
On Mon, Nov 27, 2017 at 12:33 PM, Harini Katakam
wrote:
> From: "Edgar E. Iglesias"
>
> Add RX queue pointer to macb queues to
Hi,
Please ignore this series.
I'm sending another updated one.
Sorry for the inconvenience.
Regards,
Harini
On Mon, Nov 27, 2017 at 12:33 PM, Harini Katakam
wrote:
> From: "Edgar E. Iglesias"
>
> Add RX queue pointer to macb queues to make it accessible for the
> multiple queues available.
From: Rui Feng
Add support for new chip rts5260.
In order to support rts5260, the definitions of
some internal registers and workflow have to be
modified and are different from its predecessors
and OCP function is added for RTS5260. So we need
this patch to ensure
From: Rui Feng
Add support for new chip rts5260.
In order to support rts5260, the definitions of
some internal registers and workflow have to be
modified and are different from its predecessors
and OCP function is added for RTS5260. So we need
this patch to ensure RTS5260 can work.
From: Rui Feng
Because Realtek card reader drivers are pcie and usb drivers,
and they bridge mmc subsystem and memstick subsystem, they are
not mfd drivers. Greg and Lee Jones had a discussion about
where to put the drivers, the result is that misc is a good
place for
From: Rui Feng
Because Realtek card reader drivers are pcie and usb drivers,
and they bridge mmc subsystem and memstick subsystem, they are
not mfd drivers. Greg and Lee Jones had a discussion about
where to put the drivers, the result is that misc is a good
place for them, so I move all files
On 11/24/2017 01:50 PM, Colin King wrote:
> From: Colin Ian King
>
> Use setup_timer function instead of initializing timer with the
> function and data fields.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/s390/net/fsm.c | 4 +---
> 1
On 11/24/2017 01:50 PM, Colin King wrote:
> From: Colin Ian King
>
> Use setup_timer function instead of initializing timer with the
> function and data fields.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/s390/net/fsm.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
>
It was <2017-11-24 pią 16:25>, when PrasannaKumar Muralidharan wrote:
>> +}
>> +
>> +static int exynos_trng_do_read(struct hwrng *rng, void *data, size_t max,
>> + bool wait)
>> +{
>> + struct exynos_trng_dev *trng;
>> + u32 val;
>> +
>> + max = max >
It was <2017-11-24 pią 16:25>, when PrasannaKumar Muralidharan wrote:
>> +}
>> +
>> +static int exynos_trng_do_read(struct hwrng *rng, void *data, size_t max,
>> + bool wait)
>> +{
>> + struct exynos_trng_dev *trng;
>> + u32 val;
>> +
>> + max = max >
From: Andrei Vagin
It is a hybrid of process_vm_readv() and vmsplice().
vmsplice can map memory from a current address space into a pipe.
process_vm_readv can read memory of another process.
A new system call can map memory of another process into a pipe.
ssize_t
From: Andrei Vagin
It is a hybrid of process_vm_readv() and vmsplice().
vmsplice can map memory from a current address space into a pipe.
process_vm_readv can read memory of another process.
A new system call can map memory of another process into a pipe.
ssize_t process_vmsplice(pid_t pid,
Signed-off-by: Mike Rapoport
---
man2/process_vmsplice.2 | 188
1 file changed, 188 insertions(+)
create mode 100644 man2/process_vmsplice.2
diff --git a/man2/process_vmsplice.2 b/man2/process_vmsplice.2
new file mode
Signed-off-by: Mike Rapoport
---
man2/process_vmsplice.2 | 188
1 file changed, 188 insertions(+)
create mode 100644 man2/process_vmsplice.2
diff --git a/man2/process_vmsplice.2 b/man2/process_vmsplice.2
new file mode 100644
index
Signed-off-by: Mike Rapoport
---
fs/splice.c | 57 -
1 file changed, 36 insertions(+), 21 deletions(-)
diff --git a/fs/splice.c b/fs/splice.c
index 39e2dc0..7f1ffc5 100644
--- a/fs/splice.c
+++ b/fs/splice.c
@@
Signed-off-by: Mike Rapoport
---
fs/splice.c | 57 -
1 file changed, 36 insertions(+), 21 deletions(-)
diff --git a/fs/splice.c b/fs/splice.c
index 39e2dc0..7f1ffc5 100644
--- a/fs/splice.c
+++ b/fs/splice.c
@@ -1185,6 +1185,36 @@ static
From: Andrei Vagin
This test checks that process_vmsplice() can splice pages from a remote
process and returns EFAULT, if process_vmsplice() tries to splice pages
by an unaccessiable address.
Signed-off-by: Andrei Vagin
Signed-off-by: Mike Rapoport
From: Andrei Vagin
Signed-off-by: Andrei Vagin
---
arch/x86/entry/syscalls/syscall_32.tbl | 1 +
arch/x86/entry/syscalls/syscall_64.tbl | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/x86/entry/syscalls/syscall_32.tbl
From: Andrei Vagin
Signed-off-by: Andrei Vagin
---
arch/x86/entry/syscalls/syscall_32.tbl | 1 +
arch/x86/entry/syscalls/syscall_64.tbl | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/x86/entry/syscalls/syscall_32.tbl
b/arch/x86/entry/syscalls/syscall_32.tbl
index 448ac21..dc64bf5
From: Andrei Vagin
This test checks that process_vmsplice() can splice pages from a remote
process and returns EFAULT, if process_vmsplice() tries to splice pages
by an unaccessiable address.
Signed-off-by: Andrei Vagin
Signed-off-by: Mike Rapoport
---
Hi,
This patches introduces new process_vmsplice system call that combines
functionality of process_vm_read and vmsplice.
It allows to map the memory of another process into a pipe, similarly to
what vmsplice does for its own address space.
The patch 2/4 ("vm: add a syscall to map a process
Hi,
This patches introduces new process_vmsplice system call that combines
functionality of process_vm_read and vmsplice.
It allows to map the memory of another process into a pipe, similarly to
what vmsplice does for its own address space.
The patch 2/4 ("vm: add a syscall to map a process
From: Richard Leitner
Previously phy_id was u32 and phy_id_mask was unsigned int. As the
phy_id_mask defines the important bits of the phy_id (and is therefore
the same size) these two variables should be the same data type.
Signed-off-by: Richard Leitner
From: Richard Leitner
Previously phy_id was u32 and phy_id_mask was unsigned int. As the
phy_id_mask defines the important bits of the phy_id (and is therefore
the same size) these two variables should be the same data type.
Signed-off-by: Richard Leitner
Reviewed-by: Florian Fainelli
From: "Edgar E. Iglesias"
Currently, we only use the first receive queue and leave the
remaining DMA descriptor pointers pointing at 0.
Disable unused queues by connecting them to a looped descriptor
chain without free slots.
Signed-off-by: Edgar E. Iglesias
From: "Edgar E. Iglesias"
Currently, we only use the first receive queue and leave the
remaining DMA descriptor pointers pointing at 0.
Disable unused queues by connecting them to a looped descriptor
chain without free slots.
Signed-off-by: Edgar E. Iglesias
Signed-off-by: Harini Katakam
From: "Edgar E. Iglesias"
Add RX queue pointer to macb queues to make it accessible for the
multiple queues available. Currently the first RX queue is used.
Signed-off-by: Edgar E. Iglesias
Signed-off-by: Harini Katakam
From: "Edgar E. Iglesias"
Add RX queue pointer to macb queues to make it accessible for the
multiple queues available. Currently the first RX queue is used.
Signed-off-by: Edgar E. Iglesias
Signed-off-by: Harini Katakam
Signed-off-by: Michal Simek
---
drivers/net/ethernet/cadence/macb.h
Hmm, this is almost 20 years old code (
I think the original code did a burst write and didn't check for error
conditions until the very last byte write. I seem to remember that there was
some text in the original standard to that effect (this may have gone back as
far as IBM's ESS spec).
The
Hmm, this is almost 20 years old code (
I think the original code did a burst write and didn't check for error
conditions until the very last byte write. I seem to remember that there was
some text in the original standard to that effect (this may have gone back as
far as IBM's ESS spec).
The
Reference count of device node was increased in of_i2c_register_device,
but without decreasing it in i2c_unregister_device. Then the dynamically
added device node will never be released.
Fix this by adding the of_node_put.
Signed-off-by: Lixin Wang
---
Reference count of device node was increased in of_i2c_register_device,
but without decreasing it in i2c_unregister_device. Then the dynamically
added device node will never be released.
Fix this by adding the of_node_put.
Signed-off-by: Lixin Wang
---
drivers/i2c/i2c-core-base.c | 4 +++-
1
Hi Peter,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on mmotm/master]
[also build test ERROR on v4.15-rc1 next-20171124]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
Hi Peter,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on mmotm/master]
[also build test ERROR on v4.15-rc1 next-20171124]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
This patch adds region_id to fpga_image_info data structure, it
allows driver to pass region id information to fpga-mgr via
fpga_image_info for fpga reconfiguration function.
Signed-off-by: Wu Hao
v3: add one line comment for region_id
---
include/linux/fpga/fpga-mgr.h |
Add a document for Intel FPGA driver overview.
Signed-off-by: Enno Luebbers
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
v2: added FME fpga-mgr/bridge/region platform driver to driver organization.
Hi All,
Here is v3 patch-series adding drivers for Intel FPGA devices.
The Intel FPGA driver provides interfaces for userspace applications to
configure, enumerate, open, and access FPGA accelerators on platforms
equipped with Intel(R) PCIe based FPGA solutions and enables system
level
This patch adds region_id to fpga_image_info data structure, it
allows driver to pass region id information to fpga-mgr via
fpga_image_info for fpga reconfiguration function.
Signed-off-by: Wu Hao
v3: add one line comment for region_id
---
include/linux/fpga/fpga-mgr.h | 2 ++
1 file
Add a document for Intel FPGA driver overview.
Signed-off-by: Enno Luebbers
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
v2: added FME fpga-mgr/bridge/region platform driver to driver organization.
updated open discussion per current implementation.
fixed some typos.
v3:
Hi All,
Here is v3 patch-series adding drivers for Intel FPGA devices.
The Intel FPGA driver provides interfaces for userspace applications to
configure, enumerate, open, and access FPGA accelerators on platforms
equipped with Intel(R) PCIe based FPGA solutions and enables system
level
On Sun, 26 Nov 2017, Logan Gunthorpe wrote:
>
>
> On 26/11/17 11:42 PM, Julia Lawall wrote:
> > Although I guess that in that case the whole exercise is pointless?
> > Because every print will at runtime be followed by another print, which
> > will add either the newline or a continuation.
>
>
On Sun, 26 Nov 2017, Logan Gunthorpe wrote:
>
>
> On 26/11/17 11:42 PM, Julia Lawall wrote:
> > Although I guess that in that case the whole exercise is pointless?
> > Because every print will at runtime be followed by another print, which
> > will add either the newline or a continuation.
>
>
Device Feature List (DFL) defines a feature list structure that creates
a link list of feature headers within the MMIO space to provide an
extensible way of adding features. This patch introduces a kernel module
to provide basic infrastructure to support FPGA devices which implement
the Device
Device Feature List (DFL) defines a feature list structure that creates
a link list of feature headers within the MMIO space to provide an
extensible way of adding features. This patch introduces a kernel module
to provide basic infrastructure to support FPGA devices which implement
the Device
For feature devices, e.g FPGA Management Engine (FME), it may
require fpga_cdev_find_port function to find dedicate port for
further actions, so export this function from feature device
driver module.
Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
From: Xiao Guangrong
This patch abstracts the common operations of the sub features, and defines
the feature_ops data structure, including init, uinit and ioctl function
pointers. And this patch adds some common helper functions for FME and AFU
drivers, e.g
For feature devices, e.g FPGA Management Engine (FME), it may
require fpga_cdev_find_port function to find dedicate port for
further actions, so export this function from feature device
driver module.
Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
From: Xiao Guangrong
This patch abstracts the common operations of the sub features, and defines
the feature_ops data structure, including init, uinit and ioctl function
pointers. And this patch adds some common helper functions for FME and AFU
drivers, e.g feature_dev_use_begin/end which are
From: Kang Luwei
The FPGA Management Engine (FME) provides power, thermal management,
performance counters, partial reconfiguration and other functions. For each
function, it is packaged into a private feature linked to the FME feature
device in the 'Device Feature List'.
From: Kang Luwei
The FPGA Management Engine (FME) provides power, thermal management,
performance counters, partial reconfiguration and other functions. For each
function, it is packaged into a private feature linked to the FME feature
device in the 'Device Feature List'. It's a platform device
Sometimes f2fs_gc is called with no target victim (e.g. xfstest
generic/027, ndirty_node:545 ndiry_dent:1 ndirty_imeta:513 rsvd_segs:21
free_segs:27, has_not_enough_free_secs will return true). This patch
first merges pages and then converts into sections.
Signed-off-by: Yunlong Song
From: Kang Luwei
The header register set is always present for FPGA Management Engine (FME),
this patch implements init and uinit function for header sub feature and
introduce several read-only sysfs interfaces for the capability and status.
Sysfs interfaces:
*
Sometimes f2fs_gc is called with no target victim (e.g. xfstest
generic/027, ndirty_node:545 ndiry_dent:1 ndirty_imeta:513 rsvd_segs:21
free_segs:27, has_not_enough_free_secs will return true). This patch
first merges pages and then converts into sections.
Signed-off-by: Yunlong Song
---
From: Kang Luwei
The header register set is always present for FPGA Management Engine (FME),
this patch implements init and uinit function for header sub feature and
introduce several read-only sysfs interfaces for the capability and status.
Sysfs interfaces:
*
The Device Feature List (DFL) is implemented in MMIO, and features
are linked via the DFLs. This patch enables pcie driver to prepare
enumeration information (e.g locations of all device feature lists
in MMIO) and use common APIs provided by the Device Feature List
framework to enumerate each
The Device Feature List (DFL) is implemented in MMIO, and features
are linked via the DFLs. This patch enables pcie driver to prepare
enumeration information (e.g locations of all device feature lists
in MMIO) and use common APIs provided by the Device Feature List
framework to enumerate each
This patch adds fpga bridge platform driver for FPGA Management Engine.
It implements the enable_set call back for fpga bridge.
Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
This patch adds fpga bridge platform driver for FPGA Management Engine.
It implements the enable_set call back for fpga bridge.
Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Wu Hao
v3: rename driver to
The port header register set is always present for port, it is mainly
for capability, control and status of the ports that AFU connected to.
This patch implements header sub feature support. Below user interfaces
are created by this patch.
Sysfs interface:
* /sys/class/fpga_region///id
This patch adds fpga region platform driver for FPGA Management Engine.
It register an fpga region with given fpga manager / bridge device.
Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
FPGA_GET_API_VERSION and FPGA_CHECK_EXTENSION ioctls are common ones which
need to be supported by all feature devices drivers including FME and AFU.
Userspace application can use these ioctl interfaces to get the API info
and check if specific extension is supported or not in current driver.
This patch adds fpga region platform driver for FPGA Management Engine.
It register an fpga region with given fpga manager / bridge device.
Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Wu Hao
v3:
FPGA_GET_API_VERSION and FPGA_CHECK_EXTENSION ioctls are common ones which
need to be supported by all feature devices drivers including FME and AFU.
Userspace application can use these ioctl interfaces to get the API info
and check if specific extension is supported or not in current driver.
The port header register set is always present for port, it is mainly
for capability, control and status of the ports that AFU connected to.
This patch implements header sub feature support. Below user interfaces
are created by this patch.
Sysfs interface:
* /sys/class/fpga_region///id
From: Xiao Guangrong
User Accelerated Function Unit sub feature exposes the MMIO region of
the AFU. After valid green bitstream (GBS) is programmed and port is
enabled, then this MMIO region could be accessed.
This patch adds support to enumerate the AFU MMIO
From: Xiao Guangrong
User Accelerated Function Unit sub feature exposes the MMIO region of
the AFU. After valid green bitstream (GBS) is programmed and port is
enabled, then this MMIO region could be accessed.
This patch adds support to enumerate the AFU MMIO region and expose it
to userspace
On 26/11/17 11:42 PM, Julia Lawall wrote:
> Although I guess that in that case the whole exercise is pointless?
> Because every print will at runtime be followed by another print, which
> will add either the newline or a continuation.
Yes, in practice the '\n' at the end of every log line is
On 26/11/17 11:42 PM, Julia Lawall wrote:
> Although I guess that in that case the whole exercise is pointless?
> Because every print will at runtime be followed by another print, which
> will add either the newline or a continuation.
Yes, in practice the '\n' at the end of every log line is
FPGA_GET_API_VERSION and FPGA_CHECK_EXTENSION ioctls are common ones which
need to be supported by all feature devices drivers including FME and AFU.
This patch implements above 2 ioctls in FPGA Accelerated Function Unit
(AFU) driver.
Signed-off-by: Tim Whisonant
This patch adds fpga manager driver for FPGA Management Engine (FME). It
implements fpga_manager_ops for FPGA Partial Reconfiguration function.
Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
FPGA_GET_API_VERSION and FPGA_CHECK_EXTENSION ioctls are common ones which
need to be supported by all feature devices drivers including FME and AFU.
This patch implements above 2 ioctls in FPGA Accelerated Function Unit
(AFU) driver.
Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
This patch adds fpga manager driver for FPGA Management Engine (FME). It
implements fpga_manager_ops for FPGA Partial Reconfiguration function.
Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
DMA memory regions are required for Accelerated Function Unit (AFU) usage.
These two ioctls allow user space applications to map user memory regions
for dma, and unmap them after use. Iova is returned from driver to user
space application via FPGA_PORT_DMA_MAP ioctl. Application needs to unmap
it
DMA memory regions are required for Accelerated Function Unit (AFU) usage.
These two ioctls allow user space applications to map user memory regions
for dma, and unmap them after use. Iova is returned from driver to user
space application via FPGA_PORT_DMA_MAP ioctl. Application needs to unmap
it
This patch adds status to fpga-manager data structure, to allow
driver to store full/partial reconfiguration errors and other
status information, and adds one status callback to fpga_manager_ops
to allow fpga_manager to collect latest status when failures are
detected.
The following sysfs file is
For feature devices drivers, both the FPGA Management Engine (FME) and
Accelerated Function Unit (AFU) driver need to expose user interfaces via
the device file, for example, mmap and ioctls.
This patch adds chardev support in the fpga-dfl driver for feature devices,
FME and AFU. It reserves the
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