[PATCH 17/29] arm64: Kconfig: Add CONFIG_UNMAP_KERNEL_AT_EL0

From: Will Deacon commit 084eb77cd3a8 upstream. Add a Kconfig entry to control use of the entry trampoline, which allows us to unmap the kernel whilst running in userspace and improve the robustness of KASLR. Reviewed-by: Mark Rutland Tested-by: Laura Abbott Tested-by: Shanker Donthineni

linux-next: Tree for Feb 28

Hi all, Changes since 20180227: The net-next tree gained a conflict against the net tree. Non-merge commits (relative to Linus' tree): 3753 4443 files changed, 168483 insertions(+), 107955 deletions(-) I have

[PATCH 25/29] arm64: kpti: Make use of nG dependent on arm64_kernel_unmapped_at_el0()

From: Will Deacon commit 41acec624087 upstream. To allow systems which do not require kpti to continue running with global kernel mappings (which appears to be a requirement for Cavium ThunderX due to a CPU erratum), make the use of nG in the kernel page tables dependent on

[PATCH 25/29] arm64: kpti: Make use of nG dependent on arm64_kernel_unmapped_at_el0()

From: Will Deacon commit 41acec624087 upstream. To allow systems which do not require kpti to continue running with global kernel mappings (which appears to be a requirement for Cavium ThunderX due to a CPU erratum), make the use of nG in the kernel page tables dependent on

[PATCH 26/29] arm64: kpti: Add ->enable callback to remap swapper using nG mappings

From: Will Deacon commit f992b4dfd58b upstream. Defaulting to global mappings for kernel space is generally good for performance and appears to be necessary for Cavium ThunderX. If we subsequently decide that we need to enable kpti, then we need to rewrite our existing page

[PATCH 26/29] arm64: kpti: Add ->enable callback to remap swapper using nG mappings

From: Will Deacon commit f992b4dfd58b upstream. Defaulting to global mappings for kernel space is generally good for performance and appears to be necessary for Cavium ThunderX. If we subsequently decide that we need to enable kpti, then we need to rewrite our existing page table entries to be

[PATCH 28/29] arm64: entry: Reword comment about post_ttbr_update_workaround

From: Will Deacon commit f167211a93ac upstream. We don't fully understand the Cavium ThunderX erratum, but it appears that mapping the kernel as nG can lead to horrible consequences such as attempting to execute userspace from kernel context. Since kpti isn't enabled for

[PATCH 28/29] arm64: entry: Reword comment about post_ttbr_update_workaround

From: Will Deacon commit f167211a93ac upstream. We don't fully understand the Cavium ThunderX erratum, but it appears that mapping the kernel as nG can lead to horrible consequences such as attempting to execute userspace from kernel context. Since kpti isn't enabled for these CPUs anyway,

[PATCH 29/29] arm64: idmap: Use "awx" flags for .idmap.text .pushsection directives

From: Will Deacon commit 439e70e27a51 upstream. The identity map is mapped as both writeable and executable by the SWAPPER_MM_MMUFLAGS and this is relied upon by the kpti code to manage a synchronisation flag. Update the .pushsection flags to reflect the actual mapping

[PATCH 29/29] arm64: idmap: Use "awx" flags for .idmap.text .pushsection directives

From: Will Deacon commit 439e70e27a51 upstream. The identity map is mapped as both writeable and executable by the SWAPPER_MM_MMUFLAGS and this is relied upon by the kpti code to manage a synchronisation flag. Update the .pushsection flags to reflect the actual mapping attributes. Reported-by:

[PATCH 27/29] arm64: Force KPTI to be disabled on Cavium ThunderX

From: Marc Zyngier commit 6dc52b15c4a4 upstream. Cavium ThunderX's erratum 27456 results in a corruption of icache entries that are loaded from memory that is mapped as non-global (i.e. ASID-tagged). As KPTI is based on memory being mapped non-global, let's prevent it

[PATCH 24/29] arm64: Turn on KPTI only on CPUs that need it

From: Jayachandran C commit 0ba2e29c7fc1 upstream. Whitelist Broadcom Vulcan/Cavium ThunderX2 processors in unmap_kernel_at_el0(). These CPUs are not vulnerable to CVE-2017-5754 and do not need KPTI when KASLR is off. Acked-by: Will Deacon

[PATCH 27/29] arm64: Force KPTI to be disabled on Cavium ThunderX

From: Marc Zyngier commit 6dc52b15c4a4 upstream. Cavium ThunderX's erratum 27456 results in a corruption of icache entries that are loaded from memory that is mapped as non-global (i.e. ASID-tagged). As KPTI is based on memory being mapped non-global, let's prevent it from kicking in if this

[PATCH 24/29] arm64: Turn on KPTI only on CPUs that need it

From: Jayachandran C commit 0ba2e29c7fc1 upstream. Whitelist Broadcom Vulcan/Cavium ThunderX2 processors in unmap_kernel_at_el0(). These CPUs are not vulnerable to CVE-2017-5754 and do not need KPTI when KASLR is off. Acked-by: Will Deacon Signed-off-by: Jayachandran C Signed-off-by: Catalin

[PATCH 20/29] arm64: Allow checking of a CPU-local erratum

From: Marc Zyngier commit 8f4137588261d7504f4aa022dc9d1a1fd1940e8e upstream. this_cpu_has_cap() only checks the feature array, and not the errata one. In order to be able to check for a CPU-local erratum, allow it to inspect the latter as well. This is consistent with

[PATCH 20/29] arm64: Allow checking of a CPU-local erratum

From: Marc Zyngier commit 8f4137588261d7504f4aa022dc9d1a1fd1940e8e upstream. this_cpu_has_cap() only checks the feature array, and not the errata one. In order to be able to check for a CPU-local erratum, allow it to inspect the latter as well. This is consistent with cpus_have_cap()'s

[PATCH 23/29] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs

From: Jayachandran C commit 0d90718871fe upstream. Add the older Broadcom ID as well as the new Cavium ID for ThunderX2 CPUs. Signed-off-by: Jayachandran C Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas

[PATCH 22/29] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75

From: Will Deacon commit f0be3364335d47267aa1f7c5ed5faaa59c70db13 upstream Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they will soon need MIDR matches for hardening the branch predictor. Signed-off-by: Will Deacon Signed-off-by:

[PATCH 21/29] arm64: capabilities: Handle duplicate entries for a capability

From: Suzuki K Poulose commit 67948af41f2e upstream. Sometimes a single capability could be listed multiple times with differing matches(), e.g, CPU errata for different MIDR versions. This breaks verify_local_cpu_feature() and this_cpu_has_cap() as we stop checking for

[PATCH 23/29] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs

From: Jayachandran C commit 0d90718871fe upstream. Add the older Broadcom ID as well as the new Cavium ID for ThunderX2 CPUs. Signed-off-by: Jayachandran C Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Alex Shi Conflicts: no falkor support in

[PATCH 22/29] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75

From: Will Deacon commit f0be3364335d47267aa1f7c5ed5faaa59c70db13 upstream Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they will soon need MIDR matches for hardening the branch predictor. Signed-off-by: Will Deacon Signed-off-by: Alex Shi Conflicts: add A73

[PATCH 21/29] arm64: capabilities: Handle duplicate entries for a capability

From: Suzuki K Poulose commit 67948af41f2e upstream. Sometimes a single capability could be listed multiple times with differing matches(), e.g, CPU errata for different MIDR versions. This breaks verify_local_cpu_feature() and this_cpu_has_cap() as we stop checking for a capability on a CPU

[PATCH 15/29] arm64: kaslr: Put kernel vectors address in separate data page

From: Will Deacon commit 6c27c4082f4f upstream. The literal pool entry for identifying the vectors base is the only piece of information in the trampoline page that identifies the true location of the kernel. This patch moves it into a page-aligned region of the .rodata

[PATCH 19/29] arm64: Take into account ID_AA64PFR0_EL1.CSV3

From: Will Deacon commit 179a56f6f9fb upstream. For non-KASLR kernels where the KPTI behaviour has not been overridden on the command line we can use ID_AA64PFR0_EL1.CSV3 to determine whether or not we should unmap the kernel whilst running at EL0. Reviewed-by: Suzuki K

[PATCH 15/29] arm64: kaslr: Put kernel vectors address in separate data page

From: Will Deacon commit 6c27c4082f4f upstream. The literal pool entry for identifying the vectors base is the only piece of information in the trampoline page that identifies the true location of the kernel. This patch moves it into a page-aligned region of the .rodata section and maps this

[PATCH 19/29] arm64: Take into account ID_AA64PFR0_EL1.CSV3

From: Will Deacon commit 179a56f6f9fb upstream. For non-KASLR kernels where the KPTI behaviour has not been overridden on the command line we can use ID_AA64PFR0_EL1.CSV3 to determine whether or not we should unmap the kernel whilst running at EL0. Reviewed-by: Suzuki K Poulose Signed-off-by:

[PATCH 18/29] arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry

From: Will Deacon commit 0617052ddde3 upstream. Although CONFIG_UNMAP_KERNEL_AT_EL0 does make KASLR more robust, it's actually more useful as a mitigation against speculation attacks that can leak arbitrary kernel data to userspace through speculation. Reword the Kconfig

[PATCH 16/29] arm64: use RET instruction for exiting the trampoline

From: Will Deacon commit be04a6d1126b upstream. Speculation attacks against the entry trampoline can potentially resteer the speculative instruction stream through the indirect branch and into arbitrary gadgets within the kernel. This patch defends against these attacks by

[PATCH 18/29] arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry

From: Will Deacon commit 0617052ddde3 upstream. Although CONFIG_UNMAP_KERNEL_AT_EL0 does make KASLR more robust, it's actually more useful as a mitigation against speculation attacks that can leak arbitrary kernel data to userspace through speculation. Reword the Kconfig help message to

[PATCH 16/29] arm64: use RET instruction for exiting the trampoline

From: Will Deacon commit be04a6d1126b upstream. Speculation attacks against the entry trampoline can potentially resteer the speculative instruction stream through the indirect branch and into arbitrary gadgets within the kernel. This patch defends against these attacks by forcing a

[PATCH 11/29] arm64: entry: Explicitly pass exception level to kernel_ventry macro

From: Will Deacon commit 5b1f7fe41909 upstream. We will need to treat exceptions from EL0 differently in kernel_ventry, so rework the macro to take the exception level as an argument and construct the branch target using that. Reviewed-by: Mark Rutland

[PATCH 07/29] arm64: entry.S: move SError handling into a C function for future expansion

From: Xie XiuQi commit a92d4d1454ab upstream. Today SError is taken using the inv_entry macro that ends up in bad_mode. SError can be used by the RAS Extensions to notify either the OS or firmware of CPU problems, some of which may have been corrected. To allow this

[PATCH 12/29] arm64: entry: Hook up entry trampoline to exception vectors

From: Will Deacon commit 4bf3286d29f3 upstream. Hook up the entry trampoline to our exception vectors so that all exceptions from and returns to EL0 go via the trampoline, which swizzles the vector base register accordingly. Transitioning to and from the kernel clobbers

[PATCH 11/29] arm64: entry: Explicitly pass exception level to kernel_ventry macro

From: Will Deacon commit 5b1f7fe41909 upstream. We will need to treat exceptions from EL0 differently in kernel_ventry, so rework the macro to take the exception level as an argument and construct the branch target using that. Reviewed-by: Mark Rutland Tested-by: Laura Abbott Tested-by:

[PATCH 07/29] arm64: entry.S: move SError handling into a C function for future expansion

From: Xie XiuQi commit a92d4d1454ab upstream. Today SError is taken using the inv_entry macro that ends up in bad_mode. SError can be used by the RAS Extensions to notify either the OS or firmware of CPU problems, some of which may have been corrected. To allow this handling to be added, add

[PATCH 12/29] arm64: entry: Hook up entry trampoline to exception vectors

From: Will Deacon commit 4bf3286d29f3 upstream. Hook up the entry trampoline to our exception vectors so that all exceptions from and returns to EL0 go via the trampoline, which swizzles the vector base register accordingly. Transitioning to and from the kernel clobbers x30, so we use

[PATCH 14/29] arm64: entry: Add fake CPU feature for unmapping the kernel at EL0

From: Will Deacon commit ea1e3de85e94 upstream. Allow explicit disabling of the entry trampoline on the kernel command line (kpti=off) by adding a fake CPU feature (ARM64_UNMAP_KERNEL_AT_EL0) that can be used to toggle the alternative sequences in our entry code and avoid

[PATCH 14/29] arm64: entry: Add fake CPU feature for unmapping the kernel at EL0

From: Will Deacon commit ea1e3de85e94 upstream. Allow explicit disabling of the entry trampoline on the kernel command line (kpti=off) by adding a fake CPU feature (ARM64_UNMAP_KERNEL_AT_EL0) that can be used to toggle the alternative sequences in our entry code and avoid use of the trampoline

[PATCH 09/29] arm64: entry: Add exception trampoline page for exceptions from EL0

From: Will Deacon commit c7b9adaf85f8 upstream. To allow unmapping of the kernel whilst running at EL0, we need to point the exception vectors at an entry trampoline that can map/unmap the kernel on entry/exit respectively. This patch adds the trampoline page, although it

[PATCH 08/29] module: extend 'rodata=off' boot cmdline parameter to module mappings

From: AKASHI Takahiro commit 39290b389ea upstream. The current "rodata=off" parameter disables read-only kernel mappings under CONFIG_DEBUG_RODATA: commit d2aa1acad22f ("mm/init: Add 'rodata=off' boot cmdline parameter to disable read-only kernel mappings")

[PATCH 09/29] arm64: entry: Add exception trampoline page for exceptions from EL0

From: Will Deacon commit c7b9adaf85f8 upstream. To allow unmapping of the kernel whilst running at EL0, we need to point the exception vectors at an entry trampoline that can map/unmap the kernel on entry/exit respectively. This patch adds the trampoline page, although it is not yet plugged

[PATCH 08/29] module: extend 'rodata=off' boot cmdline parameter to module mappings

From: AKASHI Takahiro commit 39290b389ea upstream. The current "rodata=off" parameter disables read-only kernel mappings under CONFIG_DEBUG_RODATA: commit d2aa1acad22f ("mm/init: Add 'rodata=off' boot cmdline parameter to disable read-only kernel mappings") This patch is a logical

[PATCH 13/29] arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks

From: Will Deacon commit 18011eac28c7 upstream. When unmapping the kernel at EL0, we use tpidrro_el0 as a scratch register during exception entry from native tasks and subsequently zero it in the kernel_ventry macro. We can therefore avoid zeroing tpidrro_el0 in the

[PATCH 13/29] arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks

From: Will Deacon commit 18011eac28c7 upstream. When unmapping the kernel at EL0, we use tpidrro_el0 as a scratch register during exception entry from native tasks and subsequently zero it in the kernel_ventry macro. We can therefore avoid zeroing tpidrro_el0 in the context-switch path for

[PATCH 02/29] arm64: mm: Move ASID from TTBR0 to TTBR1

From: Will Deacon commit 7655abb95386 upstream. In preparation for mapping kernelspace and userspace with different ASIDs, move the ASID to TTBR1 and update switch_mm to context-switch TTBR0 via an invalid mapping (the zero page). Reviewed-by: Mark Rutland

[PATCH 05/29] arm64: mm: Invalidate both kernel and user ASIDs when performing TLBI

From: Will Deacon commit 9b0de864b5bc upstream. Since an mm has both a kernel and a user ASID, we need to ensure that broadcast TLB maintenance targets both address spaces so that things like CoW continue to work with the uaccess primitives in the kernel. Reviewed-by: Mark

[PATCH 02/29] arm64: mm: Move ASID from TTBR0 to TTBR1

From: Will Deacon commit 7655abb95386 upstream. In preparation for mapping kernelspace and userspace with different ASIDs, move the ASID to TTBR1 and update switch_mm to context-switch TTBR0 via an invalid mapping (the zero page). Reviewed-by: Mark Rutland Tested-by: Laura Abbott Tested-by:

[PATCH 05/29] arm64: mm: Invalidate both kernel and user ASIDs when performing TLBI

From: Will Deacon commit 9b0de864b5bc upstream. Since an mm has both a kernel and a user ASID, we need to ensure that broadcast TLB maintenance targets both address spaces so that things like CoW continue to work with the uaccess primitives in the kernel. Reviewed-by: Mark Rutland Tested-by:

[PATCH 06/29] arm64: factor out entry stack manipulation

From: Mark Rutland commit b11e5759bfac upstream. In subsequent patches, we will detect stack overflow in our exception entry code, by verifying the SP after it has been decremented to make space for the exception regs. This verification code is small, and we can minimize

[PATCH 06/29] arm64: factor out entry stack manipulation

From: Mark Rutland commit b11e5759bfac upstream. In subsequent patches, we will detect stack overflow in our exception entry code, by verifying the SP after it has been decremented to make space for the exception regs. This verification code is small, and we can minimize its impact by placing

[PATCH 01/29] arm64: mm: Use non-global mappings for kernel space

From: Will Deacon commit e046eb0c9bf2 upstream. In preparation for unmapping the kernel whilst running in userspace, make the kernel mappings non-global so we can avoid expensive TLB invalidation on kernel exit to userspace. Reviewed-by: Mark Rutland

[PATCH 01/29] arm64: mm: Use non-global mappings for kernel space

From: Will Deacon commit e046eb0c9bf2 upstream. In preparation for unmapping the kernel whilst running in userspace, make the kernel mappings non-global so we can avoid expensive TLB invalidation on kernel exit to userspace. Reviewed-by: Mark Rutland Tested-by: Laura Abbott Tested-by:

[PATCH 03/29] arm64: mm: Allocate ASIDs in pairs

From: Will Deacon commit 0c8ea531b774 upstream. In preparation for separate kernel/user ASIDs, allocate them in pairs for each mm_struct. The bottom bit distinguishes the two: if it is set, then the ASID will map only userspace. Reviewed-by: Mark Rutland

[PATCH 0/29] arm meltdown fix backporting review for lts 4.9

Hi All, This backport patchset fixed the meltdown issue, it's original branch: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=kpti A few dependency or fixingpatches are also picked up, if they are necessary and no functional changes. The patchset also on repository:

[PATCH 04/29] arm64: mm: Add arm64_kernel_unmapped_at_el0 helper

From: Will Deacon commit fc0e1299da54 upstream. In order for code such as TLB invalidation to operate efficiently when the decision to map the kernel at EL0 is determined at runtime, this patch introduces a helper function, arm64_kernel_unmapped_at_el0, to determine whether

[PATCH 03/29] arm64: mm: Allocate ASIDs in pairs

From: Will Deacon commit 0c8ea531b774 upstream. In preparation for separate kernel/user ASIDs, allocate them in pairs for each mm_struct. The bottom bit distinguishes the two: if it is set, then the ASID will map only userspace. Reviewed-by: Mark Rutland Tested-by: Laura Abbott Tested-by:

[PATCH 0/29] arm meltdown fix backporting review for lts 4.9

Hi All, This backport patchset fixed the meltdown issue, it's original branch: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=kpti A few dependency or fixingpatches are also picked up, if they are necessary and no functional changes. The patchset also on repository:

[PATCH 04/29] arm64: mm: Add arm64_kernel_unmapped_at_el0 helper

From: Will Deacon commit fc0e1299da54 upstream. In order for code such as TLB invalidation to operate efficiently when the decision to map the kernel at EL0 is determined at runtime, this patch introduces a helper function, arm64_kernel_unmapped_at_el0, to determine whether or not the kernel is

Re: [PATCH 4/4] staging: fsl-dpaa2/eth: allow the driver to compile multi-arch

Hi Ioana, I love your patch! Perhaps something to improve: [auto build test WARNING on staging/staging-testing] [also build test WARNING on v4.16-rc3 next-20180227] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com

Re: [PATCH 4/4] staging: fsl-dpaa2/eth: allow the driver to compile multi-arch

Hi Ioana, I love your patch! Perhaps something to improve: [auto build test WARNING on staging/staging-testing] [also build test WARNING on v4.16-rc3 next-20180227] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com

回覆: [PATCH] staging: typec: handle vendor defined part and modify drp toggling flow

Hi Jun, For the questions of drp_toggling, our test is as following: According to TCPCI 4.4.5.2 It is recommended the TCPM write ROLE_CONTROL.DRP=0 before writing to POWER_CONTROL.AutoDischargeDisconnect and starting the DRP toggling using COMMAND.Look4Connection. We've encounter a

回覆: [PATCH] staging: typec: handle vendor defined part and modify drp toggling flow

Hi Jun, For the questions of drp_toggling, our test is as following: According to TCPCI 4.4.5.2 It is recommended the TCPM write ROLE_CONTROL.DRP=0 before writing to POWER_CONTROL.AutoDischargeDisconnect and starting the DRP toggling using COMMAND.Look4Connection. We've encounter a

Re: [RFC PATCH v2] ptr_ring: linked list fallback

On 2018年02月28日 11:28, Jason Wang wrote: Well I believe the main user for this is qdisc, which use skb array. And we can not use what implemented in this patch directly for sk_buff without some changes on the data structure. Why not? skb has next and prev pointers at 1st two fields: struct

Re: [RFC PATCH v2] ptr_ring: linked list fallback

On 2018年02月28日 11:28, Jason Wang wrote: Well I believe the main user for this is qdisc, which use skb array. And we can not use what implemented in this patch directly for sk_buff without some changes on the data structure. Why not? skb has next and prev pointers at 1st two fields: struct

[PATCH v5 1/2] KVM: X86: Introduce kvm_get_msr_feature()

From: Wanpeng Li Introduce kvm_get_msr_feature() to handle the msrs which are supported by different vendors and sharing the same emulation logic. Cc: Paolo Bonzini Cc: Radim Krčmář Cc: Liran Alon Cc:

[PATCH v5 1/2] KVM: X86: Introduce kvm_get_msr_feature()

From: Wanpeng Li Introduce kvm_get_msr_feature() to handle the msrs which are supported by different vendors and sharing the same emulation logic. Cc: Paolo Bonzini Cc: Radim Krčmář Cc: Liran Alon Cc: Nadav Amit Cc: Borislav Petkov Cc: Tom Lendacky Signed-off-by: Wanpeng Li ---

[PATCH v5 2/2] KVM: X86: Allow userspace to define the microcode version

From: Wanpeng Li Linux (among the others) has checks to make sure that certain features aren't enabled on a certain family/model/stepping if the microcode version isn't greater than or equal to a known good version. By exposing the real microcode version, we're

[PATCH v5 2/2] KVM: X86: Allow userspace to define the microcode version

From: Wanpeng Li Linux (among the others) has checks to make sure that certain features aren't enabled on a certain family/model/stepping if the microcode version isn't greater than or equal to a known good version. By exposing the real microcode version, we're preventing buggy guests that

[PATCH v4 19/19] selftests: ftrace: Add a testcase for array type with kprobe_event

Add a testcase for array type with kprobe event. This tests good/bad syntax combinations and also the traced data is correct in several way. If the kernel doesn't support array type, it skips the test as UNSUPPORTED. Signed-off-by: Masami Hiramatsu --- Changes in v4: -

[PATCH v4 19/19] selftests: ftrace: Add a testcase for array type with kprobe_event

Add a testcase for array type with kprobe event. This tests good/bad syntax combinations and also the traced data is correct in several way. If the kernel doesn't support array type, it skips the test as UNSUPPORTED. Signed-off-by: Masami Hiramatsu --- Changes in v4: - Add format field tests.

[PATCH v4 15/19] tracing: probeevent: Add $argN for accessing function args

Add $argN special fetch variable for accessing function arguments. This allows user to trace the Nth argument easily at the function entry. Note that this returns most probably assignment of registers and stacks. In some case, it may not work well. If you need to access correct registers or

[PATCH v4 15/19] tracing: probeevent: Add $argN for accessing function args

Add $argN special fetch variable for accessing function arguments. This allows user to trace the Nth argument easily at the function entry. Note that this returns most probably assignment of registers and stacks. In some case, it may not work well. If you need to access correct registers or

Re: [RFC PATCH v2] ptr_ring: linked list fallback

On 2018年02月28日 01:12, Michael S. Tsirkin wrote: On Tue, Feb 27, 2018 at 10:29:26AM +0800, Jason Wang wrote: On 2018年02月27日 04:34, Michael S. Tsirkin wrote: On Mon, Feb 26, 2018 at 11:15:42AM +0800, Jason Wang wrote: On 2018年02月26日 09:17, Michael S. Tsirkin wrote: So pointer rings work

Re: [RFC PATCH v2] ptr_ring: linked list fallback

On 2018年02月28日 01:12, Michael S. Tsirkin wrote: On Tue, Feb 27, 2018 at 10:29:26AM +0800, Jason Wang wrote: On 2018年02月27日 04:34, Michael S. Tsirkin wrote: On Mon, Feb 26, 2018 at 11:15:42AM +0800, Jason Wang wrote: On 2018年02月26日 09:17, Michael S. Tsirkin wrote: So pointer rings work

[PATCH v3 1/4] mm/sparse: Add a static variable nr_present_sections

It's used to record how many memory sections are marked as present during system boot up, and will be used in the later patch. Signed-off-by: Baoquan He --- mm/sparse.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/mm/sparse.c b/mm/sparse.c index

[PATCH v3 1/4] mm/sparse: Add a static variable nr_present_sections

It's used to record how many memory sections are marked as present during system boot up, and will be used in the later patch. Signed-off-by: Baoquan He --- mm/sparse.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/mm/sparse.c b/mm/sparse.c index 7af5e7a92528..3400c1c02f7a 100644

[PATCH v4 18/19] selftests: ftrace: Add a testcase for $argN with kprobe_event

Add a testcase for array type with kprobe event. This tests whether the traced data is correct or not. If the kernel doesn't support array type, it skips the test as UNSUPPORTED. Signed-off-by: Masami Hiramatsu --- .../ftrace/test.d/kprobe/kprobe_args_argN.tc | 25

[PATCH v4 18/19] selftests: ftrace: Add a testcase for $argN with kprobe_event

Add a testcase for array type with kprobe event. This tests whether the traced data is correct or not. If the kernel doesn't support array type, it skips the test as UNSUPPORTED. Signed-off-by: Masami Hiramatsu --- .../ftrace/test.d/kprobe/kprobe_args_argN.tc | 25

[PATCH v3 3/4] mm/sparse: Add a new parameter 'data_unit_size' for alloc_usemap_and_memmap

It's used to pass the size of map data unit into alloc_usemap_and_memmap, and is preparation for next patch. Signed-off-by: Baoquan He --- mm/sparse.c | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/mm/sparse.c b/mm/sparse.c index

[PATCH v4 17/19] selftests: ftrace: Add a testcase for symbol type

Add a testcase for symbol type with kprobe event. This tests good/bad syntax combinations and also the traced data. If the kernel doesn't support symbol type, it skips the test as UNSUPPORTED. Signed-off-by: Masami Hiramatsu --- Changes in v3: - Use IP/PC register to test

[PATCH v3 3/4] mm/sparse: Add a new parameter 'data_unit_size' for alloc_usemap_and_memmap

It's used to pass the size of map data unit into alloc_usemap_and_memmap, and is preparation for next patch. Signed-off-by: Baoquan He --- mm/sparse.c | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/mm/sparse.c b/mm/sparse.c index 5769a0a79dc1..e1aa2f44530d 100644

[PATCH v4 17/19] selftests: ftrace: Add a testcase for symbol type

Add a testcase for symbol type with kprobe event. This tests good/bad syntax combinations and also the traced data. If the kernel doesn't support symbol type, it skips the test as UNSUPPORTED. Signed-off-by: Masami Hiramatsu --- Changes in v3: - Use IP/PC register to test the symbol type ---

[PATCH v3 2/4] mm/sparsemem: Defer the ms->section_mem_map clearing

In sparse_init(), if CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y, system will allocate one continuous memory chunk for mem maps on one node and populate the relevant page tables to map memory section one by one. If fail to populate for a certain mem section, print warning and its ->section_mem_map

[PATCH v4 16/19] tracing: probeevent: Add array type support

Add array type support for probe events. This allows user to get arraied types from memory address. The array type syntax is TYPE[N] Where TYPE is one of types (u8/16/32/64,s8/16/32/64, x8/16/32/64, symbol, string) and N is a fixed value less than 64. The string array type is a bit

[PATCH v3 0/4] mm/sparse: Optimize memmap allocation during sparse_init()

This is v3 post. V1 can be found here: https://www.spinics.net/lists/linux-mm/msg144486.html In sparse_init(), two temporary pointer arrays, usemap_map and map_map are allocated with the size of NR_MEM_SECTIONS. They are used to store each memory section's usemap and mem map if marked as present.

[PATCH v3 4/4] mm/sparse: Optimize memmap allocation during sparse_init()

In sparse_init(), two temporary pointer arrays, usemap_map and map_map are allocated with the size of NR_MEM_SECTIONS. They are used to store each memory section's usemap and mem map if marked as present. With the help of these two arrays, continuous memory chunk is allocated for usemap and memmap

[PATCH v3 2/4] mm/sparsemem: Defer the ms->section_mem_map clearing

In sparse_init(), if CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y, system will allocate one continuous memory chunk for mem maps on one node and populate the relevant page tables to map memory section one by one. If fail to populate for a certain mem section, print warning and its ->section_mem_map

[PATCH v4 16/19] tracing: probeevent: Add array type support

Add array type support for probe events. This allows user to get arraied types from memory address. The array type syntax is TYPE[N] Where TYPE is one of types (u8/16/32/64,s8/16/32/64, x8/16/32/64, symbol, string) and N is a fixed value less than 64. The string array type is a bit

[PATCH v3 0/4] mm/sparse: Optimize memmap allocation during sparse_init()

This is v3 post. V1 can be found here: https://www.spinics.net/lists/linux-mm/msg144486.html In sparse_init(), two temporary pointer arrays, usemap_map and map_map are allocated with the size of NR_MEM_SECTIONS. They are used to store each memory section's usemap and mem map if marked as present.

[PATCH v3 4/4] mm/sparse: Optimize memmap allocation during sparse_init()

In sparse_init(), two temporary pointer arrays, usemap_map and map_map are allocated with the size of NR_MEM_SECTIONS. They are used to store each memory section's usemap and mem map if marked as present. With the help of these two arrays, continuous memory chunk is allocated for usemap and memmap

[PATCH v4 13/19] tracing: probeevent: Add symbol type

Add "symbol" type to probeevent, which is an alias of u32 or u64 (depends on BITS_PER_LONG). This shows the result value in symbol+offset style. This type is only available with kprobe events. Signed-off-by: Masami Hiramatsu --- Changes in v2: - Add symbol type to README

[PATCH v4 14/19] x86: ptrace: Add function argument access API

Add regs_get_argument() which returns N th argument of the function call. Note that this chooses most probably assignment, in some case it can be incorrect (e.g. passing data structure or floating point etc.) This is expected to be called from kprobes or ftrace with regs where the top of stack is

[PATCH v4 13/19] tracing: probeevent: Add symbol type

Add "symbol" type to probeevent, which is an alias of u32 or u64 (depends on BITS_PER_LONG). This shows the result value in symbol+offset style. This type is only available with kprobe events. Signed-off-by: Masami Hiramatsu --- Changes in v2: - Add symbol type to README file. ---

[PATCH v4 14/19] x86: ptrace: Add function argument access API

Add regs_get_argument() which returns N th argument of the function call. Note that this chooses most probably assignment, in some case it can be incorrect (e.g. passing data structure or floating point etc.) This is expected to be called from kprobes or ftrace with regs where the top of stack is

[PATCH v4 12/19] tracing: probeevent: Unify fetch_insn processing common part

Unify the fetch_insn bottom process (from stage 2: dereference indirect data) from kprobe and uprobe events, since those are mostly same. Signed-off-by: Masami Hiramatsu --- kernel/trace/trace_kprobe.c | 47 +

[PATCH v4 12/19] tracing: probeevent: Unify fetch_insn processing common part

Unify the fetch_insn bottom process (from stage 2: dereference indirect data) from kprobe and uprobe events, since those are mostly same. Signed-off-by: Masami Hiramatsu --- kernel/trace/trace_kprobe.c | 47 + kernel/trace/trace_probe_tmpl.h | 55

[PATCH v4 11/19] tracing: probeevent: Append traceprobe_ for exported function

Append traceprobe_ for exported function set_print_fmt() as same as other functions. Signed-off-by: Masami Hiramatsu --- kernel/trace/trace_kprobe.c |4 ++-- kernel/trace/trace_probe.c |2 +- kernel/trace/trace_probe.h |2 +- kernel/trace/trace_uprobe.c |4

[PATCH v4 11/19] tracing: probeevent: Append traceprobe_ for exported function

Append traceprobe_ for exported function set_print_fmt() as same as other functions. Signed-off-by: Masami Hiramatsu --- kernel/trace/trace_kprobe.c |4 ++-- kernel/trace/trace_probe.c |2 +- kernel/trace/trace_probe.h |2 +- kernel/trace/trace_uprobe.c |4 ++-- 4 files

[PATCH v4 09/19] tracing: probeevent: Unify fetch type tables

Unify {k,u}probe_fetch_type_table to probe_fetch_type_table because the main difference of those type tables (fetcharg methods) are gone. Now we can consolidate it. Signed-off-by: Masami Hiramatsu --- kernel/trace/trace_kprobe.c | 27 +-

[PATCH v4 10/19] tracing: probeevent: Return consumed bytes of dynamic area

Cleanup string fetching routine so that returns the consumed bytes of dynamic area and store the string information as data_loc format instead of data_rloc. This simplifies the fetcharg loop. Signed-off-by: Masami Hiramatsu --- kernel/trace/trace_kprobe.c | 51

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