* David Wang wrote:
> This patch set is to provide MCA support on new Centaur CPU.
>
> The first patch is used to tell the kernel that newer Centaur CPU support
> MCE broadcasting.
>
> The second patch is used to tell the kernel that newer Centaur CPU support
> CMCI.
* David Wang wrote:
> This patch set is to provide MCA support on new Centaur CPU.
>
> The first patch is used to tell the kernel that newer Centaur CPU support
> MCE broadcasting.
>
> The second patch is used to tell the kernel that newer Centaur CPU support
> CMCI.
>
> David Wang (2):
On Thu, 29 Mar 2018 14:42:02 +0530
Shreeya Patel wrote:
> Have indentation in field definitions to make them
> clearly different from the register addresses.
>
> Signed-off-by: Shreeya Patel
Applied to the togreg branch of iio.git and
On Thu, 29 Mar 2018 14:42:02 +0530
Shreeya Patel wrote:
> Have indentation in field definitions to make them
> clearly different from the register addresses.
>
> Signed-off-by: Shreeya Patel
Applied to the togreg branch of iio.git and pushed out as testing
for the autobuilders to play with it.
Sat, Mar 24, 2018 at 11:56:33AM CET, rahul.lakkire...@chelsio.com wrote:
>Add a new module crashdd that exports the /sys/kernel/crashdd/
>directory in second kernel, containing collected hardware/firmware
>dumps.
>
>The sequence of actions done by device drivers to append their device
>specific
Sat, Mar 24, 2018 at 11:56:33AM CET, rahul.lakkire...@chelsio.com wrote:
>Add a new module crashdd that exports the /sys/kernel/crashdd/
>directory in second kernel, containing collected hardware/firmware
>dumps.
>
>The sequence of actions done by device drivers to append their device
>specific
On 03/30/18 17:48, Jonathan Cameron wrote:
> On Mon, 26 Mar 2018 16:46:27 +0800
> Yixun Lan wrote:
>
>> Extract and promote common adc platform data into a new structure,
>> to make it better share the info between several SoCs,
>> this will avoid duplicating the code all
On 03/30/18 17:48, Jonathan Cameron wrote:
> On Mon, 26 Mar 2018 16:46:27 +0800
> Yixun Lan wrote:
>
>> Extract and promote common adc platform data into a new structure,
>> to make it better share the info between several SoCs,
>> this will avoid duplicating the code all over the place,
>> Save
On Thu 2018-03-29 14:56:13, Tony Lindgren wrote:
> * Pavel Machek [180329 18:41]:
> > Thanks. I got call working including outgoing audio: in capture
> > settings, right->mic 1, Mic1 + Mic2 in alsamixer -> 100%. But I had
> > the other phone muted, so I don't yet know if such call
On Thu 2018-03-29 14:56:13, Tony Lindgren wrote:
> * Pavel Machek [180329 18:41]:
> > Thanks. I got call working including outgoing audio: in capture
> > settings, right->mic 1, Mic1 + Mic2 in alsamixer -> 100%. But I had
> > the other phone muted, so I don't yet know if such call would be of
> >
On Wed 21-03-18 15:57:59, Dan Williams wrote:
> The HMM sub-system extended dev_pagemap to arrange a callback when a
> dev_pagemap managed page is freed. Since a dev_pagemap page is free /
> idle when its reference count is 1 it requires an additional branch to
> check the page-type at put_page()
On Wed 21-03-18 15:57:59, Dan Williams wrote:
> The HMM sub-system extended dev_pagemap to arrange a callback when a
> dev_pagemap managed page is freed. Since a dev_pagemap page is free /
> idle when its reference count is 1 it requires an additional branch to
> check the page-type at put_page()
Current suspend/resume implementation reuses the mvneta_open() and
mvneta_close(), but it could be optimized to take only necessary
actions during suspend/resume.
One obvious problem of current implementation is: after hundreds of
system suspend/resume cycles, the resume of mvneta could fail due
Current suspend/resume implementation reuses the mvneta_open() and
mvneta_close(), but it could be optimized to take only necessary
actions during suspend/resume.
One obvious problem of current implementation is: after hundreds of
system suspend/resume cycles, the resume of mvneta could fail due
This is to prepare the suspend/resume improvement in next patch. The
SW parts can be optimized out during resume.
As for rxq handling during suspend, we'd like to drop packets by
calling mvneta_rxq_drop_pkts() which is both SW and HW operation,
so we don't split rxq deinit.
Signed-off-by:
This is to prepare the suspend/resume improvement in next patch. The
SW parts can be optimized out during resume.
As for rxq handling during suspend, we'd like to drop packets by
calling mvneta_rxq_drop_pkts() which is both SW and HW operation,
so we don't split rxq deinit.
Signed-off-by:
This series tries to optimize the mvneta's suspend/resume
implementation by only taking necessary actions.
Since v1:
- unify ret check
- try best to keep the suspend/resume behavior
- split txq deinit into sw/hw parts as well
- adjust mvneta_stop_dev() location
I didn't add Thomas's Ack tag
This series tries to optimize the mvneta's suspend/resume
implementation by only taking necessary actions.
Since v1:
- unify ret check
- try best to keep the suspend/resume behavior
- split txq deinit into sw/hw parts as well
- adjust mvneta_stop_dev() location
I didn't add Thomas's Ack tag
On Fri, Mar 30, 2018 at 05:53:41PM +0800, David Wang wrote:
> This patch is used to tell the kernel that newer Centaur CPU support MCE
> broadcasting.
>
> Signed-off-by: David Wang
> ---
> arch/x86/kernel/cpu/mcheck/mce.c | 11 +++
> 1 file changed, 11
On Fri, Mar 30, 2018 at 05:53:41PM +0800, David Wang wrote:
> This patch is used to tell the kernel that newer Centaur CPU support MCE
> broadcasting.
>
> Signed-off-by: David Wang
> ---
> arch/x86/kernel/cpu/mcheck/mce.c | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git
On Monday, March 5, 2018 9:47:46 AM CEST Ganesh Mahendran wrote:
> single_open() interface requires that the whole output must
> fit into a single buffer. This will lead to timeout when
> system memory is not in a good situation.
>
> This patch use seq_open() to show wakeup stats. This method
>
On Monday, March 5, 2018 9:47:46 AM CEST Ganesh Mahendran wrote:
> single_open() interface requires that the whole output must
> fit into a single buffer. This will lead to timeout when
> system memory is not in a good situation.
>
> This patch use seq_open() to show wakeup stats. This method
>
Hello,
On Fri, 30 Mar 2018 12:05:31 +0200, Gregory CLEMENT wrote:
> From: Yelena Krivosheev
>
> In mvneta_port_up() we enable relevant RX and TX port queues by write
> queues bit map to an appropriate register.
>
> q_map must be ZERO in the beginning of this process.
>
>
Hello,
On Fri, 30 Mar 2018 12:05:31 +0200, Gregory CLEMENT wrote:
> From: Yelena Krivosheev
>
> In mvneta_port_up() we enable relevant RX and TX port queues by write
> queues bit map to an appropriate register.
>
> q_map must be ZERO in the beginning of this process.
>
> Signed-off-by: Yelena
Local variable irq is not used. Remove it.
Signed-off-by: Nguyen Phan Quang Minh
---
drivers/staging/fsl-dpaa2/ethsw/ethsw.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/staging/fsl-dpaa2/ethsw/ethsw.c
b/drivers/staging/fsl-dpaa2/ethsw/ethsw.c
index
Local variable irq is not used. Remove it.
Signed-off-by: Nguyen Phan Quang Minh
---
drivers/staging/fsl-dpaa2/ethsw/ethsw.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/staging/fsl-dpaa2/ethsw/ethsw.c
b/drivers/staging/fsl-dpaa2/ethsw/ethsw.c
index c723a04bc3d6..a698498b8537
On Friday, March 23, 2018 11:30:31 AM CEST George Cherian wrote:
> With commit e948bc8fbee0 ("cpufreq: Cap the default transition delay
> value to 10 ms") the cpufreq was not honouring the delay passed via
> ACPI (PCCT). Due to which on ARM based platforms using CPPC the cpufreq
> governor tries
On Friday, March 23, 2018 11:30:31 AM CEST George Cherian wrote:
> With commit e948bc8fbee0 ("cpufreq: Cap the default transition delay
> value to 10 ms") the cpufreq was not honouring the delay passed via
> ACPI (PCCT). Due to which on ARM based platforms using CPPC the cpufreq
> governor tries
* Dominik Brodowski wrote:
> A few questions remain, from important stuff to bikeshedding:
>
> 1) Is it acceptable to pass the existing struct pt_regs to the sys_*()
>kernel functions in emulate_vsyscall(), or should it use a hand-crafted
>struct pt_regs
* Dominik Brodowski wrote:
> A few questions remain, from important stuff to bikeshedding:
>
> 1) Is it acceptable to pass the existing struct pt_regs to the sys_*()
>kernel functions in emulate_vsyscall(), or should it use a hand-crafted
>struct pt_regs instead?
I think so: we
* Dominik Brodowski wrote:
> .endif
> pushq \rdx/* pt_regs->dx */
> + xorl%edx, %edx /* nosepc dx */
> pushq %rcx/* pt_regs->cx */
> + xorl%ecx, %ecx /* nosepc cx */
> pushq \rax
* Dominik Brodowski wrote:
> .endif
> pushq \rdx/* pt_regs->dx */
> + xorl%edx, %edx /* nosepc dx */
> pushq %rcx/* pt_regs->cx */
> + xorl%ecx, %ecx /* nosepc cx */
> pushq \rax/* pt_regs->ax */
>
On Tuesday, March 27, 2018 3:56:40 PM CEST Lenny Szubowicz wrote:
> Fix once per second (round_robin_time) memory leak of about 1 KB in
> each acpi_pad kernel idling thread that is activated.
>
> Found by testing with kmemleak.
>
> Signed-off-by: Lenny Szubowicz
> ---
>
On Tuesday, March 27, 2018 3:56:40 PM CEST Lenny Szubowicz wrote:
> Fix once per second (round_robin_time) memory leak of about 1 KB in
> each acpi_pad kernel idling thread that is activated.
>
> Found by testing with kmemleak.
>
> Signed-off-by: Lenny Szubowicz
> ---
> drivers/acpi/acpi_pad.c
On Wednesday, March 28, 2018 7:01:10 PM CEST Mario Limonciello wrote:
> This file is used both for setting the wakeup device without kernel
> command line as well as for actually waking the system (when appropriate
> swap header is in place).
>
> To avoid confusion on incorrect logs in system log
On Wednesday, March 28, 2018 7:01:10 PM CEST Mario Limonciello wrote:
> This file is used both for setting the wakeup device without kernel
> command line as well as for actually waking the system (when appropriate
> swap header is in place).
>
> To avoid confusion on incorrect logs in system log
From: Yelena Krivosheev
In mvneta_port_up() we enable relevant RX and TX port queues by write
queues bit map to an appropriate register.
q_map must be ZERO in the beginning of this process.
Signed-off-by: Yelena Krivosheev
Signed-off-by: Gregory CLEMENT
From: Yelena Krivosheev
In mvneta_port_up() we enable relevant RX and TX port queues by write
queues bit map to an appropriate register.
q_map must be ZERO in the beginning of this process.
Signed-off-by: Yelena Krivosheev
Signed-off-by: Gregory CLEMENT
---
STM32 Timers can support up to 7 DMA requests:
- 4 channels, update, compare and trigger.
Optionally request part, or all DMAs from stm32-timers MFD core.
Also add routine to implement burst reads using DMA from timer registers.
This is exported. So, it can be used by child drivers, PWM capture
STM32 Timers can support up to 7 DMA requests:
- 4 channels, update, compare and trigger.
Optionally request part, or all DMAs from stm32-timers MFD core.
Also add routine to implement burst reads using DMA from timer registers.
This is exported. So, it can be used by child drivers, PWM capture
On Fri, Mar 30, 2018 at 10:29:21AM +0900, Minchan Kim wrote:
> Hi Ganesh,
>
> On Fri, Mar 30, 2018 at 09:21:55AM +0800, Ganesh Mahendran wrote:
> > 2018-03-29 14:54 GMT+08:00 Minchan Kim :
> > > binder_update_page_range needs down_write of mmap_sem because
> > > vm_insert_page
Currently, capture is based on timeout window to configure prescaler.
PWM capture framework provides 1s window at the time of writing.
There's place for improvement, after input signal has been captured once:
- Finer tune counter clock prescaler, by using 1st capture result (with
arbitrary
On Fri, Mar 30, 2018 at 10:29:21AM +0900, Minchan Kim wrote:
> Hi Ganesh,
>
> On Fri, Mar 30, 2018 at 09:21:55AM +0800, Ganesh Mahendran wrote:
> > 2018-03-29 14:54 GMT+08:00 Minchan Kim :
> > > binder_update_page_range needs down_write of mmap_sem because
> > > vm_insert_page need to change
Currently, capture is based on timeout window to configure prescaler.
PWM capture framework provides 1s window at the time of writing.
There's place for improvement, after input signal has been captured once:
- Finer tune counter clock prescaler, by using 1st capture result (with
arbitrary
Add support for PMW input mode on pwm-stm32. STM32 timers support
period and duty cycle capture as long as they have at least two PWM
channels. One capture channel is used for period (rising-edge), one
for duty-cycle (falling-edge).
When there's only one channel available, only period can be
Add support for PMW input mode on pwm-stm32. STM32 timers support
period and duty cycle capture as long as they have at least two PWM
channels. One capture channel is used for period (rising-edge), one
for duty-cycle (falling-edge).
When there's only one channel available, only period can be
Enable pwm3 input capture on stm32f429i-eval, by using DMA.
Signed-off-by: Fabrice Gasnier
Reviewed-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32429i-eval.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git
Enable pwm3 input capture on stm32f429i-eval, by using DMA.
Signed-off-by: Fabrice Gasnier
Reviewed-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32429i-eval.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
Using input prescaler, capture unit will trigger DMA once every
configurable /2, /4 or /8 events (rising edge). This helps improve
period (only) capture accuracy at high rates.
Signed-off-by: Fabrice Gasnier
Reviewed-by: Benjamin Gaignard
Using input prescaler, capture unit will trigger DMA once every
configurable /2, /4 or /8 events (rising edge). This helps improve
period (only) capture accuracy at high rates.
Signed-off-by: Fabrice Gasnier
Reviewed-by: Benjamin Gaignard
Acked-by: Thierry Reding
---
Changes in v2:
- Adopt DMA
This series adds support for capture to stm32-pwm driver.
Capture is based on DMAs.
- First two patches add support for requesting DMAs to MFD core
- Next three patches add support for capture to stm32-pwm driver
- This has been tested on stm32429i-eval board.
---
Changes in v3:
- Dropped 2
This series adds support for capture to stm32-pwm driver.
Capture is based on DMAs.
- First two patches add support for requesting DMAs to MFD core
- Next three patches add support for capture to stm32-pwm driver
- This has been tested on stm32429i-eval board.
---
Changes in v3:
- Dropped 2
Add support for DMAs to STM32 timers. STM32 Timers can support up to 7
dma requests: up to 4 channels, update, compare and trigger.
DMAs may be used to transfer data from pwm capture for instance.
DMA support is made optional, PWM capture support is also an option.
This is much more wise
Add support for DMAs to STM32 timers. STM32 Timers can support up to 7
dma requests: up to 4 channels, update, compare and trigger.
DMAs may be used to transfer data from pwm capture for instance.
DMA support is made optional, PWM capture support is also an option.
This is much more wise
On Fri, Mar 30, 2018 at 12:07:35AM -0700, Quytelda Kahja wrote:
> The "_t" suffix is not needed for structure names in this driver, and is a
> reflection of an older typedef system that is no longer in place. Replace
> all occurences of 'struct hostif_mib_set_confirm_t' with 'struct
>
On Fri, Mar 30, 2018 at 12:07:35AM -0700, Quytelda Kahja wrote:
> The "_t" suffix is not needed for structure names in this driver, and is a
> reflection of an older typedef system that is no longer in place. Replace
> all occurences of 'struct hostif_mib_set_confirm_t' with 'struct
>
Lo! On 27.03.2018 20:33, Thorsten Leemhuis wrote:
> On 19.03.2018 16:49, Sasha Levin wrote:
>> From: Christoph Hellwig
>> [ Upstream commit 84676c1f21e8ff54befe985f4f14dc1edc10046b ]
> TWIMC: That commit (also reported by autosel for 4.14) triggered a
> regression in 4.16 reported by
Lo! On 27.03.2018 20:33, Thorsten Leemhuis wrote:
> On 19.03.2018 16:49, Sasha Levin wrote:
>> From: Christoph Hellwig
>> [ Upstream commit 84676c1f21e8ff54befe985f4f14dc1edc10046b ]
> TWIMC: That commit (also reported by autosel for 4.14) triggered a
> regression in 4.16 reported by Artem
On Fri 2018-03-30 12:07:58, Ilya Smith wrote:
> Hi
>
> > On 30 Mar 2018, at 10:55, Pavel Machek wrote:
> >
> > Hi!
> >
> >> Current implementation doesn't randomize address returned by mmap.
> >> All the entropy ends with choosing mmap_base_addr at the process
> >> creation.
On Fri 2018-03-30 12:07:58, Ilya Smith wrote:
> Hi
>
> > On 30 Mar 2018, at 10:55, Pavel Machek wrote:
> >
> > Hi!
> >
> >> Current implementation doesn't randomize address returned by mmap.
> >> All the entropy ends with choosing mmap_base_addr at the process
> >> creation. After that mmap
This patch allows placing more than one flash chip on the qspi bus
by checking which spi device has been memory-mapped and remapping
if necessary.
Signed-off-by: Arkadiusz Kwiatkowski
---
drivers/spi/spi-ti-qspi.c | 16 ++--
1 file changed, 10
This patch allows placing more than one flash chip on the qspi bus
by checking which spi device has been memory-mapped and remapping
if necessary.
Signed-off-by: Arkadiusz Kwiatkowski
---
drivers/spi/spi-ti-qspi.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff
This commit fixes the order of parameters passed to regmap_update_bits
function inside spi-ti-qspi driver. Accidentally the code worked
correctly when cs=0, but it is not the case for other values.
Signed-off-by: Arkadiusz Kwiatkowski
---
This commit fixes the order of parameters passed to regmap_update_bits
function inside spi-ti-qspi driver. Accidentally the code worked
correctly when cs=0, but it is not the case for other values.
Signed-off-by: Arkadiusz Kwiatkowski
---
drivers/spi/spi-ti-qspi.c | 6 +++---
1 file changed, 3
This patch set is to provide MCA support on new Centaur CPU.
The first patch is used to tell the kernel that newer Centaur CPU support
MCE broadcasting.
The second patch is used to tell the kernel that newer Centaur CPU support
CMCI.
David Wang (2):
x86/mce: new centaur CPUs support MCE
This patch is used to tell the kernel that centaur CPUs support CMCI
mechanism which is compatible with INTEL CMCI.
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/mcheck/mce.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c
This patch is used to tell the kernel that newer Centaur CPU support MCE
broadcasting.
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/mcheck/mce.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c
This patch set is to provide MCA support on new Centaur CPU.
The first patch is used to tell the kernel that newer Centaur CPU support
MCE broadcasting.
The second patch is used to tell the kernel that newer Centaur CPU support
CMCI.
David Wang (2):
x86/mce: new centaur CPUs support MCE
This patch is used to tell the kernel that centaur CPUs support CMCI
mechanism which is compatible with INTEL CMCI.
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/mcheck/mce.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c
This patch is used to tell the kernel that newer Centaur CPU support MCE
broadcasting.
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/mcheck/mce.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index
On Tue, Mar 20, 2018 at 10:35:47AM -0700, Joe Perches wrote:
> To make the test a bit clearer and to reduce object size a little.
>
> Miscellanea:
>
> o remove now unnecessary static const array
>
> $ size ip_set_hash_mac.o*
>text data bss dec hex filename
> 22822
On Tue, Mar 20, 2018 at 10:35:47AM -0700, Joe Perches wrote:
> To make the test a bit clearer and to reduce object size a little.
>
> Miscellanea:
>
> o remove now unnecessary static const array
>
> $ size ip_set_hash_mac.o*
>text data bss dec hex filename
> 22822
On Wed, Mar 21, 2018 at 04:03:22AM -0700, Joe Perches wrote:
> Instead of unnecessary const declarations, use the generic functions to
> save a little object space.
>
> $ size net/bridge/netfilter/ebt_stp.o*
>text data bss dec hex filename
>1250 144 0
On Wed, Mar 21, 2018 at 04:03:22AM -0700, Joe Perches wrote:
> Instead of unnecessary const declarations, use the generic functions to
> save a little object space.
>
> $ size net/bridge/netfilter/ebt_stp.o*
>text data bss dec hex filename
>1250 144 0
From: Rafael J. Wysocki
The intel_pstate driver doesn't use debugfs any more, so drop
linux/debugfs.h from the list of included headers in it.
Signed-off-by: Rafael J. Wysocki
---
drivers/cpufreq/intel_pstate.c |1 -
1 file changed,
From: Rafael J. Wysocki
The intel_pstate driver doesn't use debugfs any more, so drop
linux/debugfs.h from the list of included headers in it.
Signed-off-by: Rafael J. Wysocki
---
drivers/cpufreq/intel_pstate.c |1 -
1 file changed, 1 deletion(-)
Index:
On Mon, 26 Mar 2018 16:46:29 +0800
Yixun Lan wrote:
> From: Xingyu Chen
>
> Add the SAR ADC driver for the Amlogic Meson-AXG SoC.
>
> Signed-off-by: Xingyu Chen
Applied to the togreg branch of iio.git and pushed out as
On Mon, 26 Mar 2018 16:46:29 +0800
Yixun Lan wrote:
> From: Xingyu Chen
>
> Add the SAR ADC driver for the Amlogic Meson-AXG SoC.
>
> Signed-off-by: Xingyu Chen
Applied to the togreg branch of iio.git and pushed out as testing
for the autobuilders to play with it.
Thanks,
Jonathan
> ---
>
On Thu, Mar 29, 2018 at 12:39:50AM +0530, Arushi Singhal wrote:
> Merge assignment with return statement to directly return the value.
Applied, thanks Arushi.
On Thu, Mar 29, 2018 at 12:39:50AM +0530, Arushi Singhal wrote:
> Merge assignment with return statement to directly return the value.
Applied, thanks Arushi.
Hi Julia,
On Thursday, March 29, 2018 9:12:06 PM CEST Julia Lawall wrote:
> Use DEFINE_DEBUGFS_ATTRIBUTE rather than DEFINE_SIMPLE_ATTRIBUTE
> for debugfs files.
>
> Semantic patch information:
> Rationale: DEFINE_SIMPLE_ATTRIBUTE + debugfs_create_file()
> imposes some significant overhead
Hi Julia,
On Thursday, March 29, 2018 9:12:06 PM CEST Julia Lawall wrote:
> Use DEFINE_DEBUGFS_ATTRIBUTE rather than DEFINE_SIMPLE_ATTRIBUTE
> for debugfs files.
>
> Semantic patch information:
> Rationale: DEFINE_SIMPLE_ATTRIBUTE + debugfs_create_file()
> imposes some significant overhead
On Tue, 27 Mar 2018 10:07:30 -0500
Rob Herring wrote:
> On Mon, Mar 26, 2018 at 04:46:28PM +0800, Yixun Lan wrote:
> > From: Xingyu Chen
> >
> > Update the documentation to expicitly support the Meson-AXG SoC.
> >
> > Signed-off-by: Xingyu Chen
On Tue, 27 Mar 2018 10:07:30 -0500
Rob Herring wrote:
> On Mon, Mar 26, 2018 at 04:46:28PM +0800, Yixun Lan wrote:
> > From: Xingyu Chen
> >
> > Update the documentation to expicitly support the Meson-AXG SoC.
> >
> > Signed-off-by: Xingyu Chen
> > ---
> >
Hello,
On Fri, 30 Mar 2018 17:15:47 +0800, Jisheng Zhang wrote:
> > > + cpuhp_state_remove_instance_nocalls(online_hpstate,
> > > + >node_online);
> > > + cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
> > > +
Hello,
On Fri, 30 Mar 2018 17:15:47 +0800, Jisheng Zhang wrote:
> > > + cpuhp_state_remove_instance_nocalls(online_hpstate,
> > > + >node_online);
> > > + cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
> > > +
On Mon, 26 Mar 2018 16:46:27 +0800
Yixun Lan wrote:
> Extract and promote common adc platform data into a new structure,
> to make it better share the info between several SoCs,
> this will avoid duplicating the code all over the place,
> Save a few memory and make the
On Mon, 26 Mar 2018 16:46:27 +0800
Yixun Lan wrote:
> Extract and promote common adc platform data into a new structure,
> to make it better share the info between several SoCs,
> this will avoid duplicating the code all over the place,
> Save a few memory and make the code more maintainable.
>
Add clock lines for PCI-express and SATA controllers implemented on
UniPhier SoCs, and additional clock lines for ethernet controller on Pro4.
Kunihiko Hayashi (3):
clk: uniphier: add PCIe clock control support
clk: uniphier: add SATA clock control support
clk: uniphier: add additional
Add clock lines for PCI-express and SATA controllers implemented on
UniPhier SoCs, and additional clock lines for ethernet controller on Pro4.
Kunihiko Hayashi (3):
clk: uniphier: add PCIe clock control support
clk: uniphier: add SATA clock control support
clk: uniphier: add additional
Add reset lines for SATA controller on UniPhier SoCs.
This adds support for Pro4 and PXs3 in addition to PXs2.
And this changes the ID of the reset line for SATA-PHY on PXs2.
Since some SoCs have two controller instances with a common PHY, this moves
the ID of SATA-PHY for consistency.
Add reset lines for SATA controller on UniPhier SoCs.
This adds support for Pro4 and PXs3 in addition to PXs2.
And this changes the ID of the reset line for SATA-PHY on PXs2.
Since some SoCs have two controller instances with a common PHY, this moves
the ID of SATA-PHY for consistency.
Add reset lines for PCIe controller on UniPhier SoCs. This adds support for
Pro5, LD20 and PXs3.
Signed-off-by: Kunihiko Hayashi
---
drivers/reset/reset-uniphier.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/reset/reset-uniphier.c
Add reset lines for PCIe controller on UniPhier SoCs. This adds support for
Pro5, LD20 and PXs3.
Signed-off-by: Kunihiko Hayashi
---
drivers/reset/reset-uniphier.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index
Add clock control for PCIe controller on UniPhier SoCs. This adds
support for Pro5, LD20 and PXs3.
Signed-off-by: Kunihiko Hayashi
---
drivers/clk/uniphier/clk-uniphier-sys.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
Add clock control for PCIe controller on UniPhier SoCs. This adds
support for Pro5, LD20 and PXs3.
Signed-off-by: Kunihiko Hayashi
---
drivers/clk/uniphier/clk-uniphier-sys.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c
add reset lines for PCI-express and SATA controllers implemented on
UniPhier SoCs.
Kunihiko Hayashi (2):
reset: uniphier: add PCIe reset control support
reset: uniphier: add SATA reset control support and change SATA-PHY ID
drivers/reset/reset-uniphier.c | 11 ++-
1 file changed, 10
add reset lines for PCI-express and SATA controllers implemented on
UniPhier SoCs.
Kunihiko Hayashi (2):
reset: uniphier: add PCIe reset control support
reset: uniphier: add SATA reset control support and change SATA-PHY ID
drivers/reset/reset-uniphier.c | 11 ++-
1 file changed, 10
Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
and these are mandatory to activate the ethernet controller. This adds
support for the clock lines.
Signed-off-by: Kunihiko Hayashi
---
drivers/clk/uniphier/clk-uniphier-sys.c | 3 +++
1 file
Add clock control for SATA controller on UniPhier SoCs. This adds
support for PXs2, LD20 and PXs3.
Signed-off-by: Kunihiko Hayashi
---
drivers/clk/uniphier/clk-uniphier-sys.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
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