Re: [PATCH 6/9] iommu/vt-d: Allocate and free pasid table

Hi, On 05/01/2018 05:22 PM, Liu, Yi L wrote: >> From: Lu Baolu [mailto:baolu...@linux.intel.com] >> Sent: Tuesday, April 17, 2018 11:03 AM >> >> This patch allocates PASID table for a domain at the time when >> it is being created (if any devices using this domain supports >> PASID feature), and

Re: [PATCH 6/9] iommu/vt-d: Allocate and free pasid table

Hi, On 05/01/2018 05:22 PM, Liu, Yi L wrote: >> From: Lu Baolu [mailto:baolu...@linux.intel.com] >> Sent: Tuesday, April 17, 2018 11:03 AM >> >> This patch allocates PASID table for a domain at the time when >> it is being created (if any devices using this domain supports >> PASID feature), and

[PATCH v5 04/28] fpga: mgr: add compat_id support

This patch introduces compat_id support to fpga manager, it adds a fpga_compat_id pointer to fpga manager data structure to allow fpga manager drivers to save the compatibility id. This compat_id could be used for compatibility checking before doing partial reconfiguration to associated fpga

[PATCH v5 04/28] fpga: mgr: add compat_id support

This patch introduces compat_id support to fpga manager, it adds a fpga_compat_id pointer to fpga manager data structure to allow fpga manager drivers to save the compatibility id. This compat_id could be used for compatibility checking before doing partial reconfiguration to associated fpga

Re: [PATCH 5/9] iommu/vt-d: Per domain pasid table interfaces

Hi Yi, Thank you very much for reviewing my patches. On 05/01/2018 05:22 PM, Liu, Yi L wrote: >> From: Lu Baolu [mailto:baolu...@linux.intel.com] >> Sent: Tuesday, April 17, 2018 11:03 AM >> >> This patch adds the interfaces for per domain pasid table >> management. Currently we allocate one

[PATCH v5 06/28] fpga: add device feature list support

Device Feature List (DFL) defines a feature list structure that creates a link list of feature headers within the MMIO space to provide an extensible way of adding features. This patch introduces a kernel module to provide basic infrastructure to support FPGA devices which implement the Device

[PATCH v5 02/28] fpga: mgr: add region_id to fpga_image_info

This patch adds region_id to fpga_image_info data structure, it allows driver to pass region id information to fpga-mgr via fpga_image_info for fpga reconfiguration function. Signed-off-by: Wu Hao Acked-by: Moritz Fischer Acked-by: Alan Tull

Re: [PATCH 5/9] iommu/vt-d: Per domain pasid table interfaces

Hi Yi, Thank you very much for reviewing my patches. On 05/01/2018 05:22 PM, Liu, Yi L wrote: >> From: Lu Baolu [mailto:baolu...@linux.intel.com] >> Sent: Tuesday, April 17, 2018 11:03 AM >> >> This patch adds the interfaces for per domain pasid table >> management. Currently we allocate one

[PATCH v5 06/28] fpga: add device feature list support

Device Feature List (DFL) defines a feature list structure that creates a link list of feature headers within the MMIO space to provide an extensible way of adding features. This patch introduces a kernel module to provide basic infrastructure to support FPGA devices which implement the Device

[PATCH v5 02/28] fpga: mgr: add region_id to fpga_image_info

This patch adds region_id to fpga_image_info data structure, it allows driver to pass region id information to fpga-mgr via fpga_image_info for fpga reconfiguration function. Signed-off-by: Wu Hao Acked-by: Moritz Fischer Acked-by: Alan Tull --- v3: add one line comment for region_id v4: add

[PATCH v5 08/28] fpga: dfl: add dfl_fpga_cdev_find_port

For feature devices, we need a method to find the port dedicated to the device. This patch adds a function dfl_fpga_cdev_find_port for this purpose. e.g FPGA Management Engine (FME) Partial Reconfiguration sub feature, it uses this function to find dedicated port on the device for PR function

[PATCH v5 08/28] fpga: dfl: add dfl_fpga_cdev_find_port

For feature devices, we need a method to find the port dedicated to the device. This patch adds a function dfl_fpga_cdev_find_port for this purpose. e.g FPGA Management Engine (FME) Partial Reconfiguration sub feature, it uses this function to find dedicated port on the device for PR function

[PATCH v5 03/28] fpga: mgr: add status for fpga-manager

This patch adds status sysfs interface for fpga manager, it's a read only interface which allows user to get fpga manager status, including full/partial reconfiguration error and other status information. It adds a status callback to fpga_manager_ops too, allows each fpga_manager driver to define

[PATCH v5 07/28] fpga: dfl: add chardev support for feature devices

For feature devices drivers, both the FPGA Management Engine (FME) and Accelerated Function Unit (AFU) driver need to expose user interfaces via the device file, for example, mmap and ioctls. This patch adds chardev support in the dfl driver for feature devices, FME and AFU. It reserves the

[PATCH v5 03/28] fpga: mgr: add status for fpga-manager

This patch adds status sysfs interface for fpga manager, it's a read only interface which allows user to get fpga manager status, including full/partial reconfiguration error and other status information. It adds a status callback to fpga_manager_ops too, allows each fpga_manager driver to define

[PATCH v5 07/28] fpga: dfl: add chardev support for feature devices

For feature devices drivers, both the FPGA Management Engine (FME) and Accelerated Function Unit (AFU) driver need to expose user interfaces via the device file, for example, mmap and ioctls. This patch adds chardev support in the dfl driver for feature devices, FME and AFU. It reserves the

[PATCH v5 10/28] fpga: dfl: add dfl_fpga_port_ops support.

In some cases, other DFL driver modules may need to access some port operations, e.g disable / enable port for partial reconfiguration in FME module. In order to avoid dependency between port and FME modules, this patch introduces the dfl_fpga_port_ops support in DFL framework. A global

[PATCH v5 10/28] fpga: dfl: add dfl_fpga_port_ops support.

In some cases, other DFL driver modules may need to access some port operations, e.g disable / enable port for partial reconfiguration in FME module. In order to avoid dependency between port and FME modules, this patch introduces the dfl_fpga_port_ops support in DFL framework. A global

[PATCH v5 14/28] fpga: dfl: add FPGA Management Engine driver basic framework

From: Kang Luwei The FPGA Management Engine (FME) provides power, thermal management, performance counters, partial reconfiguration and other functions. For each function, it is packaged into a private feature linked to the FME feature device in the 'Device Feature List'.

[PATCH v5 14/28] fpga: dfl: add FPGA Management Engine driver basic framework

From: Kang Luwei The FPGA Management Engine (FME) provides power, thermal management, performance counters, partial reconfiguration and other functions. For each function, it is packaged into a private feature linked to the FME feature device in the 'Device Feature List'. It's a platform device

[PATCH v5 11/28] fpga: dfl: add dfl_fpga_check_port_id function.

This patch adds one common function in DFL framework. It uses port_ops get_id callback to get port id and compare it with given value. This function could be used as match function of the dfl_fpga_cdev_find_port function. Signed-off-by: Wu Hao --- drivers/fpga/dfl.c | 22

[PATCH v5 11/28] fpga: dfl: add dfl_fpga_check_port_id function.

This patch adds one common function in DFL framework. It uses port_ops get_id callback to get port id and compare it with given value. This function could be used as match function of the dfl_fpga_cdev_find_port function. Signed-off-by: Wu Hao --- drivers/fpga/dfl.c | 22 ++

[PATCH v2 0/2] usb: dwc2: fix isoc split in transfer issue

This patch fix dma unaligned problem and data lost problem for isoc split in transfer. Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb fs audio device (Plantronics headset) to capture and playback. William Wu (2): usb: dwc2: alloc dma aligned buffer for isoc split in usb:

[PATCH v2 0/2] usb: dwc2: fix isoc split in transfer issue

This patch fix dma unaligned problem and data lost problem for isoc split in transfer. Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb fs audio device (Plantronics headset) to capture and playback. William Wu (2): usb: dwc2: alloc dma aligned buffer for isoc split in usb:

[PATCH v2 1/2] usb: dwc2: alloc dma aligned buffer for isoc split in

The commit 3bc04e28a030 ("usb: dwc2: host: Get aligned DMA in a more supported way") rips out a lot of code to simply the allocation of aligned DMA. However, it also introduces a new issue when use isoc split in transfer. In my test case, I connect the dwc2 controller with an usb hs Hub

[PATCH v2 1/2] usb: dwc2: alloc dma aligned buffer for isoc split in

The commit 3bc04e28a030 ("usb: dwc2: host: Get aligned DMA in a more supported way") rips out a lot of code to simply the allocation of aligned DMA. However, it also introduces a new issue when use isoc split in transfer. In my test case, I connect the dwc2 controller with an usb hs Hub

Re: [PATCH 10/10] staging: lustre: fix error deref in ll_splice_alias().

> d_splice_alias() can return an ERR_PTR(). > If it does while debugging is enabled, the following > CDEBUG() will dereference that error and crash. > > So add appropriate checking, and provide a separate > debug message for the error case. Yeah!!! It fixed the issues. Thank you. Reviewed-by:

Re: [PATCH 10/10] staging: lustre: fix error deref in ll_splice_alias().

> d_splice_alias() can return an ERR_PTR(). > If it does while debugging is enabled, the following > CDEBUG() will dereference that error and crash. > > So add appropriate checking, and provide a separate > debug message for the error case. Yeah!!! It fixed the issues. Thank you. Reviewed-by:

Re: [PATCH 02/10] staging: lustre: make struct lu_site_bkt_data private

> This data structure only needs to be public so that > various modules can access a wait queue to wait for object > destruction. > If we provide a function to get the wait queue, rather than the > whole bucket, the structure can be made private. > > Signed-off-by: NeilBrown >

[PATCH v5 15/28] fpga: dfl: fme: add header sub feature support

From: Kang Luwei The Header Register set is always present for FPGA Management Engine (FME), this patch implements init and uinit function for header sub feature and introduces several read-only sysfs interfaces for the capability and status. Sysfs interfaces: *

[PATCH v5 15/28] fpga: dfl: fme: add header sub feature support

From: Kang Luwei The Header Register set is always present for FPGA Management Engine (FME), this patch implements init and uinit function for header sub feature and introduces several read-only sysfs interfaces for the capability and status. Sysfs interfaces: *

Re: [PATCH 02/10] staging: lustre: make struct lu_site_bkt_data private

> This data structure only needs to be public so that > various modules can access a wait queue to wait for object > destruction. > If we provide a function to get the wait queue, rather than the > whole bucket, the structure can be made private. > > Signed-off-by: NeilBrown > --- >

[PATCH v5 19/28] fpga: dfl: fme-mgr: add compat_id support

This patch adds compat_id support to fme manager driver, it reads the ID from the hardware register. And it could be used for compatibility check before partial reconfiguration. Signed-off-by: Wu Hao --- drivers/fpga/dfl-fme-mgr.c | 15 +++ 1 file changed, 15

[PATCH v5 19/28] fpga: dfl: fme-mgr: add compat_id support

This patch adds compat_id support to fme manager driver, it reads the ID from the hardware register. And it could be used for compatibility check before partial reconfiguration. Signed-off-by: Wu Hao --- drivers/fpga/dfl-fme-mgr.c | 15 +++ 1 file changed, 15 insertions(+) diff

[PATCH v5 21/28] fpga: dfl: add fpga region platform driver for FME

This patch adds fpga region platform driver for FPGA Management Engine. It register an fpga region with given fpga manager / bridge device. Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao

[PATCH v5 21/28] fpga: dfl: add fpga region platform driver for FME

This patch adds fpga region platform driver for FPGA Management Engine. It register an fpga region with given fpga manager / bridge device. Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Wu Hao Acked-by: Alan

[PATCH v5 17/28] fpga: dfl: fme: add partial reconfiguration sub feature support

From: Kang Luwei Partial Reconfiguration (PR) is the most important function for FME. It allows reconfiguration for given Port/Accelerated Function Unit (AFU). It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges, and invokes fpga-region's interface

[PATCH v5 24/28] fpga: dfl: afu: add port ops support

This patch registers the port ops into the global list in the DFL framework, and it allows other modules to use the port ops. And This patch includes the implementation of the get_id and enable_set ops too. Signed-off-by: Wu Hao --- drivers/fpga/dfl-afu-main.c | 122

[PATCH v5 17/28] fpga: dfl: fme: add partial reconfiguration sub feature support

From: Kang Luwei Partial Reconfiguration (PR) is the most important function for FME. It allows reconfiguration for given Port/Accelerated Function Unit (AFU). It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges, and invokes fpga-region's interface (fpga_region_program_fpga)

[PATCH v5 24/28] fpga: dfl: afu: add port ops support

This patch registers the port ops into the global list in the DFL framework, and it allows other modules to use the port ops. And This patch includes the implementation of the get_id and enable_set ops too. Signed-off-by: Wu Hao --- drivers/fpga/dfl-afu-main.c | 122

[PATCH v5 25/28] fpga: dfl: afu: add header sub feature support

The port header register set is always present for port, it is mainly for capability, control and status of the ports that AFU connected to. This patch implements header sub feature support. Below user interfaces are created by this patch. Sysfs interface: * /sys/class/fpga_region///id

[PATCH v5 25/28] fpga: dfl: afu: add header sub feature support

The port header register set is always present for port, it is mainly for capability, control and status of the ports that AFU connected to. This patch implements header sub feature support. Below user interfaces are created by this patch. Sysfs interface: * /sys/class/fpga_region///id

[PATCH v5 20/28] fpga: dfl: add fpga bridge platform driver for FME

This patch adds fpga bridge platform driver for FPGA Management Engine. It implements the enable_set callback for fpga bridge. Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao

[PATCH v5 27/28] fpga: dfl: afu: add afu sub feature support

From: Xiao Guangrong User Accelerated Function Unit sub feature exposes the MMIO region of the AFU. After valid PR bitstream is programmed and the port is enabled, then this MMIO region could be accessed. This patch adds support to enumerate the AFU MMIO region

[PATCH v5 23/28] fpga: dfl: add FPGA Accelerated Function Unit driver basic framework

On DFL FPGA devices, the Accelerated Function Unit (AFU), can be reprogrammed for different functions. It connects to the FPGA infrastructure (static FPGA region) via a Port. Port CSRs are implemented separately from the AFU CSRs to provide control and status of the Port. Once valid PR bitstream

[PATCH v5 20/28] fpga: dfl: add fpga bridge platform driver for FME

This patch adds fpga bridge platform driver for FPGA Management Engine. It implements the enable_set callback for fpga bridge. Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Wu Hao Acked-by: Alan Tull

[PATCH v5 27/28] fpga: dfl: afu: add afu sub feature support

From: Xiao Guangrong User Accelerated Function Unit sub feature exposes the MMIO region of the AFU. After valid PR bitstream is programmed and the port is enabled, then this MMIO region could be accessed. This patch adds support to enumerate the AFU MMIO region and expose it to userspace via

[PATCH v5 23/28] fpga: dfl: add FPGA Accelerated Function Unit driver basic framework

On DFL FPGA devices, the Accelerated Function Unit (AFU), can be reprogrammed for different functions. It connects to the FPGA infrastructure (static FPGA region) via a Port. Port CSRs are implemented separately from the AFU CSRs to provide control and status of the Port. Once valid PR bitstream

[PATCH v5 26/28] fpga: dfl: afu: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support

DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common ones which need to be supported by all feature devices drivers including FME and AFU. This patch implements above 2 ioctls in FPGA Accelerated Function Unit (AFU) driver. Signed-off-by: Tim Whisonant

[PATCH v5 26/28] fpga: dfl: afu: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support

DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common ones which need to be supported by all feature devices drivers including FME and AFU. This patch implements above 2 ioctls in FPGA Accelerated Function Unit (AFU) driver. Signed-off-by: Tim Whisonant Signed-off-by: Enno

[PATCH v5 28/28] fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support

DMA memory regions are required for Accelerated Function Unit (AFU) usage. These two ioctls allow user space applications to map user memory regions for dma, and unmap them after use. Iova is returned from driver to user space application via DFL_FPGA_PORT_DMA_MAP ioctl. Application needs to unmap

Re: [PATCH 0/6] use memcpy_mcsafe() for copy_to_iter()

On Tue, May 1, 2018 at 7:53 PM, Linus Torvalds wrote: > On Tue, May 1, 2018 at 7:26 PM Dan Williams > wrote: > >> Right, but the only way to make MCE non-fatal is to teach the machine >> check handler about recoverable conditions. This

[PATCH v5 28/28] fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support

DMA memory regions are required for Accelerated Function Unit (AFU) usage. These two ioctls allow user space applications to map user memory regions for dma, and unmap them after use. Iova is returned from driver to user space application via DFL_FPGA_PORT_DMA_MAP ioctl. Application needs to unmap

Re: [PATCH 0/6] use memcpy_mcsafe() for copy_to_iter()

On Tue, May 1, 2018 at 7:53 PM, Linus Torvalds wrote: > On Tue, May 1, 2018 at 7:26 PM Dan Williams > wrote: > >> Right, but the only way to make MCE non-fatal is to teach the machine >> check handler about recoverable conditions. This patch teaches the >> machine check handler how to recover

[PATCH v5 13/28] fpga: dfl-pci: add enumeration for feature devices

The Device Feature List (DFL) is implemented in MMIO, and features are linked via the DFLs. This patch enables pcie driver to prepare enumeration information (e.g locations of all device feature lists in MMIO) and use common APIs provided by the Device Feature List framework to enumerate each

[PATCH v5 12/28] fpga: add FPGA DFL PCIe device driver

From: Zhang Yi This patch implements the basic framework of the driver for FPGA PCIe device which implements the Device Feature List (DFL) in its MMIO space. This driver is verified on Intel(R) PCIe based FPGA DFL devices, including both integrated (e.g Intel Server

[PATCH v5 16/28] fpga: dfl: fme: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support

DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common ones which need to be supported by all feature devices drivers including FME and AFU. Userspace application can use these ioctl interfaces to get the API info and check if specific extension is supported or not in current

[PATCH v5 13/28] fpga: dfl-pci: add enumeration for feature devices

The Device Feature List (DFL) is implemented in MMIO, and features are linked via the DFLs. This patch enables pcie driver to prepare enumeration information (e.g locations of all device feature lists in MMIO) and use common APIs provided by the Device Feature List framework to enumerate each

[PATCH v5 12/28] fpga: add FPGA DFL PCIe device driver

From: Zhang Yi This patch implements the basic framework of the driver for FPGA PCIe device which implements the Device Feature List (DFL) in its MMIO space. This driver is verified on Intel(R) PCIe based FPGA DFL devices, including both integrated (e.g Intel Server Platform with In-package

[PATCH v5 16/28] fpga: dfl: fme: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support

DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common ones which need to be supported by all feature devices drivers including FME and AFU. Userspace application can use these ioctl interfaces to get the API info and check if specific extension is supported or not in current

[PATCH v5 18/28] fpga: dfl: add fpga manager platform driver for FME

This patch adds fpga manager driver for FPGA Management Engine (FME). It implements fpga_manager_ops for FPGA Partial Reconfiguration function. Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao

[PATCH v5 22/28] fpga: dfl: fme-region: add support for compat_id

This patch adds compat_id support, it reuses fme manager's compat id, as the per region compat id is actually from the fme manager's register. Signed-off-by: Wu Hao --- v5: reuse fme manager's compat_id as per region compat_id --- drivers/fpga/dfl-fme-region.c | 1 + 1 file

[PATCH v5 18/28] fpga: dfl: add fpga manager platform driver for FME

This patch adds fpga manager driver for FPGA Management Engine (FME). It implements fpga_manager_ops for FPGA Partial Reconfiguration function. Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Kang Luwei

[PATCH v5 22/28] fpga: dfl: fme-region: add support for compat_id

This patch adds compat_id support, it reuses fme manager's compat id, as the per region compat id is actually from the fme manager's register. Signed-off-by: Wu Hao --- v5: reuse fme manager's compat_id as per region compat_id --- drivers/fpga/dfl-fme-region.c | 1 + 1 file changed, 1

[PATCH v5 00/28] FPGA Device Feature List (DFL) Device Drivers

Hi All, Here is v5 patch-series adding drivers for FPGA DFL devices. This patch series provides a common framework to support FPGA Device Feature List (DFL), and also feature dev drivers under this DFL framework to provide interfaces for userspace applications to configure, enumerate, open, and

[PATCH v5 00/28] FPGA Device Feature List (DFL) Device Drivers

Hi All, Here is v5 patch-series adding drivers for FPGA DFL devices. This patch series provides a common framework to support FPGA Device Feature List (DFL), and also feature dev drivers under this DFL framework to provide interfaces for userspace applications to configure, enumerate, open, and

[PATCH v5 09/28] fpga: dfl: add feature device infrastructure

From: Xiao Guangrong This patch abstracts the common operations of the sub features, and defines the feature_ops data structure, including init, uinit and ioctl function pointers. And this patch adds some common helper functions for FME and AFU drivers, e.g

[PATCH v5 05/28] fpga: region: add compat_id support

This patch introduces a compat_id pointer member and sysfs interface for each fpga region, similar as compat_id for fpga manager, it allows applications to read the per region compat_id for compatibility checking before other actions on this fpga-region (e.g PR). Signed-off-by: Wu Hao

[PATCH v5 09/28] fpga: dfl: add feature device infrastructure

From: Xiao Guangrong This patch abstracts the common operations of the sub features, and defines the feature_ops data structure, including init, uinit and ioctl function pointers. And this patch adds some common helper functions for FME and AFU drivers, e.g dfl_feature_dev_use_begin/end which

[PATCH v5 05/28] fpga: region: add compat_id support

This patch introduces a compat_id pointer member and sysfs interface for each fpga region, similar as compat_id for fpga manager, it allows applications to read the per region compat_id for compatibility checking before other actions on this fpga-region (e.g PR). Signed-off-by: Wu Hao --- v5:

[PATCH v5 01/28] docs: fpga: add a document for FPGA Device Feature List (DFL) Framework Overview

Add a document for FPGA Device Feature List (DFL) Framework Overview. Signed-off-by: Enno Luebbers Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao --- v2: added FME fpga-mgr/bridge/region platform driver to driver

[PATCH v5 01/28] docs: fpga: add a document for FPGA Device Feature List (DFL) Framework Overview

Add a document for FPGA Device Feature List (DFL) Framework Overview. Signed-off-by: Enno Luebbers Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao --- v2: added FME fpga-mgr/bridge/region platform driver to driver organization. updated open discussion per current implementation.

Re: [PATCH 0/6] use memcpy_mcsafe() for copy_to_iter()

On Tue, May 1, 2018 at 7:26 PM Dan Williams wrote: > Right, but the only way to make MCE non-fatal is to teach the machine > check handler about recoverable conditions. This patch teaches the > machine check handler how to recover copy_to_iter() errors. Why not just

Re: [PATCH 0/6] use memcpy_mcsafe() for copy_to_iter()

On Tue, May 1, 2018 at 7:26 PM Dan Williams wrote: > Right, but the only way to make MCE non-fatal is to teach the machine > check handler about recoverable conditions. This patch teaches the > machine check handler how to recover copy_to_iter() errors. Why not just unmap the page and remap a

Re: [PATCH 3/3] vsprintf: Add use-early-random-bytes cmd line option

On Tue, May 1, 2018 at 6:45 PM Steven Rostedt wrote: > Except for where hardware vendors control what random bytes you > actually get ;-) In which case you should just use "nordrand" and be done with it. .. and you might also want to reconsider your other life choices,

Re: [RFC v3 4/5] virtio_ring: add event idx support in packed ring

On 2018年04月25日 13:15, Tiwei Bie wrote: This commit introduces the event idx support in packed ring. This feature is temporarily disabled, because the implementation in this patch may not work as expected, and some further discussions on the implementation are needed, e.g. do we have to check

Re: [RFC v3 4/5] virtio_ring: add event idx support in packed ring

On 2018年04月25日 13:15, Tiwei Bie wrote: This commit introduces the event idx support in packed ring. This feature is temporarily disabled, because the implementation in this patch may not work as expected, and some further discussions on the implementation are needed, e.g. do we have to check

Re: [PATCH 3/3] vsprintf: Add use-early-random-bytes cmd line option

On Tue, May 1, 2018 at 6:45 PM Steven Rostedt wrote: > Except for where hardware vendors control what random bytes you > actually get ;-) In which case you should just use "nordrand" and be done with it. .. and you might also want to reconsider your other life choices, because honestly, there

答复: Tracking: radeon 0000:00:10.0: ring 0 stalled for more than 10240msec

Hi , If you are sure that the HW worked fine before. I think you should: 1. Be sure that HW works fine now. 2. recall the driver to the point at where it works well, and then replace them one by one to confirm component which causes the issue. 3. try to update the last VBIOS to adapt new

答复: Tracking: radeon 0000:00:10.0: ring 0 stalled for more than 10240msec

Hi , If you are sure that the HW worked fine before. I think you should: 1. Be sure that HW works fine now. 2. recall the driver to the point at where it works well, and then replace them one by one to confirm component which causes the issue. 3. try to update the last VBIOS to adapt new

Re: [PATCH] h8300: switch to NO_BOOTMEM

On Fri, Mar 16, 2018 at 4:33 PM, Rob Herring wrote: > Commit 0fa1c579349f ("of/fdt: use memblock_virt_alloc for early alloc") > inadvertently switched the DT unflattening allocations from memblock to > bootmem which doesn't work because the unflattening happens before > bootmem

Re: [PATCH] h8300: switch to NO_BOOTMEM

On Fri, Mar 16, 2018 at 4:33 PM, Rob Herring wrote: > Commit 0fa1c579349f ("of/fdt: use memblock_virt_alloc for early alloc") > inadvertently switched the DT unflattening allocations from memblock to > bootmem which doesn't work because the unflattening happens before > bootmem is initialized.

Re: Re: [PATCH v2 15/17] power: reset: mt6323: add a driver for MT6323 power controller

On Tue, 2018-05-01 at 14:56 +0200, Sebastian Reichel wrote: > Hi, > > On Wed, Apr 25, 2018 at 05:32:41PM +0800, sean.w...@mediatek.com wrote: > > From: Sean Wang > > > > The power device is responsible for externally down or up the power > > of the remote MediaTek SoC

Re: Re: [PATCH v2 15/17] power: reset: mt6323: add a driver for MT6323 power controller

On Tue, 2018-05-01 at 14:56 +0200, Sebastian Reichel wrote: > Hi, > > On Wed, Apr 25, 2018 at 05:32:41PM +0800, sean.w...@mediatek.com wrote: > > From: Sean Wang > > > > The power device is responsible for externally down or up the power > > of the remote MediaTek SoC through the tiny circuit

Re: [PATCH v3] PM / wakeup: use seq_open() to show wakeup stats

Hi, Pavel Thanks for your review. 2018-04-29 22:30 GMT+08:00 Pavel Machek : > On Wed 2018-04-25 18:59:31, Ganesh Mahendran wrote: >> single_open() interface requires that the whole output must >> fit into a single buffer. This will lead to timeout when >> system memory is not in a

Re: [PATCH v3] PM / wakeup: use seq_open() to show wakeup stats

Hi, Pavel Thanks for your review. 2018-04-29 22:30 GMT+08:00 Pavel Machek : > On Wed 2018-04-25 18:59:31, Ganesh Mahendran wrote: >> single_open() interface requires that the whole output must >> fit into a single buffer. This will lead to timeout when >> system memory is not in a good

Re: [PATCH 0/6] use memcpy_mcsafe() for copy_to_iter()

On Tue, May 1, 2018 at 5:09 PM, Linus Torvalds wrote: > On Tue, May 1, 2018 at 4:03 PM Dan Williams > wrote: > >> I'm confused. Are you talking about getting rid of the block-layer >> bypass or changing how MCS errors are handled? > > The

Re: [PATCH 0/6] use memcpy_mcsafe() for copy_to_iter()

On Tue, May 1, 2018 at 5:09 PM, Linus Torvalds wrote: > On Tue, May 1, 2018 at 4:03 PM Dan Williams > wrote: > >> I'm confused. Are you talking about getting rid of the block-layer >> bypass or changing how MCS errors are handled? > > The latter. > >> If it's the latter, MCS error handling, I

Re: [PATCHv4 1/2] iommu/vt-d: Ratelimit each dmar fault printing

Hi Joerg, is there anything I may do about those two patches? In 2/2 I've limited loop cnt as discussed in v3. This one solves softlockup for us, might be useful. On Sat, 2018-03-31 at 01:33 +0100, Dmitry Safonov wrote: > There is a ratelimit for printing, but it's incremented each time the >

Re: [PATCHv4 1/2] iommu/vt-d: Ratelimit each dmar fault printing

Hi Joerg, is there anything I may do about those two patches? In 2/2 I've limited loop cnt as discussed in v3. This one solves softlockup for us, might be useful. On Sat, 2018-03-31 at 01:33 +0100, Dmitry Safonov wrote: > There is a ratelimit for printing, but it's incremented each time the >

Re: [PATCH v3] module: Fix display of wrong module .text address

On Wed, Apr 18, 2018 at 12:14 AM, Thomas Richter wrote: > Reading file /proc/modules shows the correct address: > [root@s35lp76 ~]# cat /proc/modules | egrep '^qeth_l2' > qeth_l2 94208 1 - Live 0x03ff80401000 > > and reading file /sys/module/qeth_l2/sections/.text >

Re: [PATCH v3] module: Fix display of wrong module .text address

On Wed, Apr 18, 2018 at 12:14 AM, Thomas Richter wrote: > Reading file /proc/modules shows the correct address: > [root@s35lp76 ~]# cat /proc/modules | egrep '^qeth_l2' > qeth_l2 94208 1 - Live 0x03ff80401000 > > and reading file /sys/module/qeth_l2/sections/.text > [root@s35lp76 ~]# cat

Re: [PATCH v6 0/8] ipc: Clamp *mni to the real IPCMNI limit & increase that limit

> The sysctl parameters msgmni, shmmni and semmni have an inherent limit > of IPC_MNI (32k). However, users may not be aware of that because they > can write a value much higher than that without getting any error or > notification. Reading the parameters back will show the newly written >

Re: [PATCH v6 0/8] ipc: Clamp *mni to the real IPCMNI limit & increase that limit

> The sysctl parameters msgmni, shmmni and semmni have an inherent limit > of IPC_MNI (32k). However, users may not be aware of that because they > can write a value much higher than that without getting any error or > notification. Reading the parameters back will show the newly written >

WARNING in __snd_pcm_lib_xfer

Hello, syzbot found the following crash on: HEAD commit:fff75eb2a08c Merge tag 'errseq-v4.17' of git://git.kernel.o... git tree: upstream console output: https://syzkaller.appspot.com/x/log.txt?id=6530078334779392 kernel config:

WARNING in __snd_pcm_lib_xfer

Hello, syzbot found the following crash on: HEAD commit:fff75eb2a08c Merge tag 'errseq-v4.17' of git://git.kernel.o... git tree: upstream console output: https://syzkaller.appspot.com/x/log.txt?id=6530078334779392 kernel config:

linux-next: manual merge of the bpf-next tree with the bpf tree

Hi all, Today's linux-next merge of the bpf-next tree got a conflict in: tools/testing/selftests/bpf/test_progs.c between commit: a4e21ff8d9a3 ("bpf: minor fix to selftest test_stacktrace_build_id()") from the bpf tree and commit: 79b453501310 ("tools/bpf: add a test for bpf_get_stack

linux-next: manual merge of the bpf-next tree with the bpf tree

Hi all, Today's linux-next merge of the bpf-next tree got a conflict in: tools/testing/selftests/bpf/test_progs.c between commit: a4e21ff8d9a3 ("bpf: minor fix to selftest test_stacktrace_build_id()") from the bpf tree and commit: 79b453501310 ("tools/bpf: add a test for bpf_get_stack

[GIT PULL] Hexagon fixes

Linus, Please pull the following changes for Hexagon; they contain some small fixes for module compilation. Thanks, Richard Kuo The following changes since commit 6da6c0db5316275015e8cc2959f12a17584aeb64: Linux v4.17-rc3 (2018-04-29 14:17:42 -0700) are available in the git repository at:

[GIT PULL] Hexagon fixes

Linus, Please pull the following changes for Hexagon; they contain some small fixes for module compilation. Thanks, Richard Kuo The following changes since commit 6da6c0db5316275015e8cc2959f12a17584aeb64: Linux v4.17-rc3 (2018-04-29 14:17:42 -0700) are available in the git repository at:

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