Both the kernel and the vDSO need to have unique build ids.
Insert the build salt section to make the build ids unique.
Signed-off-by: Laura Abbott
---
arch/x86/entry/vdso/vdso-layout.lds.S | 3 ++-
arch/x86/kernel/vmlinux.lds.S | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
Hi,
This is v4 of the series to allow unique build ids in the kernel. As a
reminder of the context:
""
In Fedora, the debug information is packaged separately (foo-debuginfo) and
can be installed separately. There's been a long standing issue where only one
version of a debuginfo info package
The build id generated from --build-id can be generated in several different
ways, with the default being the sha1 on the output of the linked file. For
distributions, it can be useful to make sure this ID is unique, even if the
actual file contents don't change. The easiest way to do this is to
The build id generated from --build-id can be generated in several different
ways, with the default being the sha1 on the output of the linked file. For
distributions, it can be useful to make sure this ID is unique, even if the
actual file contents don't change. The easiest way to do this is to
In preparation for some upcoming work, allow module-common.lds
to be run through the preprocessor.
Signed-off-by: Laura Abbott
---
scripts/.gitignore | 1 +
scripts/Makefile | 2 +-
scripts/{module-common.lds =>
In preparation for some upcoming work, allow module-common.lds
to be run through the preprocessor.
Signed-off-by: Laura Abbott
---
scripts/.gitignore | 1 +
scripts/Makefile | 2 +-
scripts/{module-common.lds =>
On 2018-06-08 16:10, Vivek Gautam wrote:
Hi Can,
On 5/29/2018 10:07 AM, Can Guo wrote:
Add UFS PHY support to make SDM845 UFS work with common PHY framework.
Signed-off-by: Can Guo
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 200
+---
On 2018-06-08 16:10, Vivek Gautam wrote:
Hi Can,
On 5/29/2018 10:07 AM, Can Guo wrote:
Add UFS PHY support to make SDM845 UFS work with common PHY framework.
Signed-off-by: Can Guo
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 200
+---
On 2018-06-08 14:45, Manu Gautam wrote:
Hi,
On 5/29/2018 10:07 AM, Can Guo wrote:
All PHYs should be powered on before register configuration starts.
And
only PCIe PHYs need an extra power control before deasserts reset
state.
Signed-off-by: Can Guo
---
drivers/phy/qualcomm/phy-qcom-qmp.c
On 2018-06-08 14:45, Manu Gautam wrote:
Hi,
On 5/29/2018 10:07 AM, Can Guo wrote:
All PHYs should be powered on before register configuration starts.
And
only PCIe PHYs need an extra power control before deasserts reset
state.
Signed-off-by: Can Guo
---
drivers/phy/qualcomm/phy-qcom-qmp.c
Maybe I can do it, I have a kernel with speakup, using 4.9.43. Will
the patch fit there?
On Mon, 11 Jun 2018 18:57:03 -0400,
Samuel Thibault wrote:
>
> [1 ]
> Hello,
>
> Samuel Thibault, le mer. 06 juin 2018 15:26:28 +0200, a ecrit:
> > I'd also rather see it tested in the real wild before
On 6/11/2018 3:36 PM, Florian Fainelli wrote:
On 05/29/2018 02:58 PM, Ray Jui wrote:
Change the PCIe INTx mapping to model the 4 INTx interrupts in the
IRQ domain of the iProc PCIe controller itself
Signed-off-by: Ray Jui
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 18 ++
1
Maybe I can do it, I have a kernel with speakup, using 4.9.43. Will
the patch fit there?
On Mon, 11 Jun 2018 18:57:03 -0400,
Samuel Thibault wrote:
>
> [1 ]
> Hello,
>
> Samuel Thibault, le mer. 06 juin 2018 15:26:28 +0200, a ecrit:
> > I'd also rather see it tested in the real wild before
On 6/11/2018 3:36 PM, Florian Fainelli wrote:
On 05/29/2018 02:58 PM, Ray Jui wrote:
Change the PCIe INTx mapping to model the 4 INTx interrupts in the
IRQ domain of the iProc PCIe controller itself
Signed-off-by: Ray Jui
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 18 ++
1
On Mon 11 Jun 15:08 PDT 2018, Ramon Fried wrote:
> * Fixed checkpatch.sh warnings in smem.c & smem.h:
> - WARNING: Prefer 'unsigned int' to bare use of 'unsigned'.
> - WARNING: Block comments should align the * on each line.
> - WARNING: line over 80 characters.
> - ERROR: do not use assignment
On Mon 11 Jun 15:08 PDT 2018, Ramon Fried wrote:
> * Fixed checkpatch.sh warnings in smem.c & smem.h:
> - WARNING: Prefer 'unsigned int' to bare use of 'unsigned'.
> - WARNING: Block comments should align the * on each line.
> - WARNING: line over 80 characters.
> - ERROR: do not use assignment
Activate PAXC bridge quirk for more PAXC based PCIe root complex with
the following PCIe device ID:
0xd750, 0xd802, 0xd804
Signed-off-by: Ray Jui
---
drivers/pci/quirks.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 2990ad1..47dfea0
Activate PAXC bridge quirk for more PAXC based PCIe root complex with
the following PCIe device ID:
0xd750, 0xd802, 0xd804
Signed-off-by: Ray Jui
---
drivers/pci/quirks.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 2990ad1..47dfea0
The internal MSI parsing logic in certain revisions of PAXC root
complexes does not work properly and can casue corruptions on the
writes. They need to be disabled
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
drivers/pci/host/pcie-iproc.c | 34 --
1
This patch series improves the Broadcom PAXC support by 1) adding more
quirks for specific versions of PAXC controllers; 2) adding logic to
reject internally unconfigured physical functions from the embedded
network processor acting as endpoint; 3) reducing verbose print level
in the
Reduce inbound/outbound mapping print level from dev_info to
dev_dbg. This reduces the console logs during Linux boot process
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
drivers/pci/host/pcie-iproc.c | 34 +-
1 file changed, 17 insertions(+), 17
On certain versions of Broadcom PAXC based root complexes, certain
regions of the configuration space are corrupted. As a result, it
prevents the Linux PCIe stack from traversing the linked list of the
capability registers completely and therefore the root complex is
not advertised as "PCIe
PAXC is an emulated PCIe root complex internally in various Broadcom
based SoCs. PAXC internally connects to the embedded network processor
within these SoCs, with the embedeed network processor exposed as an
endpoint device
The number of physical functions from the embedded network processor
Reduce inbound/outbound mapping print level from dev_info to
dev_dbg. This reduces the console logs during Linux boot process
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
drivers/pci/host/pcie-iproc.c | 34 +-
1 file changed, 17 insertions(+), 17
On certain versions of Broadcom PAXC based root complexes, certain
regions of the configuration space are corrupted. As a result, it
prevents the Linux PCIe stack from traversing the linked list of the
capability registers completely and therefore the root complex is
not advertised as "PCIe
PAXC is an emulated PCIe root complex internally in various Broadcom
based SoCs. PAXC internally connects to the embedded network processor
within these SoCs, with the embedeed network processor exposed as an
endpoint device
The number of physical functions from the embedded network processor
The internal MSI parsing logic in certain revisions of PAXC root
complexes does not work properly and can casue corruptions on the
writes. They need to be disabled
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
drivers/pci/host/pcie-iproc.c | 34 --
1
This patch series improves the Broadcom PAXC support by 1) adding more
quirks for specific versions of PAXC controllers; 2) adding logic to
reject internally unconfigured physical functions from the embedded
network processor acting as endpoint; 3) reducing verbose print level
in the
The TCG SAPI specification [1] defines a set of functions, which allows
applications to use the TPM device in either blocking or non-blocking fashion.
Each command defined by the specification has a corresponding
Tss2_Sys__Prepare() and Tss2_Sys__Complete() call, which
together with
The TCG SAPI specification [1] defines a set of functions, which allows
applications to use the TPM device in either blocking or non-blocking fashion.
Each command defined by the specification has a corresponding
Tss2_Sys__Prepare() and Tss2_Sys__Complete() call, which
together with
Add a ptr to struct tpm_space to the file_priv to have an easy
access to it in the async job without the need to allocate memory.
This also allows to consolidate of the write operations for
the two interfaces.
Signed-off-by: Tadeusz Struk
---
drivers/char/tpm/tpm-dev-common.c |8 +---
Hi Samuel,
After merging the nfc-next tree, today's linux-next build (x86_64
allmodconfig) produced this warning:
drivers/nfc/fdp/fdp.c: In function 'fdp_nci_open':
drivers/nfc/fdp/fdp.c:250:17: warning: unused variable 'dev' [-Wunused-variable]
struct device *dev = >phy->i2c_dev->dev;
Currently the TPM driver only supports blocking calls, which doesn't allow
asynchronous IO operations to the TPM hardware.
This patch changes it and adds support for nonblocking write and a new poll
function to enable applications, which want to take advantage of this.
Signed-off-by: Tadeusz
Add a ptr to struct tpm_space to the file_priv to have an easy
access to it in the async job without the need to allocate memory.
This also allows to consolidate of the write operations for
the two interfaces.
Signed-off-by: Tadeusz Struk
---
drivers/char/tpm/tpm-dev-common.c |8 +---
Hi Samuel,
After merging the nfc-next tree, today's linux-next build (x86_64
allmodconfig) produced this warning:
drivers/nfc/fdp/fdp.c: In function 'fdp_nci_open':
drivers/nfc/fdp/fdp.c:250:17: warning: unused variable 'dev' [-Wunused-variable]
struct device *dev = >phy->i2c_dev->dev;
Currently the TPM driver only supports blocking calls, which doesn't allow
asynchronous IO operations to the TPM hardware.
This patch changes it and adds support for nonblocking write and a new poll
function to enable applications, which want to take advantage of this.
Signed-off-by: Tadeusz
Hi Bjorn,
On 5/30/2018 10:43 AM, Ray Jui wrote:
Hi Bjorn,
On 5/30/2018 10:27 AM, Bjorn Helgaas wrote:
On Thu, May 17, 2018 at 10:21:31AM -0700, Ray Jui wrote:
On certain versions of Broadcom PAXC based root complexes, certain
regions of the configuration space are corrupted. As a result, it
Hi Bjorn,
On 5/30/2018 10:43 AM, Ray Jui wrote:
Hi Bjorn,
On 5/30/2018 10:27 AM, Bjorn Helgaas wrote:
On Thu, May 17, 2018 at 10:21:31AM -0700, Ray Jui wrote:
On certain versions of Broadcom PAXC based root complexes, certain
regions of the configuration space are corrupted. As a result, it
On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC
On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC
This is a branch with a few merge requests that either came in late, or
took a while longer for us to review and merge than usual and thus cut
it a bit close to the merge window. We stage them in a separate branch
and if things look good, we still send them up -- and that's the case
here.
This is
This is a branch with a few merge requests that either came in late, or
took a while longer for us to review and merge than usual and thus cut
it a bit close to the merge window. We stage them in a separate branch
and if things look good, we still send them up -- and that's the case
here.
This is
This branch contains platform-related driver updates for ARM and ARM64.
Highlights:
- ARM SCMI (System Control & Management Interface) driver cleanups
- Hisilicon support for LPC bus w/ ACPI
- Reset driver updates for several platforms: Uniphier,
- Rockchip power domain bindings and hardware
This branch contains platform-related driver updates for ARM and ARM64.
Highlights:
- ARM SCMI (System Control & Management Interface) driver cleanups
- Hisilicon support for LPC bus w/ ACPI
- Reset driver updates for several platforms: Uniphier,
- Rockchip power domain bindings and hardware
Hi Linus,
Here are the pull requests for arm-soc for this merge window, broken up
into 4 different pull requests. In addition to this, I will follow up
with a small branch that normalizes some of the defconfigs at the end
of the merge window, since they have become quite shuffled with time.
As always, a large number of DT updates. Too many to enumerate them all,
but at a glance:
New SoCs introduced in this release:
- Amlogic:
+ Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some set
top boxes and other products.
- Mediatek:
+ MT7623A, which is a flavor of the MT7623
Hi Linus,
Here are the pull requests for arm-soc for this merge window, broken up
into 4 different pull requests. In addition to this, I will follow up
with a small branch that normalizes some of the defconfigs at the end
of the merge window, since they have become quite shuffled with time.
As always, a large number of DT updates. Too many to enumerate them all,
but at a glance:
New SoCs introduced in this release:
- Amlogic:
+ Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some set
top boxes and other products.
- Mediatek:
+ MT7623A, which is a flavor of the MT7623
Here are the main updates for SoC support (besides DT additions) for ARM
32- and 64-bit platforms. The branch also contains defconfig updates to
turn on drivers and options as needed on the various platforms.
The largest parts of the delta are from cleanups moving platform data
and board file
Here are the main updates for SoC support (besides DT additions) for ARM
32- and 64-bit platforms. The branch also contains defconfig updates to
turn on drivers and options as needed on the various platforms.
The largest parts of the delta are from cleanups moving platform data
and board file
There are still quite a few cases where a device might want to get to a
different node of the device-tree, obtain the resources and map them.
Drivers doing that currently open code the whole thing, which is error
proe.
We have of_iomap() and of_io_request_and_map() but they both have
These days of_address_to_resource() puts a reasonable name
in the resource struct, thus make the "name" argument an
optional override.
Signed-off-by: Benjamin Herrenschmidt
---
Just something I noticed ... we should probably update the
callers to stop passing stupid names..
There are still quite a few cases where a device might want to get to a
different node of the device-tree, obtain the resources and map them.
Drivers doing that currently open code the whole thing, which is error
proe.
We have of_iomap() and of_io_request_and_map() but they both have
These days of_address_to_resource() puts a reasonable name
in the resource struct, thus make the "name" argument an
optional override.
Signed-off-by: Benjamin Herrenschmidt
---
Just something I noticed ... we should probably update the
callers to stop passing stupid names..
On Tue, Jun 12, 2018 at 12:57:03AM +0200, Samuel Thibault wrote:
> Anybody up for testing please?
>
> If people want to see speakup get mainlined instead of staging, please
> help.
If I understand right, this patch changes how synthesizers are loaded
and unloaded through
On Tue, Jun 12, 2018 at 12:57:03AM +0200, Samuel Thibault wrote:
> Anybody up for testing please?
>
> If people want to see speakup get mainlined instead of staging, please
> help.
If I understand right, this patch changes how synthesizers are loaded
and unloaded through
On Tue, 2018-06-12 at 01:38 +0200, Karim Eshapa wrote:
> Use sign_extend32 kernel function instead of code duplication.
> Safe also for 16 bit.
Perhaps remove the bits declaration and assignments
and just use 9 directly.
> diff --git a/drivers/staging/iio/accel/adis16240.c
>
On Tue, 2018-06-12 at 01:38 +0200, Karim Eshapa wrote:
> Use sign_extend32 kernel function instead of code duplication.
> Safe also for 16 bit.
Perhaps remove the bits declaration and assignments
and just use 9 directly.
> diff --git a/drivers/staging/iio/accel/adis16240.c
>
Hi all,
On Fri, 1 Jun 2018 11:56:19 +1000 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the vfs tree got a conflict in:
>
> include/linux/fs.h
>
> between commit:
>
> 29aca8b3f7cd ("fsnotify: introduce prototype struct fsnotify_obj")
>
> from the ext3 tree and commit:
>
>
Hi all,
On Fri, 1 Jun 2018 11:56:19 +1000 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the vfs tree got a conflict in:
>
> include/linux/fs.h
>
> between commit:
>
> 29aca8b3f7cd ("fsnotify: introduce prototype struct fsnotify_obj")
>
> from the ext3 tree and commit:
>
>
Use sign_extend32 kernel function instead of code duplication.
Safe also for 16 bit.
Signed-off-by: Karim Eshapa
---
drivers/staging/iio/accel/adis16240.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/iio/accel/adis16240.c
Use sign_extend32 kernel function instead of code duplication.
Safe also for 16 bit.
Signed-off-by: Karim Eshapa
---
drivers/staging/iio/accel/adis16240.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/iio/accel/adis16240.c
On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC
On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC
On Sat, 09 Jun 2018 08:48:48 +0200 Takashi Iwai wrote:
> On Fri, 08 Jun 2018 23:16:59 +0200,
> Andrew Morton wrote:
> >
> > On Fri, 8 Jun 2018 15:49:49 +0200 Takashi Iwai wrote:
> >
> > > Currently shmmni proc entry accepts all entered integer values, but
> > > the practical limit is IPCMNI
On Sat, 09 Jun 2018 08:48:48 +0200 Takashi Iwai wrote:
> On Fri, 08 Jun 2018 23:16:59 +0200,
> Andrew Morton wrote:
> >
> > On Fri, 8 Jun 2018 15:49:49 +0200 Takashi Iwai wrote:
> >
> > > Currently shmmni proc entry accepts all entered integer values, but
> > > the practical limit is IPCMNI
On Mon, Jun 11, 2018 at 03:36:21PM -0700, Andrew Morton wrote:
> On Mon, 11 Jun 2018 10:54:15 -0700 Roman Gushchin wrote:
>
> > Hi, Andrew!
> >
> > Please, find an updated version of memory.min refinements/fixes
> > in this patchset. It's against linus tree.
> > Please, merge these patches into
On Mon, Jun 11, 2018 at 03:36:21PM -0700, Andrew Morton wrote:
> On Mon, 11 Jun 2018 10:54:15 -0700 Roman Gushchin wrote:
>
> > Hi, Andrew!
> >
> > Please, find an updated version of memory.min refinements/fixes
> > in this patchset. It's against linus tree.
> > Please, merge these patches into
Hi Stefan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on mtd/nand/next]
[also build test WARNING on v4.17 next-20180608]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
Hi Stefan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on mtd/nand/next]
[also build test WARNING on v4.17 next-20180608]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
Hello,
Samuel Thibault, le mer. 06 juin 2018 15:26:28 +0200, a ecrit:
> I'd also rather see it tested in the real wild before committing. Could
> somebody on the speakup mailing list test the patch? (which I have
> re-attached as a file for conveniency).
Anybody up for testing please?
If people
Hello,
Samuel Thibault, le mer. 06 juin 2018 15:26:28 +0200, a ecrit:
> I'd also rather see it tested in the real wild before committing. Could
> somebody on the speakup mailing list test the patch? (which I have
> re-attached as a file for conveniency).
Anybody up for testing please?
If people
The i2c controller should be using IRQ_TYPE_LEVEL_HIGH, fix that.
Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT")
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm5301x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The i2c controller should be using IRQ_TYPE_LEVEL_HIGH, fix that.
Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT")
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm5301x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
In ubifs_jnl_update() we sync parent and child inodes to the flash,
in case of xattrs, the parent inode (AKA host inode) has a non-zero
data_len. Therefore we need to adjust synced_i_size too.
This issue was reported by ubifs self tests unter a xattr related work
load.
UBIFS error (ubi0:0 pid
In ubifs_jnl_update() we sync parent and child inodes to the flash,
in case of xattrs, the parent inode (AKA host inode) has a non-zero
data_len. Therefore we need to adjust synced_i_size too.
This issue was reported by ubifs self tests unter a xattr related work
load.
UBIFS error (ubi0:0 pid
The i2c and PCIe controllers had an incorrect type which should have
been set to IRQ_TYPE_LEVEL_HIGH, fix that.
Fixes: b9099ec754b5 ("ARM: dts: Add Broadcom Hurricane 2 DTS include file")
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm-hr2.dtsi | 24
1 file
The i2c and PCIe controllers had an incorrect type which should have
been set to IRQ_TYPE_LEVEL_HIGH, fix that.
Fixes: b9099ec754b5 ("ARM: dts: Add Broadcom Hurricane 2 DTS include file")
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm-hr2.dtsi | 24
1 file
The i2c controller should use IRQ_TYPE_LEVEL_HIGH instead of
IRQ_TYPE_NONE.
Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The i2c controller should use IRQ_TYPE_LEVEL_HIGH instead of
IRQ_TYPE_NONE.
Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT")
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The interrupts for the PCIe controllers should all be of type
IRQ_TYPE_LEVEL_HIGH instead of IRQ_TYPE_NONE.
Fixes: d71eb9412088 ("ARM: dts: NSP: Add MSI support on PCI")
Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm-nsp.dtsi |
Hi all,
This patch series fixes incorrect interrupt type specifiers for the
NSP and HR2 SoCs.
Florian Fainelli (3):
ARM: dts: NSP: Fix i2c controller interrupt type
ARM: dts: NSP: Fix PCIe controllers interrupt types
ARM: dts: HR2: Fix interrupt types for i2c and PCIe
The interrupts for the PCIe controllers should all be of type
IRQ_TYPE_LEVEL_HIGH instead of IRQ_TYPE_NONE.
Fixes: d71eb9412088 ("ARM: dts: NSP: Add MSI support on PCI")
Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue")
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm-nsp.dtsi |
Hi all,
This patch series fixes incorrect interrupt type specifiers for the
NSP and HR2 SoCs.
Florian Fainelli (3):
ARM: dts: NSP: Fix i2c controller interrupt type
ARM: dts: NSP: Fix PCIe controllers interrupt types
ARM: dts: HR2: Fix interrupt types for i2c and PCIe
On Mon, 11 Jun 2018 17:34:15 +0300 "Kirill A. Shutemov"
wrote:
> On Thu, May 31, 2018 at 01:54:55PM +, Kirill A. Shutemov wrote:
> > A pair of trivial cleanups in preparation for memory encryption.
>
> Andrew, can we get these applied?
>
Mid-merge-window is not a good time to be looking
On Mon, 11 Jun 2018 17:34:15 +0300 "Kirill A. Shutemov"
wrote:
> On Thu, May 31, 2018 at 01:54:55PM +, Kirill A. Shutemov wrote:
> > A pair of trivial cleanups in preparation for memory encryption.
>
> Andrew, can we get these applied?
>
Mid-merge-window is not a good time to be looking
On 05/29/2018 02:58 PM, Ray Jui wrote:
> Change the PCIe INTx mapping to model the 4 INTx interrupts in the
> IRQ domain of the iProc PCIe controller itself
>
> Signed-off-by: Ray Jui
> ---
> arch/arm/boot/dts/bcm-cygnus.dtsi | 18 ++
> 1 file changed, 14 insertions(+), 4
On 05/29/2018 02:58 PM, Ray Jui wrote:
> Change the PCIe INTx mapping to model the 4 INTx interrupts in the
> IRQ domain of the iProc PCIe controller itself
>
> Signed-off-by: Ray Jui
> ---
> arch/arm/boot/dts/bcm-cygnus.dtsi | 18 ++
> 1 file changed, 14 insertions(+), 4
On Mon, 11 Jun 2018 10:54:15 -0700 Roman Gushchin wrote:
> Hi, Andrew!
>
> Please, find an updated version of memory.min refinements/fixes
> in this patchset. It's against linus tree.
> Please, merge these patches into 4.18.
>
> ...
>
> mm: fix null pointer dereference in
On Mon, 11 Jun 2018 10:54:15 -0700 Roman Gushchin wrote:
> Hi, Andrew!
>
> Please, find an updated version of memory.min refinements/fixes
> in this patchset. It's against linus tree.
> Please, merge these patches into 4.18.
>
> ...
>
> mm: fix null pointer dereference in
On Mon, Jun 11 2018, Boris Brezillon wrote:
>
> Also, I'd prefer to have this patch split in 2:
> 1/ one patch removing the check in spi_nor_write()
> 2/ and the second patch removing the while() loop in m25p80_write()
>
> How about the following commit messages for those 2 patches:
>
> 1:
> "
>
On Mon, Jun 11 2018, Boris Brezillon wrote:
>
> Also, I'd prefer to have this patch split in 2:
> 1/ one patch removing the check in spi_nor_write()
> 2/ and the second patch removing the while() loop in m25p80_write()
>
> How about the following commit messages for those 2 patches:
>
> 1:
> "
>
On Mon, Jun 11, 2018 at 10:09 AM, Rafael J. Wysocki wrote:
> On Mon, Jun 11, 2018 at 8:26 AM, Kai-Heng Feng
> wrote:
>> Hi Rafael,
>>
>> There's a regression report [1] that says commit a192aa923b66a ("ACPI /
>> LPSS: Consolidate runtime PM and system sleep handling") is the first bad
>> commit.
On Mon, Jun 11, 2018 at 10:09 AM, Rafael J. Wysocki wrote:
> On Mon, Jun 11, 2018 at 8:26 AM, Kai-Heng Feng
> wrote:
>> Hi Rafael,
>>
>> There's a regression report [1] that says commit a192aa923b66a ("ACPI /
>> LPSS: Consolidate runtime PM and system sleep handling") is the first bad
>> commit.
In riscv_gpr_set, pass regs instead of to user_regset_copyin to fix
gdb segfault.
Signed-off-by: Jim Wilson
---
arch/riscv/kernel/ptrace.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index
In riscv_gpr_set, pass regs instead of to user_regset_copyin to fix
gdb segfault.
Signed-off-by: Jim Wilson
---
arch/riscv/kernel/ptrace.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index
On 11 June 2018 at 10:55, Suzuki K Poulose wrote:
> On 11/06/18 17:52, Mathieu Poirier wrote:
>>
>> On 11 June 2018 at 03:22, Suzuki K Poulose wrote:
>>>
>>> On 08/06/18 22:22, Mathieu Poirier wrote:
On Tue, Jun 05, 2018 at 10:43:19PM +0100, Suzuki K Poulose wrote:
>
>
On 11 June 2018 at 10:55, Suzuki K Poulose wrote:
> On 11/06/18 17:52, Mathieu Poirier wrote:
>>
>> On 11 June 2018 at 03:22, Suzuki K Poulose wrote:
>>>
>>> On 08/06/18 22:22, Mathieu Poirier wrote:
On Tue, Jun 05, 2018 at 10:43:19PM +0100, Suzuki K Poulose wrote:
>
>
Allow the code which provides extensions to support direct assignment
of Intel IGD (GVT-d) to be compiled out of the kernel if desired. The
config option for this was previously automatically enabled on X86,
therefore the default remains Y. This simply provides the option to
disable it even for
Allow the code which provides extensions to support direct assignment
of Intel IGD (GVT-d) to be compiled out of the kernel if desired. The
config option for this was previously automatically enabled on X86,
therefore the default remains Y. This simply provides the option to
disable it even for
201 - 300 of 1498 matches
Mail list logo
