Quoting Jordan Crouse (2018-08-06 08:04:37)
> On Mon, Aug 06, 2018 at 02:37:18PM +0530, Amit Nischal wrote:
> > On 2018-08-03 04:14, Stephen Boyd wrote:
> > >Quoting Amit Nischal (2018-07-30 04:28:56)
> > >>On 2018-07-25 12:28, Stephen Boyd wrote:
> > >>>
> > >>> Ok. Sounds good! Is the rate range
Quoting Jordan Crouse (2018-08-06 08:04:37)
> On Mon, Aug 06, 2018 at 02:37:18PM +0530, Amit Nischal wrote:
> > On 2018-08-03 04:14, Stephen Boyd wrote:
> > >Quoting Amit Nischal (2018-07-30 04:28:56)
> > >>On 2018-07-25 12:28, Stephen Boyd wrote:
> > >>>
> > >>> Ok. Sounds good! Is the rate range
--
kernel: 4.4.147-rc1
git repo: https://git.linaro.org/lkft/arm64-stable-rc.git
git branch: 4.4.147-rc1-hikey-20180807-254
git commit: a7af4a3cb7756f8a159f54cb757f30764f3d5166
git describe: 4.4.147-rc1-hikey-20180807-254
Test details:
https://qa-reports.linaro.or
On 07/24/2018 03:10 PM, Waiman Long wrote:
> It was discovered that a constant stream of readers with occassional
> writers pounding on a rwsem may cause many of the readers to enter the
> slowpath unnecessarily thus increasing latency and lowering performance.
>
> In the current code, a reader
On 07/24/2018 03:10 PM, Waiman Long wrote:
> It was discovered that a constant stream of readers with occassional
> writers pounding on a rwsem may cause many of the readers to enter the
> slowpath unnecessarily thus increasing latency and lowering performance.
>
> In the current code, a reader
--
kernel: 4.4.147-rc1
git repo: https://git.linaro.org/lkft/arm64-stable-rc.git
git branch: 4.4.147-rc1-hikey-20180807-254
git commit: a7af4a3cb7756f8a159f54cb757f30764f3d5166
git describe: 4.4.147-rc1-hikey-20180807-254
Test details:
https://qa-reports.linaro.or
Hi Greg !
This adds two FSI fixes to what you already have in your tree
- Fix a NULL dereference in the scom driver
- Fix a command buffer size issue in the sbefifo driver that
breaks some operations with POWER system debugger (cronus)
Cheers,
Ben.
The following changes since tag
Hi Greg !
This adds two FSI fixes to what you already have in your tree
- Fix a NULL dereference in the scom driver
- Fix a command buffer size issue in the sbefifo driver that
breaks some operations with POWER system debugger (cronus)
Cheers,
Ben.
The following changes since tag
Quoting Songjun Wu (2018-08-02 20:02:21)
> From: Yixin Zhu
>
> This driver provides PLL clock registration as well as various clock
> branches, e.g. MUX clock, gate clock, divider clock and so on.
>
> PLLs that provide clock to DDR, CPU and peripherals are shown below:
>
>
Quoting Songjun Wu (2018-08-02 20:02:21)
> From: Yixin Zhu
>
> This driver provides PLL clock registration as well as various clock
> branches, e.g. MUX clock, gate clock, divider clock and so on.
>
> PLLs that provide clock to DDR, CPU and peripherals are shown below:
>
>
There are some 0 resource size pci devices, and it leads to the
accumulator fails to maintain the correct value.
It results in a strange issue on my machine that xhci_hcd failed to init.
[2.437278] xhci_hcd :05:00.0: init :05:00.0 fail, -16
[2.437300] xhci_hcd: probe of
There are some 0 resource size pci devices, and it leads to the
accumulator fails to maintain the correct value.
It results in a strange issue on my machine that xhci_hcd failed to init.
[2.437278] xhci_hcd :05:00.0: init :05:00.0 fail, -16
[2.437300] xhci_hcd: probe of
Hi Tony,
On 8/7/2018 6:28 PM, Luck, Tony wrote:
> Would it help to call routines to read the "before" values of the counter
> twice. The first time to preload the cache with anything needed to execute
> the perf code path.
>>> In an attempt to improve the accuracy of the above I modified it to
Hi Tony,
On 8/7/2018 6:28 PM, Luck, Tony wrote:
> Would it help to call routines to read the "before" values of the counter
> twice. The first time to preload the cache with anything needed to execute
> the perf code path.
>>> In an attempt to improve the accuracy of the above I modified it to
On Tue, Aug 7, 2018 at 9:52 PM, Vlastimil Babka wrote:
> On 08/06/2018 08:52 AM, Rashmica Gupta wrote:
>> When hot-removing memory release_mem_region_adjustable() splits
>> iomem resources if they are not the exact size of the memory being
>> hot-deleted. Adding this memory back to the kernel
On Tue, Aug 7, 2018 at 9:52 PM, Vlastimil Babka wrote:
> On 08/06/2018 08:52 AM, Rashmica Gupta wrote:
>> When hot-removing memory release_mem_region_adjustable() splits
>> iomem resources if they are not the exact size of the memory being
>> hot-deleted. Adding this memory back to the kernel
On Tue, Aug 7, 2018 at 6:12 PM Stephen Rothwell wrote:
>
> Hi Kirill,
>
> On Tue, 07 Aug 2018 18:37:19 +0300 Kirill Tkhai wrote:
> >
> > After bitmaps of not-empty memcg shrinkers were implemented
> > (see "[PATCH v9 00/17] Improve shrink_slab() scalability..."
> > series, which is already in mm
On Tue, Aug 7, 2018 at 6:12 PM Stephen Rothwell wrote:
>
> Hi Kirill,
>
> On Tue, 07 Aug 2018 18:37:19 +0300 Kirill Tkhai wrote:
> >
> > After bitmaps of not-empty memcg shrinkers were implemented
> > (see "[PATCH v9 00/17] Improve shrink_slab() scalability..."
> > series, which is already in mm
On Tue, Aug 07, 2018 at 08:52:59PM -0600, Shuah Khan wrote:
> On 08/07/2018 12:51 PM, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 3.18.118 release.
> > There are 85 patches in this series, all will be posted as a response
> > to this one. If anyone has any
On Tue, Aug 07, 2018 at 08:52:59PM -0600, Shuah Khan wrote:
> On 08/07/2018 12:51 PM, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 3.18.118 release.
> > There are 85 patches in this series, all will be posted as a response
> > to this one. If anyone has any
On Wed, Aug 08, 2018 at 12:17:30AM +0200, Matthias Schiffer wrote:
> On 08/01/2018 06:52 PM, Greg Kroah-Hartman wrote:
> > 4.14-stable review patch. If anyone has any objections, please let me know.
>
> It seems this patch is still missing from the 4.4.y and 4.9.y branches.
Maybe because no one
On Wed, Aug 08, 2018 at 12:17:30AM +0200, Matthias Schiffer wrote:
> On 08/01/2018 06:52 PM, Greg Kroah-Hartman wrote:
> > 4.14-stable review patch. If anyone has any objections, please let me know.
>
> It seems this patch is still missing from the 4.4.y and 4.9.y branches.
Maybe because no one
On 8 August 2018 at 00:21, Greg Kroah-Hartman
wrote:
> This is the start of the stable review cycle for the 4.9.119 release.
> There are 17 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
>
On 8 August 2018 at 00:21, Greg Kroah-Hartman
wrote:
> This is the start of the stable review cycle for the 4.9.119 release.
> There are 17 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
>
On 8 August 2018 at 00:21, Greg Kroah-Hartman
wrote:
> This is the start of the stable review cycle for the 4.14.62 release.
> There are 21 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
>
On 8 August 2018 at 00:21, Greg Kroah-Hartman
wrote:
> This is the start of the stable review cycle for the 4.14.62 release.
> There are 21 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
>
On 8 August 2018 at 00:21, Greg Kroah-Hartman
wrote:
> This is the start of the stable review cycle for the 4.17.14 release.
> There are 18 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
>
On 8 August 2018 at 00:21, Greg Kroah-Hartman
wrote:
> This is the start of the stable review cycle for the 4.17.14 release.
> There are 18 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
>
On Tue, 7 Aug 2018, Andi Kleen wrote:
> > Which simply does not work. Look at Goldmont Fam 6 Model 5C. The SoCs
> > with that Fam/Model combination are:
> >
> > - Apollo Lake
> > - Broxton (has two platforms: Morganfield and Willowtrail)
>
> Right pick one. The others are the same for
On Tue, 7 Aug 2018, Andi Kleen wrote:
> > Which simply does not work. Look at Goldmont Fam 6 Model 5C. The SoCs
> > with that Fam/Model combination are:
> >
> > - Apollo Lake
> > - Broxton (has two platforms: Morganfield and Willowtrail)
>
> Right pick one. The others are the same for
On Tue, Aug 7, 2018 at 8:53 PM, Joel Fernandes wrote:
> On Tue, Aug 7, 2018 at 8:44 PM, Joel Fernandes wrote:
>> Hi Steve,
>>
>> On Tue, Aug 7, 2018 at 7:28 PM, Steven Rostedt wrote:
> [...]
@@ -171,8 +174,7 @@ extern void syscall_unregfunc(void);
} while
On Tue, Aug 7, 2018 at 8:53 PM, Joel Fernandes wrote:
> On Tue, Aug 7, 2018 at 8:44 PM, Joel Fernandes wrote:
>> Hi Steve,
>>
>> On Tue, Aug 7, 2018 at 7:28 PM, Steven Rostedt wrote:
> [...]
@@ -171,8 +174,7 @@ extern void syscall_unregfunc(void);
} while
Did you receive my email yesterday?
Just want to check if you have needs for photo editing for our studio?
We normally edit 300 images within 12-24 hours.
We take care of different kinds of e-commerce photos, jewelry images, and
portrait model images.
Including cutting out and clipping path
Did you receive my email yesterday?
Just want to check if you have needs for photo editing for our studio?
We normally edit 300 images within 12-24 hours.
We take care of different kinds of e-commerce photos, jewelry images, and
portrait model images.
Including cutting out and clipping path
Hi Ravi,
On 2018-08-07 23:59, Ravi Chandra Sadineni wrote:
> hi Merek,
>
> I tried booting a snow device and could not get it to boot it to the
> console. I assume i don't have right kernel config. Can you share your
> config if possible.
I use standard exynos_defconfig bundled with Linux
Hi Ravi,
On 2018-08-07 23:59, Ravi Chandra Sadineni wrote:
> hi Merek,
>
> I tried booting a snow device and could not get it to boot it to the
> console. I assume i don't have right kernel config. Can you share your
> config if possible.
I use standard exynos_defconfig bundled with Linux
Clock framework will enable those clocks registered
with CLK_IS_CRITICAL flag, so no need to have
clks_init_on array during clock initialization now.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx7d.c | 27 ---
drivers/clk/imx/clk.h | 7 +++
2 files
Clock framework will enable those clocks registered
with CLK_IS_CRITICAL flag, so no need to have
clks_init_on array during clock initialization now.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx7d.c | 27 ---
drivers/clk/imx/clk.h | 7 +++
2 files
On i.MX7D, IMX7D_NAND_USDHC_BUS_ROOT_CLK is NOT necessary
for system, and IMX7D_AHB_CHANNEL_ROOT_CLK is NOT existing
at all, remove them from clks_init_on array.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx7d.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
On i.MX7D, IMX7D_NAND_USDHC_BUS_ROOT_CLK is NOT necessary
for system, and IMX7D_AHB_CHANNEL_ROOT_CLK is NOT existing
at all, remove them from clks_init_on array.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx7d.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
From: Rob Landley
Avoids warning messages with the latest release of toybox, which never
bothered to implement the --longopts nothing was using.
Signed-off-by: Rob Landley
Signed-off-by: Masahiro Yamada
---
This was sent to the trivial ML some time ago,
but not applied yet.
I will apply
From: Rob Landley
Avoids warning messages with the latest release of toybox, which never
bothered to implement the --longopts nothing was using.
Signed-off-by: Rob Landley
Signed-off-by: Masahiro Yamada
---
This was sent to the trivial ML some time ago,
but not applied yet.
I will apply
On 8/7/2018 3:33 PM, Geert Uytterhoeven wrote:
Hi Songjun,
On Fri, Aug 3, 2018 at 5:04 AM Songjun Wu wrote:
Get serial id from dts.
"#ifdef CONFIG_LANTIQ" preprocessor is used because LTQ_EARLY_ASC
macro is defined in lantiq_soc.h.
lantiq_soc.h is in arch path for legacy product support.
On 8/7/2018 3:33 PM, Geert Uytterhoeven wrote:
Hi Songjun,
On Fri, Aug 3, 2018 at 5:04 AM Songjun Wu wrote:
Get serial id from dts.
"#ifdef CONFIG_LANTIQ" preprocessor is used because LTQ_EARLY_ASC
macro is defined in lantiq_soc.h.
lantiq_soc.h is in arch path for legacy product support.
Hi all,
Paolo pointed out a semantic conflict between the kvm tree and the tip
tree in
arch/x86/kernel/kvm.c
between commit:
368a540e0232 ("x86/kvmclock: Remove memblock dependency")
from the tip tree and commit:
d63bae079b64 ("KVM: X86: Add kvm hypervisor init time platform setup
Hi all,
Paolo pointed out a semantic conflict between the kvm tree and the tip
tree in
arch/x86/kernel/kvm.c
between commit:
368a540e0232 ("x86/kvmclock: Remove memblock dependency")
from the tip tree and commit:
d63bae079b64 ("KVM: X86: Add kvm hypervisor init time platform setup
On Tue, Aug 7, 2018 at 8:44 PM, Joel Fernandes wrote:
> Hi Steve,
>
> On Tue, Aug 7, 2018 at 7:28 PM, Steven Rostedt wrote:
[...]
>>> @@ -171,8 +174,7 @@ extern void syscall_unregfunc(void);
>>> } while ((++it_func_ptr)->func);\
>>> }
On Tue, Aug 7, 2018 at 8:44 PM, Joel Fernandes wrote:
> Hi Steve,
>
> On Tue, Aug 7, 2018 at 7:28 PM, Steven Rostedt wrote:
[...]
>>> @@ -171,8 +174,7 @@ extern void syscall_unregfunc(void);
>>> } while ((++it_func_ptr)->func);\
>>> }
On 08/07/2018 08:14 PM, Bjorn Helgaas wrote:
On Mon, Jul 30, 2018 at 06:35:31PM -0500, Alexandru Gagniuc wrote:
When we don't own AER, we shouldn't touch the AER error bits. Clearing
error bits willy-nilly might cause firmware to miss some errors. In
theory, these bits get cleared by FFS, or
On 08/07/2018 08:14 PM, Bjorn Helgaas wrote:
On Mon, Jul 30, 2018 at 06:35:31PM -0500, Alexandru Gagniuc wrote:
When we don't own AER, we shouldn't touch the AER error bits. Clearing
error bits willy-nilly might cause firmware to miss some errors. In
theory, these bits get cleared by FFS, or
Hi Steve,
On Tue, Aug 7, 2018 at 7:28 PM, Steven Rostedt wrote:
> On Tue, 7 Aug 2018 19:13:32 -0700
> Joel Fernandes wrote:
>> >
>> >> From 6986af946ceb04fc9ddc6d5b45fc559b6807e465 Mon Sep 17 00:00:00 2001
>> >> From: "Joel Fernandes (Google)"
>> >> Date: Sun, 5 Aug 2018 20:17:41 -0700
>> >>
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Wednesday, August 8, 2018 2:44 AM
> To: Bharat Bhushan ;
> b...@kernel.crashing.org; pau...@samba.org; m...@ellerman.id.au;
> ga...@kernel.crashing.org; mark.rutl...@arm.com;
> kstew...@linuxfoundation.org;
Hi Steve,
On Tue, Aug 7, 2018 at 7:28 PM, Steven Rostedt wrote:
> On Tue, 7 Aug 2018 19:13:32 -0700
> Joel Fernandes wrote:
>> >
>> >> From 6986af946ceb04fc9ddc6d5b45fc559b6807e465 Mon Sep 17 00:00:00 2001
>> >> From: "Joel Fernandes (Google)"
>> >> Date: Sun, 5 Aug 2018 20:17:41 -0700
>> >>
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Wednesday, August 8, 2018 2:44 AM
> To: Bharat Bhushan ;
> b...@kernel.crashing.org; pau...@samba.org; m...@ellerman.id.au;
> ga...@kernel.crashing.org; mark.rutl...@arm.com;
> kstew...@linuxfoundation.org;
Thomas Richter writes:
> Add support for s390 auxiliary trace support.
> Use 'perf record -e rbd000' to create the perf.data file.
> The event also has the symbolic name SF_CYCLES_BASIC_DIAG,
> using 'perf record -e SF_CYCLES_BASIC_DIAG' is equivalent.
...
>
> Signed-off-by: Thomas Richter
>
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Wednesday, August 8, 2018 2:34 AM
> To: Rob Herring ; Bharat Bhushan
>
> Cc: b...@kernel.crashing.org; pau...@samba.org; m...@ellerman.id.au;
> ga...@kernel.crashing.org; mark.rutl...@arm.com;
>
Thomas Richter writes:
> Add support for s390 auxiliary trace support.
> Use 'perf record -e rbd000' to create the perf.data file.
> The event also has the symbolic name SF_CYCLES_BASIC_DIAG,
> using 'perf record -e SF_CYCLES_BASIC_DIAG' is equivalent.
...
>
> Signed-off-by: Thomas Richter
>
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Wednesday, August 8, 2018 2:34 AM
> To: Rob Herring ; Bharat Bhushan
>
> Cc: b...@kernel.crashing.org; pau...@samba.org; m...@ellerman.id.au;
> ga...@kernel.crashing.org; mark.rutl...@arm.com;
>
FPU codes have been separated from common part in previous patches.
This patch add the CONFIG_FPU option and some stubs, so that a no-FPU
configuration is allowed.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
---
arch/riscv/Kconfig | 9
FPU codes have been separated from common part in previous patches.
This patch add the CONFIG_FPU option and some stubs, so that a no-FPU
configuration is allowed.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
---
arch/riscv/Kconfig | 9
We move __fstate_save and __fstate_restore to a new source
file, fpu.S.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/entry.S | 87 --
We move __fstate_save and __fstate_restore to a new source
file, fpu.S.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/entry.S | 87 --
We expect that a kernel with CONFIG_FPU=y can still support no-FPU machines.
To do so, the kernel should first examine the existence of a FPU, then
do nothing if a FPU does exist; otherwise, it should disable/bypass all
FPU-related functions.
In this patch, a new global variable, no_fpu, is
FPU-related logic is separated from normal signal handling path in
this patch. Kernel can easily be configured to exclude those procedures
for no-FPU systems.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
Just a side note: (Assume that atomic and compressed is on)
Before this patch, assembler was always given the riscv64imafdc
MARCH string because there are fld/fsd's in entry.S; compiler was
always given riscv64imac because kernel doesn't need floating point
code generation. After this, the MARCH
We expect that a kernel with CONFIG_FPU=y can still support no-FPU machines.
To do so, the kernel should first examine the existence of a FPU, then
do nothing if a FPU does exist; otherwise, it should disable/bypass all
FPU-related functions.
In this patch, a new global variable, no_fpu, is
FPU-related logic is separated from normal signal handling path in
this patch. Kernel can easily be configured to exclude those procedures
for no-FPU systems.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
Just a side note: (Assume that atomic and compressed is on)
Before this patch, assembler was always given the riscv64imafdc
MARCH string because there are fld/fsd's in entry.S; compiler was
always given riscv64imac because kernel doesn't need floating point
code generation. After this, the MARCH
This patchset adds an option, CONFIG_FPU, to enable/disable floating-
point procedures.
Kernel's new behavior will be as follows:
* with CONFIG_FPU=y
All FPU codes are reserved. If no FPU is found during booting, a
global flag will be set, and those functions will be bypassed with
This patchset adds an option, CONFIG_FPU, to enable/disable floating-
point procedures.
Kernel's new behavior will be as follows:
* with CONFIG_FPU=y
All FPU codes are reserved. If no FPU is found during booting, a
global flag will be set, and those functions will be bypassed with
Hi Trent,
On 8 August 2018 at 01:10, Trent Piepho wrote:
> On Tue, 2018-08-07 at 18:43 +0800, Baolin Wang wrote:
>>
>> +static u32 sprd_spi_transfer_max_timeout(struct sprd_spi *ss,
>> + struct spi_transfer *t)
>> +{
>> + /*
>> + * The time spent on
Hi Trent,
On 8 August 2018 at 01:10, Trent Piepho wrote:
> On Tue, 2018-08-07 at 18:43 +0800, Baolin Wang wrote:
>>
>> +static u32 sprd_spi_transfer_max_timeout(struct sprd_spi *ss,
>> + struct spi_transfer *t)
>> +{
>> + /*
>> + * The time spent on
On 8/6/2018 11:18 PM, Rob Herring wrote:
On Thu, Aug 2, 2018 at 9:03 PM Songjun Wu wrote:
From: Yixin Zhu
This patch adds binding documentation for grx500 clock controller.
Signed-off-by: YiXin Zhu
Signed-off-by: Songjun Wu
---
Changes in v2:
- Rewrite clock driver's dt-binding
On 8/6/2018 11:18 PM, Rob Herring wrote:
On Thu, Aug 2, 2018 at 9:03 PM Songjun Wu wrote:
From: Yixin Zhu
This patch adds binding documentation for grx500 clock controller.
Signed-off-by: YiXin Zhu
Signed-off-by: Songjun Wu
---
Changes in v2:
- Rewrite clock driver's dt-binding
Signed-off-by: Ryan Lee
---
Changes : Added 'MAX98373_R2000_SW_RESET' register to
'max98373_readable_register'
Software reset didn't work properly after suspend/resume.
sound/soc/codecs/max98373.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/soc/codecs/max98373.c
Signed-off-by: Ryan Lee
---
Changes : Added 'MAX98373_R2000_SW_RESET' register to
'max98373_readable_register'
Software reset didn't work properly after suspend/resume.
sound/soc/codecs/max98373.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/soc/codecs/max98373.c
On 08/07/2018 12:52 PM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.4.147 release.
> There are 12 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On 08/07/2018 12:52 PM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.4.147 release.
> There are 12 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On 08/07/2018 12:51 PM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.9.119 release.
> There are 17 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On 08/07/2018 12:51 PM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.9.119 release.
> There are 17 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On 08/07/2018 12:51 PM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.14.62 release.
> There are 21 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On 08/07/2018 12:51 PM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.14.62 release.
> There are 21 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On 08/07/2018 12:51 PM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.17.14 release.
> There are 18 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On 08/07/2018 12:51 PM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.17.14 release.
> There are 18 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On 08/07/2018 12:51 PM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 3.18.118 release.
> There are 85 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On 08/07/2018 12:51 PM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 3.18.118 release.
> There are 85 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On 8/6/2018 11:19 PM, Rob Herring wrote:
On Thu, Aug 2, 2018 at 9:03 PM Songjun Wu wrote:
From: Yixin Zhu
This driver provides PLL clock registration as well as various clock
branches, e.g. MUX clock, gate clock, divider clock and so on.
PLLs that provide clock to DDR, CPU and
On 8/6/2018 11:19 PM, Rob Herring wrote:
On Thu, Aug 2, 2018 at 9:03 PM Songjun Wu wrote:
From: Yixin Zhu
This driver provides PLL clock registration as well as various clock
branches, e.g. MUX clock, gate clock, divider clock and so on.
PLLs that provide clock to DDR, CPU and
On 8/8/2018 12:54 AM, skan...@codeaurora.org wrote:
On 2018-08-07 04:12, Sudeep Holla wrote:
On Mon, Aug 06, 2018 at 01:54:24PM -0700, skan...@codeaurora.org wrote:
On 2018-08-03 16:46, Stephen Boyd wrote:
>Quoting Taniya Das (2018-07-24 03:42:49)
>>diff --git
On 8/8/2018 12:54 AM, skan...@codeaurora.org wrote:
On 2018-08-07 04:12, Sudeep Holla wrote:
On Mon, Aug 06, 2018 at 01:54:24PM -0700, skan...@codeaurora.org wrote:
On 2018-08-03 16:46, Stephen Boyd wrote:
>Quoting Taniya Das (2018-07-24 03:42:49)
>>diff --git
Hi Mark,
On 7 August 2018 at 22:24, Mark Brown wrote:
> On Tue, Aug 07, 2018 at 06:43:38PM +0800, Baolin Wang wrote:
>> From: Lanqing Liu
>>
>> This patch adds the SPI controller driver for Spreadtrum SC9860 platform.
>
> This all looks pretty clean, a few comments below but nothing too major:
Hi Mark,
On 7 August 2018 at 22:24, Mark Brown wrote:
> On Tue, Aug 07, 2018 at 06:43:38PM +0800, Baolin Wang wrote:
>> From: Lanqing Liu
>>
>> This patch adds the SPI controller driver for Spreadtrum SC9860 platform.
>
> This all looks pretty clean, a few comments below but nothing too major:
On Tue, 7 Aug 2018 19:13:32 -0700
Joel Fernandes wrote:
> On Tue, Aug 7, 2018 at 6:55 PM, Steven Rostedt wrote:
> > On Tue, 7 Aug 2018 18:17:42 -0700
> > Joel Fernandes wrote:
> >
> >> From 6986af946ceb04fc9ddc6d5b45fc559b6807e465 Mon Sep 17 00:00:00 2001
> >> From: "Joel Fernandes (Google)"
On Tue, 7 Aug 2018 19:13:32 -0700
Joel Fernandes wrote:
> On Tue, Aug 7, 2018 at 6:55 PM, Steven Rostedt wrote:
> > On Tue, 7 Aug 2018 18:17:42 -0700
> > Joel Fernandes wrote:
> >
> >> From 6986af946ceb04fc9ddc6d5b45fc559b6807e465 Mon Sep 17 00:00:00 2001
> >> From: "Joel Fernandes (Google)"
Hi Mark,
On 7 August 2018 at 21:41, Mark Brown wrote:
> On Tue, Aug 07, 2018 at 06:43:37PM +0800, Baolin Wang wrote:
>
>> +Optional properties:
>> +- sprd,spi-interval: Specify the intervals of two SPI frames, which can be
>> + converted to the delay clock cycles = interval number * 4 + 10.
Hi Mark,
On 7 August 2018 at 21:41, Mark Brown wrote:
> On Tue, Aug 07, 2018 at 06:43:37PM +0800, Baolin Wang wrote:
>
>> +Optional properties:
>> +- sprd,spi-interval: Specify the intervals of two SPI frames, which can be
>> + converted to the delay clock cycles = interval number * 4 + 10.
2018-08-08 11:14 GMT+09:00 Masahiro Yamada :
> Kernel headers must be installed into $(objtree)/usr/include to avoid
> the build failure of samples.
>
> Commit ddea05fa148b ("kbuild: make samples depend on headers_install")
> addressed this, but "samples/" is only used for the single target build.
2018-08-08 11:14 GMT+09:00 Masahiro Yamada :
> Kernel headers must be installed into $(objtree)/usr/include to avoid
> the build failure of samples.
>
> Commit ddea05fa148b ("kbuild: make samples depend on headers_install")
> addressed this, but "samples/" is only used for the single target build.
On Sat, 04 Aug 2018 01:23:11 PDT (-0700), Christoph Hellwig wrote:
This series tries adds support for interrupt handling and timers
for the RISC-V architecture.
The basic per-hart interrupt handling implemented by the scause
and sie CSRs is extremely simple and implemented directly in
On Sat, 04 Aug 2018 01:23:11 PDT (-0700), Christoph Hellwig wrote:
This series tries adds support for interrupt handling and timers
for the RISC-V architecture.
The basic per-hart interrupt handling implemented by the scause
and sie CSRs is extremely simple and implemented directly in
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