flush_tlb_kernel_range() is only ever used to invalidate last-level
entries, so we can restrict the scope of the TLB invalidation
instruction.
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/tlbflush.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
flush_tlb_kernel_range() is only ever used to invalidate last-level
entries, so we can restrict the scope of the TLB invalidation
instruction.
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/tlbflush.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Now that our walk-cache invalidation routines imply a DSB before the
invalidation, we no longer need one when we are clearing an entry during
unmap.
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/pgtable.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git
Now that our walk-cache invalidation routines imply a DSB before the
invalidation, we no longer need one when we are clearing an entry during
unmap.
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/pgtable.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git
From: Peter Zijlstra
Some architectures require different TLB invalidation instructions
depending on whether it is only the last-level of page table being
changed, or whether there are also changes to the intermediate
(directory) entries higher up the tree.
Add a new bit to the flags bitfield
__flush_tlb_[kernel_]pgtable() rely on set_pXd() having a DSB after
writing the new table entry and therefore avoid the barrier prior to the
TLBI instruction.
In preparation for delaying our walk-cache invalidation on the unmap()
path, move the DSB into the TLB invalidation routines.
From: Peter Zijlstra
Some architectures require different TLB invalidation instructions
depending on whether it is only the last-level of page table being
changed, or whether there are also changes to the intermediate
(directory) entries higher up the tree.
Add a new bit to the flags bitfield
__flush_tlb_[kernel_]pgtable() rely on set_pXd() having a DSB after
writing the new table entry and therefore avoid the barrier prior to the
TLBI instruction.
In preparation for delaying our walk-cache invalidation on the unmap()
path, move the DSB into the TLB invalidation routines.
The inner workings of the mmu_gather-based TLB invalidation mechanism
are not relevant to nommu configurations, so guard them with an #ifdef.
This allows us to implement future functions using static inlines
without breaking the build.
Signed-off-by: Will Deacon
---
include/asm-generic/tlb.h |
The inner workings of the mmu_gather-based TLB invalidation mechanism
are not relevant to nommu configurations, so guard them with an #ifdef.
This allows us to implement future functions using static inlines
without breaking the build.
Signed-off-by: Will Deacon
---
include/asm-generic/tlb.h |
If there's one thing the RCU-based table freeing doesn't need, it's more
ifdeffery.
Remove the redundant !CONFIG_HAVE_RCU_TABLE_FREE code, since this option
is unconditionally selected in our Kconfig.
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/tlb.h | 12 +++-
1 file
If there's one thing the RCU-based table freeing doesn't need, it's more
ifdeffery.
Remove the redundant !CONFIG_HAVE_RCU_TABLE_FREE code, since this option
is unconditionally selected in our Kconfig.
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/tlb.h | 12 +++-
1 file
Add a comment to explain why we can't get away with last-level
invalidation in flush_tlb_range()
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/tlbflush.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h
b/arch/arm64/include/asm/tlbflush.h
index
When we are unmapping intermediate page-table entries or huge pages, we
don't need to issue a TLBI instruction for every PAGE_SIZE chunk in the
VA range being unmapped.
Allow the invalidation stride to be passed to __flush_tlb_range(), and
adjust our "just nuke the ASID" heuristic to take this
Add a comment to explain why we can't get away with last-level
invalidation in flush_tlb_range()
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/tlbflush.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h
b/arch/arm64/include/asm/tlbflush.h
index
When we are unmapping intermediate page-table entries or huge pages, we
don't need to issue a TLBI instruction for every PAGE_SIZE chunk in the
VA range being unmapped.
Allow the invalidation stride to be passed to __flush_tlb_range(), and
adjust our "just nuke the ASID" heuristic to take this
By selecting HAVE_RCU_TABLE_INVALIDATE, we can rely on tlb_flush() being
called if we fail to batch table pages for freeing. This in turn allows
us to postpone walk-cache invalidation until tlb_finish_mmu(), which
avoids lots of unnecessary DSBs and means we can shoot down the ASID if
the range is
By selecting HAVE_RCU_TABLE_INVALIDATE, we can rely on tlb_flush() being
called if we fail to batch table pages for freeing. This in turn allows
us to postpone walk-cache invalidation until tlb_finish_mmu(), which
avoids lots of unnecessary DSBs and means we can shoot down the ASID if
the range is
Peter Z asked me to justify the barrier usage in asm/tlbflush.h, but
actually that whole block comment needs to be rewritten.
Reported-by: Peter Zijlstra
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/tlbflush.h | 80 +++
1 file changed, 55
Peter Z asked me to justify the barrier usage in asm/tlbflush.h, but
actually that whole block comment needs to be rewritten.
Reported-by: Peter Zijlstra
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/tlbflush.h | 80 +++
1 file changed, 55
Now that the core mmu_gather code keeps track of both the levels of page
table cleared and also whether or not these entries correspond to
intermediate entries, we can use this in our tlb_flush() callback to
reduce the number of invalidations we issue as well as their scope.
Signed-off-by: Will
Now that the core mmu_gather code keeps track of both the levels of page
table cleared and also whether or not these entries correspond to
intermediate entries, we can use this in our tlb_flush() callback to
reduce the number of invalidations we issue as well as their scope.
Signed-off-by: Will
It is common for architectures with hugepage support to require only a
single TLB invalidation operation per hugepage during unmap(), rather than
iterating through the mapping at a PAGE_SIZE increment. Currently,
however, the level in the page table where the unmap() operation occurs
is not stored
It is common for architectures with hugepage support to require only a
single TLB invalidation operation per hugepage during unmap(), rather than
iterating through the mapping at a PAGE_SIZE increment. Currently,
however, the level in the page table where the unmap() operation occurs
is not stored
On 8/30/18 7:41 AM, Christoph Hellwig wrote:
struct device_node *dn = NULL;
- int hart, im_okay_therefore_i_am = 0;
+ int hart, found_boot_cpu = 0;
If you rename this anyway please switch to use a bool.
I can address the comment on this patch and fold it in my series to
On 8/30/18 7:41 AM, Christoph Hellwig wrote:
struct device_node *dn = NULL;
- int hart, im_okay_therefore_i_am = 0;
+ int hart, found_boot_cpu = 0;
If you rename this anyway please switch to use a bool.
I can address the comment on this patch and fold it in my series to
Good day,
Did you receive my previous message?Just so You know,I want you and I to
work together as partners.
I would explain what this entails when I hear from you.
Thank You.
Helen.
Good day,
Did you receive my previous message?Just so You know,I want you and I to
work together as partners.
I would explain what this entails when I hear from you.
Thank You.
Helen.
On 8/30/18 7:18 AM, Anup Patel wrote:
On Thu, Aug 30, 2018 at 10:11 AM, Christoph Hellwig wrote:
On Thu, Aug 30, 2018 at 09:53:50AM -0400, Anup Patel wrote:
Atish Patra (3):
RISC-V: Add logical CPU indexing for RISC-V
RISC-V: Use Linux logical cpu number instead of hartid
RISC-V:
On 8/30/18 7:18 AM, Anup Patel wrote:
On Thu, Aug 30, 2018 at 10:11 AM, Christoph Hellwig wrote:
On Thu, Aug 30, 2018 at 09:53:50AM -0400, Anup Patel wrote:
Atish Patra (3):
RISC-V: Add logical CPU indexing for RISC-V
RISC-V: Use Linux logical cpu number instead of hartid
RISC-V:
On Mon, Aug 27, 2018 at 3:22 AM Johan Hovold wrote:
>
> Add of_get_compatible_child() helper that can be used to lookup
> compatible child nodes.
>
> Several drivers currently use of_find_compatible_node() to lookup child
> nodes while failing to notice that the of_find_ functions search the
>
On Mon, Aug 27, 2018 at 3:22 AM Johan Hovold wrote:
>
> Add of_get_compatible_child() helper that can be used to lookup
> compatible child nodes.
>
> Several drivers currently use of_find_compatible_node() to lookup child
> nodes while failing to notice that the of_find_ functions search the
>
On Thu, 30 Aug 2018 16:12:18 +0900
Masami Hiramatsu wrote:
> > I'm fine with this, but one day I need to port over some of my other
> > tests. I have a test that stresses the ring buffer size (basically
> > checks to see if it can cause an oom). I need to port that to
> > selftests. But for
On Thu, 30 Aug 2018 16:12:18 +0900
Masami Hiramatsu wrote:
> > I'm fine with this, but one day I need to port over some of my other
> > tests. I have a test that stresses the ring buffer size (basically
> > checks to see if it can cause an oom). I need to port that to
> > selftests. But for
On Wed, Aug 29, 2018 at 12:00 AM Christoph Hellwig wrote:
>
> > config ANDROID_BINDER_IPC
> > bool "Android Binder IPC Driver"
> > - depends on MMU
> > + depends on MMU && !CPU_CACHE_VIVT
>
> Thats is a purely arm specific symbol which should not be
> used in common code.
On Wed, Aug 29, 2018 at 12:00 AM Christoph Hellwig wrote:
>
> > config ANDROID_BINDER_IPC
> > bool "Android Binder IPC Driver"
> > - depends on MMU
> > + depends on MMU && !CPU_CACHE_VIVT
>
> Thats is a purely arm specific symbol which should not be
> used in common code.
On Wed, 29 Aug 2018 21:10:17 -0700
"Paul E. McKenney" wrote:
> On Wed, Aug 29, 2018 at 08:22:16PM -0700, Paul E. McKenney wrote:
> > On Wed, Aug 29, 2018 at 10:00:26PM -0400, Steven Rostedt wrote:
> > > On Wed, 29 Aug 2018 15:38:30 -0700
> > > "Paul E. McKenney" wrote:
> > >
> > > > Hello!
On Wed, 29 Aug 2018 21:10:17 -0700
"Paul E. McKenney" wrote:
> On Wed, Aug 29, 2018 at 08:22:16PM -0700, Paul E. McKenney wrote:
> > On Wed, Aug 29, 2018 at 10:00:26PM -0400, Steven Rostedt wrote:
> > > On Wed, 29 Aug 2018 15:38:30 -0700
> > > "Paul E. McKenney" wrote:
> > >
> > > > Hello!
On Wed, 29 Aug 2018 21:20:07 -0700
Josh Triplett wrote:
> > And please see below for what the resulting diff would look like. Is
> > this an improvement?
>
> Honestly, as long as the result after each commit compiles, I prefer the
> split version for ease of review.
You and I have
On Wed, 29 Aug 2018 21:20:07 -0700
Josh Triplett wrote:
> > And please see below for what the resulting diff would look like. Is
> > this an improvement?
>
> Honestly, as long as the result after each commit compiles, I prefer the
> split version for ease of review.
You and I have
On 08/30/2018 02:22 AM, Rong Chen wrote:
>
>
> On 08/24/2018 12:55 AM, Dave Jiang wrote:
>> I am not able to reproduce when I booted my test system with "mem=8G
>> memmap=4G!8G". I ended up with a single pmem:
> The issue seems to be related to specific machines,
> If you need any other debug
On 08/30/2018 02:22 AM, Rong Chen wrote:
>
>
> On 08/24/2018 12:55 AM, Dave Jiang wrote:
>> I am not able to reproduce when I booted my test system with "mem=8G
>> memmap=4G!8G". I ended up with a single pmem:
> The issue seems to be related to specific machines,
> If you need any other debug
On 08/30/2018 03:22 AM, Manish Narani wrote:
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 4a75492..405ea00 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -941,4 +941,14 @@ config XILINX_XADC
> The driver can also be build as a
On 08/30/2018 03:22 AM, Manish Narani wrote:
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 4a75492..405ea00 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -941,4 +941,14 @@ config XILINX_XADC
> The driver can also be build as a
Hello,
syzbot found the following crash on:
HEAD commit:58c3f14f86c9 Merge tag 'riscv-for-linus-4.19-rc2' of git:/..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=10be176a40
kernel config: https://syzkaller.appspot.com/x/.config?x=531a917630d2a492
Hello,
syzbot found the following crash on:
HEAD commit:58c3f14f86c9 Merge tag 'riscv-for-linus-4.19-rc2' of git:/..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=10be176a40
kernel config: https://syzkaller.appspot.com/x/.config?x=531a917630d2a492
Hi,
On Mon, Jul 9, 2018 at 4:17 AM, Linus Walleij wrote:
> On Tue, Jul 3, 2018 at 8:09 AM Stephen Boyd wrote:
>
>> > Fixes: eadff3024472 ("pinctrl: Qualcomm SPMI PMIC GPIO pin controller
>> > driver")
>> > Signed-off-by: Douglas Anderson
>>
>> We should fix the ssbi-gpio/mpp and spmi-mpp
Hi,
On Mon, Jul 9, 2018 at 4:17 AM, Linus Walleij wrote:
> On Tue, Jul 3, 2018 at 8:09 AM Stephen Boyd wrote:
>
>> > Fixes: eadff3024472 ("pinctrl: Qualcomm SPMI PMIC GPIO pin controller
>> > driver")
>> > Signed-off-by: Douglas Anderson
>>
>> We should fix the ssbi-gpio/mpp and spmi-mpp
From: cphlip...@gmail.com
> Sent: 30 August 2018 03:20
>
> Some implementations of libc do not support the 'm' width modifier
> as part of the scanf string format specifier. This can cause the
> parsing to fail. Since the parser never checks if the scanf
> parsing was successesful, this can
From: cphlip...@gmail.com
> Sent: 30 August 2018 03:20
>
> Some implementations of libc do not support the 'm' width modifier
> as part of the scanf string format specifier. This can cause the
> parsing to fail. Since the parser never checks if the scanf
> parsing was successesful, this can
Hi Kirill,
I made a new version according to your suggestion, just a little
different, I didn't make 1TB as default, just calculate with the actual
size, then align up to 1TB boundary. Just found kcore is printing more
entries than before, I thought it's caused by my code, later got it was
Hi Kirill,
I made a new version according to your suggestion, just a little
different, I didn't make 1TB as default, just calculate with the actual
size, then align up to 1TB boundary. Just found kcore is printing more
entries than before, I thought it's caused by my code, later got it was
If you look at "pinconf-groups" in debugfs for ssbi-gpio you'll notice
it looks like nonsense.
The problem is fairly well described in commit 1cf86bc21257 ("pinctrl:
qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliant") and
commit 05e0c828955c ("pinctrl: msm: Fix msm_config_group_get() to
If you look at "pinconf-groups" in debugfs for ssbi-gpio you'll notice
it looks like nonsense.
The problem is fairly well described in commit 1cf86bc21257 ("pinctrl:
qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliant") and
commit 05e0c828955c ("pinctrl: msm: Fix msm_config_group_get() to
If you look at "pinconf-groups" in debugfs for ssbi-mpp you'll notice
it looks like nonsense.
The problem is fairly well described in commit 1cf86bc21257 ("pinctrl:
qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliant") and
commit 05e0c828955c ("pinctrl: msm: Fix msm_config_group_get() to
If you look at "pinconf-groups" in debugfs for ssbi-mpp you'll notice
it looks like nonsense.
The problem is fairly well described in commit 1cf86bc21257 ("pinctrl:
qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliant") and
commit 05e0c828955c ("pinctrl: msm: Fix msm_config_group_get() to
I have no way to test the patches in this series, but Stephen Boyd
pointed out the problems being fixed here when he reviewed my patch
("pinctrl: qcom: spmi-gpio: Fix pmic_gpio_config_get() to be
compliant"). It seemed nice to (finally) follow-up and address the
problems that Stephen found.
I have no way to test the patches in this series, but Stephen Boyd
pointed out the problems being fixed here when he reviewed my patch
("pinctrl: qcom: spmi-gpio: Fix pmic_gpio_config_get() to be
compliant"). It seemed nice to (finally) follow-up and address the
problems that Stephen found.
On Wed, Aug 15, 2018 at 10:03:13AM -0700, Song Liu wrote:
SNIP
> @@ -6100,7 +6333,7 @@ static void perf_output_read_group(struct
> perf_output_handle *handle,
>
> if ((sub != event) &&
> (sub->state == PERF_EVENT_STATE_ACTIVE))
> -
On Wed, Aug 15, 2018 at 10:03:13AM -0700, Song Liu wrote:
SNIP
> @@ -6100,7 +6333,7 @@ static void perf_output_read_group(struct
> perf_output_handle *handle,
>
> if ((sub != event) &&
> (sub->state == PERF_EVENT_STATE_ACTIVE))
> -
On Wed, Aug 15, 2018 at 10:03:13AM -0700, Song Liu wrote:
SNIP
>
> + perf_event_remove_dup(event, ctx);
> /*
>* We can have double detach due to exit/hot-unplug + close.
>*/
> @@ -1982,6 +2123,92 @@ event_filter_match(struct perf_event *event)
>
On Wed, Aug 15, 2018 at 10:03:13AM -0700, Song Liu wrote:
SNIP
>
> + perf_event_remove_dup(event, ctx);
> /*
>* We can have double detach due to exit/hot-unplug + close.
>*/
> @@ -1982,6 +2123,92 @@ event_filter_match(struct perf_event *event)
>
On Thu, Aug 30, 2018 at 05:05:19PM +0200, Thomas Gleixner wrote:
> Commit 0a0e0829f990 ("nohz: Fix missing tick reprogram when interrupting an
> inline softirq") got backported to stable trees and now causes the NOHZ
> softirq pending warning to trigger. It's not an upstream issue as the NOHZ
>
On Thu, Aug 30, 2018 at 05:05:19PM +0200, Thomas Gleixner wrote:
> Commit 0a0e0829f990 ("nohz: Fix missing tick reprogram when interrupting an
> inline softirq") got backported to stable trees and now causes the NOHZ
> softirq pending warning to trigger. It's not an upstream issue as the NOHZ
>
On August 30, 2018 5:20:32 PM GMT+03:00, wufan wrote:
>> > +static int ghes_edac_dimm_index(u16 handle)
>>
>> get_dimm_smbios_handle()
>
>This function returns an index. So how about get_dimm_smbios_index()?
Sure.
--
Sent from a small device: formatting sux and brevity is inevitable.
On August 30, 2018 5:20:32 PM GMT+03:00, wufan wrote:
>> > +static int ghes_edac_dimm_index(u16 handle)
>>
>> get_dimm_smbios_handle()
>
>This function returns an index. So how about get_dimm_smbios_index()?
Sure.
--
Sent from a small device: formatting sux and brevity is inevitable.
Hi Marek,
On jeu., août 30 2018, Marek Behún wrote:
> This adds support for the Turris Mox board from CZ.NIC.
>
> Turris Mox is as modular router based on the Armada 3720 SOC (same as
> EspressoBin).
>
> The basic module can be extended by different modules.
> When those modules are
Hi Marek,
On jeu., août 30 2018, Marek Behún wrote:
> This adds support for the Turris Mox board from CZ.NIC.
>
> Turris Mox is as modular router based on the Armada 3720 SOC (same as
> EspressoBin).
>
> The basic module can be extended by different modules.
> When those modules are
Automatic pad drive strength calibration is performed on a separate pad
identical to the ones used for driving the actual bus. Power on the
calibration pad during the calibration procedure and power it off
afterwards to save power.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
Automatic pad drive strength calibration is performed on a separate pad
identical to the ones used for driving the actual bus. Power on the
calibration pad during the calibration procedure and power it off
afterwards to save power.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
Use assigned-clock properties to configure pllc4 as the parent clock
for sdmmc4 on Tegra210. pllc4 offers better jitter perfomance than
the default pllp and is required by HS200 and HS400 modes.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi |
Use assigned-clock properties to configure pllc4 as the parent clock
for sdmmc4 on Tegra210. pllc4 offers better jitter perfomance than
the default pllp and is required by HS200 and HS400 modes.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi |
Add SDHCI inbound and outbound SDHCI sampling trimmer values for
Tegra210.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
Configure sdmmc4 parent clock to pllc4 and sdmmc1 to pllp_out0 by
setting the assigned-clocks device tree properties. pllc4 offer
better jitter performance and should be used with higher speed
modes like HS200 and HS400.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
Add SDHCI inbound and outbound SDHCI sampling trimmer values for
Tegra210.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
Configure sdmmc4 parent clock to pllc4 and sdmmc1 to pllp_out0 by
setting the assigned-clocks device tree properties. pllc4 offer
better jitter performance and should be used with higher speed
modes like HS200 and HS400.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
Add SDHCI inbound and outbound SDHCI sampling trimmer values for
Tegra186.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
Add SDHCI inbound and outbound SDHCI sampling trimmer values for
Tegra186.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
On p2180 sdmmc4 is powered from a fixed 1.8 V regulator.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
Set regulator-min-microvolt property of ldo2 to 1.8 V in
tegra210-p2180.dtsi. ldo2 is used by the sdmmc1 SDHCI controller and its
voltage needs to be adjusted down to 1.8 V to support faster signaling
modes. It appears that the comment about the SDHCI driver requesting
invalid voltages no longer
On p2180 sdmmc4 is powered from a fixed 1.8 V regulator.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
Set regulator-min-microvolt property of ldo2 to 1.8 V in
tegra210-p2180.dtsi. ldo2 is used by the sdmmc1 SDHCI controller and its
voltage needs to be adjusted down to 1.8 V to support faster signaling
modes. It appears that the comment about the SDHCI driver requesting
invalid voltages no longer
Add the calibration offset properties used for automatic pad drive
strength calibration.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 20
1 file changed, 20 insertions(+)
diff --git
Add the calibration offset properties used for automatic pad drive
strength calibration.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
Allow sdmmc1 to set the signaling voltage to 1.8 V in order to support
faster signaling modes.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git
Add the calibration offset properties used for automatic pad drive
strength calibration.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 20
1 file changed, 20 insertions(+)
diff --git
Add the calibration offset properties used for automatic pad drive
strength calibration.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
Allow sdmmc1 to set the signaling voltage to 1.8 V in order to support
faster signaling modes.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git
Set nvquirks to enable higher speed modes.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
drivers/mmc/host/sdhci-tegra.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index
Add pad voltage configuration nodes for sdmmc pads with configurable
voltages on Tegra210.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 27
1 file changed, 27 insertions(+)
diff --git
Add pad voltage configuration nodes for sdmmc pads with configurable
voltages on Tegra186.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 40
1 file changed, 40 insertions(+)
diff --git
Add a new sdhci_ops struct for Tegra210 and Tegra186 which doesn't
set the custom tuning callback used on previous SoC generations.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
drivers/mmc/host/sdhci-tegra.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
tegra_sdhci_writew() defers the write to SDHCI_TRANSFER_MODE until
SDHCI_COMMAND is written. This is not necessary on Tegra210 and Tegra186
and it breaks read-modify-write operations on SDHCI_TRANSFER_MODE
because writes to SDHCI_TRANSFER_MODE aren't visible until SDHCI_COMMAND
has been written
Implement tegra210_sdhci_writew() to disable card clock and issue a
reset when the tuning command is sent. This is done to prevent an
intermittent hang with around 10 % failure rate during tuning.
Add tegra186_sdhci_ops because this workaround is specific to Tegra210.
Signed-off-by: Aapo Vienamo
Set nvquirks to enable higher speed modes.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
drivers/mmc/host/sdhci-tegra.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index
Add pad voltage configuration nodes for sdmmc pads with configurable
voltages on Tegra210.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 27
1 file changed, 27 insertions(+)
diff --git
Add pad voltage configuration nodes for sdmmc pads with configurable
voltages on Tegra186.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
Acked-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 40
1 file changed, 40 insertions(+)
diff --git
Add a new sdhci_ops struct for Tegra210 and Tegra186 which doesn't
set the custom tuning callback used on previous SoC generations.
Signed-off-by: Aapo Vienamo
Acked-by: Thierry Reding
---
drivers/mmc/host/sdhci-tegra.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
tegra_sdhci_writew() defers the write to SDHCI_TRANSFER_MODE until
SDHCI_COMMAND is written. This is not necessary on Tegra210 and Tegra186
and it breaks read-modify-write operations on SDHCI_TRANSFER_MODE
because writes to SDHCI_TRANSFER_MODE aren't visible until SDHCI_COMMAND
has been written
Implement tegra210_sdhci_writew() to disable card clock and issue a
reset when the tuning command is sent. This is done to prevent an
intermittent hang with around 10 % failure rate during tuning.
Add tegra186_sdhci_ops because this workaround is specific to Tegra210.
Signed-off-by: Aapo Vienamo
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