On 2 October 2018 at 14:30, Jason A. Donenfeld wrote:
> Hi Arnd,
>
> On Tue, Oct 2, 2018 at 9:58 AM Arnd Bergmann wrote:
>> > I think we're going to wind up playing whack-a-mole in silly ways. The
>> > fact of the matter is that the ARM assembly I'm adding to the tree is
>> > for ARMv4 and up, an
On Tue, Oct 02, 2018 at 10:11:20AM +0200, Lukasz Majewski wrote:
> > As documented in SubmittingPatches please send patches to the
> > maintainers for the code you would like to change.
> I'm using the ./scripts/get_maintainer.py script to obtain list of
> relevant people.
Your patch went to t
On Tuesday 02 Oct 2018 at 14:34:16 (+0200), Peter Zijlstra wrote:
> On Wed, Sep 12, 2018 at 10:13:00AM +0100, Quentin Perret wrote:
> > In order to make sure Energy Aware Scheduling (EAS) doesn't hurt
> > systems not using it, add a new sched_feat, called ENERGY_AWARE,
> > guarding the access to EA
On Tue, Oct 02, 2018 at 09:43:17AM +0300, Matti Vaittinen wrote:
> tree is correct way to go, right? I'll prepare one against Mark's branch
> "origin/topic/bd718xx". Mark, please let me know if you want me to send
> it or if I should do it on top of some other branch.
That branch is good, thanks!
at91sam9x5cm comes with a 2Gb NAND flash. Fix the rootfs size to
match this limit.
Signed-off-by: Tudor Ambarus
Acked-by: Ludovic Desroches
---
v2:
- collect Ludovic's Acked-by
arch/arm/boot/dts/at91sam9x5cm.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot
sama5d4_xplained comes with a 4Gb NAND flash. Increase the rootfs
size to match this limit.
Signed-off-by: Tudor Ambarus
Acked-by: Ludovic Desroches
---
v2:
- fix typo in subject line
- collect Ludovic's Acked-by
arch/arm/boot/dts/at91-sama5d4_xplained.dts | 2 +-
1 file changed, 1 insertion(+
On Tue, Oct 02, 2018 at 02:18:17PM +0200, Torsten Duwe wrote:
> Hi Mark,
Hi,
> thank you for your very detailed feedback, I'll incorporate it
> all into the next version, besides one issue:
>
> On Tue, Oct 02, 2018 at 12:27:41PM +0100, Mark Rutland wrote:
> >
> > Please use the insn framework,
On 10/02/2018 06:08 PM, Suzuki K Poulose wrote:
> Hi Anshuman
>
> On 02/10/18 13:15, Anshuman Khandual wrote:
>> Architectures like arm64 have PUD level HugeTLB pages for certain configs
>> (1GB huge page is PUD based on ARM64_4K_PAGES base page size) that can be
>> enabled for migration. It ca
On Tuesday 02 Oct 2018 at 14:25:35 (+0200), Peter Zijlstra wrote:
> On Wed, Sep 12, 2018 at 10:12:58AM +0100, Quentin Perret wrote:
> > +/**
> > + * em_pd_energy() - Estimates the energy consumed by the CPUs of a perf.
> > domain
> > + * @pd : performance domain for which energy has to
On Tuesday 02 Oct 2018 at 14:30:31 (+0200), Peter Zijlstra wrote:
> On Wed, Sep 12, 2018 at 10:12:58AM +0100, Quentin Perret wrote:
> > +/**
> > + * em_register_perf_domain() - Register the Energy Model of a performance
> > domain
> > + * @span : Mask of CPUs in the performance domain
> > + * @n
On Tue, Oct 2, 2018 at 2:26 PM Timur Tabi wrote:
> On 10/2/18 2:38 AM, Linus Walleij wrote:
> >> But as today the only driver that seems to be using valid_mask is msm,
> >> so perhaps a hack is something better and then when we have a second
> >> driver that requires it we figure out the real requ
>
> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> index 25c7c7e09cbd..7fc4a371bdd2 100644
> --- a/kernel/sched/fair.c
> +++ b/kernel/sched/fair.c
> @@ -1392,6 +1392,17 @@ bool should_numa_migrate_memory(struct task_struct *p,
> struct page * page,
> int last_cpupid, this_cpupid;
>
On Tue 02-10-18 17:45:28, Anshuman Khandual wrote:
> Architectures like arm64 have PUD level HugeTLB pages for certain configs
> (1GB huge page is PUD based on ARM64_4K_PAGES base page size) that can be
> enabled for migration. It can be achieved through checking for PUD_SHIFT
> order based HugeTLB
Hi Anshuman
On 02/10/18 13:15, Anshuman Khandual wrote:
Architectures like arm64 have PUD level HugeTLB pages for certain configs
(1GB huge page is PUD based on ARM64_4K_PAGES base page size) that can be
enabled for migration. It can be achieved through checking for PUD_SHIFT
order based HugeTLB
Hi Tudor,
There is a typo is your subject line.I don't have any other comment ;)
On 02/10/2018 14:29:48+0300, Tudor Ambarus wrote:
> sama5d4_xplained comes with a 4Gb NAND flash. Increase the rootfs
> size to match this limit.
>
> Signed-off-by: Tudor Ambarus
> ---
> arch/arm/boot/dts/at91-sam
On Wed, Sep 12, 2018 at 10:13:01AM +0100, Quentin Perret wrote:
> +struct perf_domain {
> + struct em_perf_domain *obj;
> + struct perf_domain *next;
> + struct rcu_head rcu;
> +};
Maybe s/obj/em_pd/ or something like that? @obj is so very opaque.
On Wed, Sep 12, 2018 at 10:13:00AM +0100, Quentin Perret wrote:
> In order to make sure Energy Aware Scheduling (EAS) doesn't hurt
> systems not using it, add a new sched_feat, called ENERGY_AWARE,
> guarding the access to EAS code paths.
>
> Signed-off-by: Quentin Perret
> ---
> kernel/sched/fe
Pavel
On 10/02/2018 02:56 AM, Pavel Machek wrote:
> On Fri 2018-09-28 13:29:46, Dan Murphy wrote:
>> From: Pavel Machek
>>
>> This adds backlight support for the following TI LMU
>> chips: LM3532, LM3631, LM3632, LM3633, LM3695 and LM3697.
>>
>> It controls LEDs on Droid 4
>> smartphone, includin
> consider this scenario with your patch:
>
> 1. CPU0 sees a locked val, and is about to do your xchg_relaxed() to set
>pending.
>
> 2. CPU1 comes in and sets pending, spins on locked
>
> 3. CPU2 sees a pending and locked val, and is about to enter the head of
>the waitqueue (i.e. it's r
On Wed, Sep 12, 2018 at 10:12:58AM +0100, Quentin Perret wrote:
> +/**
> + * em_register_perf_domain() - Register the Energy Model of a performance
> domain
> + * @span : Mask of CPUs in the performance domain
> + * @nr_states: Number of capacity states to register
> + * @cb
Hi Arnd,
On Tue, Oct 2, 2018 at 9:58 AM Arnd Bergmann wrote:
> > I think we're going to wind up playing whack-a-mole in silly ways. The
> > fact of the matter is that the ARM assembly I'm adding to the tree is
> > for ARMv4 and up, and not for ARMv3.
>
> I don't see what issues remain. The 'reteq
On 10/2/18 3:27 AM, Ricardo Ribalda Delgado wrote:
+ /* REVISIT: most hardware initializes GPIOs as inputs (often
+* with pullups enabled) so power usage is minimized. Linux
+* code should set the gpio direction first thing; but until
+
On Fri, 28 Sep 2018 13:16:01 +0900
Masahiro Yamada wrote:
> NAND devices need additional data area (OOB) for error correction,
> but it is also used for Bad Block Marker (BBM). In many cases, the
> first byte in OOB is used for BBM, but the location actually depends
> on chip vendors. The NAND
On 10/2/18 2:38 AM, Linus Walleij wrote:
But as today the only driver that seems to be using valid_mask is msm,
so perhaps a hack is something better and then when we have a second
driver that requires it we figure out the real requirements. But it is
definately your decision;)
Please note that
On Wed, Sep 12, 2018 at 10:12:58AM +0100, Quentin Perret wrote:
> +/**
> + * em_pd_energy() - Estimates the energy consumed by the CPUs of a perf.
> domain
> + * @pd : performance domain for which energy has to be
> estimated
> + * @max_util : highest utilization among CPUs of the d
Hi Mark,
thank you for your very detailed feedback, I'll incorporate it
all into the next version, besides one issue:
On Tue, Oct 02, 2018 at 12:27:41PM +0100, Mark Rutland wrote:
>
> Please use the insn framework, as we do to generate all the other
> instruction sequences in ftrace.
>
> MOV (r
Both the header and the command parameters of the fsl_mc_command are
64-bit little-endian words. Use the appropriate type to explicitly
specify their endianness.
Signed-off-by: Ioana Ciornei
---
include/linux/fsl/mc.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
Let arm64 subscribe to the previously added framework in which architecture
can inform whether a given huge page size is supported for migration. This
just overrides the default function arch_hugetlb_migration_supported() and
enables migration for all possible HugeTLB page sizes on arm64. With this
Let arm64 subscribe to generic HugeTLB page migration framework. Right now
this only works on the following PMD and PUD level HugeTLB page sizes with
various kernel base page size combinations.
CONT PTEPMDCONT PMDPUD
------
4K: NA 2
This patch series enables HugeTLB migration support for all supported
huge page sizes at all levels including contiguous bit implementation.
Following HugeTLB migration support matrix has been enabled with this
patch series. All permutations have been tested except for the 16GB.
CONT PTE
Architectures like arm64 have HugeTLB page sizes which are different than
generic sizes at PMD, PUD, PGD level and implemented via contiguous bits.
At present these special size HugeTLB pages cannot be identified through
macros like (PMD|PUD|PGDIR)_SHIFT and hence chosen not be migrated.
Enabling
Architectures like arm64 have PUD level HugeTLB pages for certain configs
(1GB huge page is PUD based on ARM64_4K_PAGES base page size) that can be
enabled for migration. It can be achieved through checking for PUD_SHIFT
order based HugeTLB pages during migration.
Signed-off-by: Anshuman Khandual
On Tue, 2 Oct 2018, Juergen Gross wrote:
> Sorry for noticing this only now, but I have been fighting with
> Xen PV qspinlocks last weekend:
>
> > + /*
> > +* Read HV_X64_MSR_GUEST_IDLE MSR can trigger the guest's
> > +* transition to the idle power state which can be exited
> > +*
From: Ludovic Barre
Recent versions of checkpatch have a new warning based on a documented
preference of Linus to not use bool in structures due to wasted space and
the size of bool is implementation dependent. For more information, see
the email thread at https://lkml.org/lkml/2017/11/21/384
f
From: Ludovic Barre
This patch adds validate_data callback at mmci_host_ops
to check specific constraints of variant.
Move mmci_validate_data function to regroup mmci_host_ops interfaces.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 39 +--
dri
From: Ludovic Barre
This patch adds dma_finalize callback at mmci_host_ops
to allow to call specific variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 19 ---
drivers/mmc/host/mmci.h | 3 ++-
drivers/mmc/host/mmci_qcom_dml.c | 1 +
3 files
From: Ludovic Barre
The goal of this serie is to add support of sdmmc for stm32.
Be to able to add this new variant it is needed to do some changes in
mmci core:
-Internalize specific needs of legacy dmaengine.
-Create and setup dma_priv pointer
-Create generic callbacks which share some features
From: Ludovic Barre
This patch adds dma_start callback to mmci_host_ops.
Create a generic mmci_dma_start function which regroup
common action between variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 69 +++-
drivers/mmc/host/mmci.
From: Ludovic Barre
This patch adds set_clkreg and set_pwrreg callbacks
at mmci_host_ops to allow to call specific variant.
extends visibility of mmci_write_clk/pwrreg functions
to be used into specific file variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 16 ---
From: Ludovic Barre
This patch adds dma_error callback at mmci_host_ops
to allow to call specific variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 25 +++--
drivers/mmc/host/mmci.h | 2 ++
drivers/mmc/host/mmci_qcom_dml.c | 1 +
3 file
From: Ludovic Barre
This patch merges the prepare data functions.
This allows to define a single access to prepare data service.
This prepares integration for mmci host ops.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 19 +++
1 file changed, 7 insertions(+), 12 d
From: Ludovic Barre
This patch adds prepare/unprepare callbacks to mmci_host_ops.
Like this mmci_pre/post_request can be generic, mmci_prepare_data
and mmci_unprepare_data provide common next_cookie management.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 101 +++
From: Ludovic Barre
-Introduces dma_priv pointer to define specific
needs for each dma engine. This patch is needed to prepare
sdmmc variant with internal dma which not use dmaengine API.
-Moves next cookie to mmci host structure to share same cookie
management between all variants.
Signed-off-b
From: Ludovic Barre
The STM32 sdmmc variant has a different clock divider.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 2 ++
drivers/mmc/host/mmci.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 0898cc9..0421e18 10
From: Ludovic Barre
This patch creates a generic mmci_dma_setup which calls
dma_setup callback of mmci_host_ops and manages common features
like use_dma... If there is a fallbacks to pio mode, dma
functions must check use_dma.
If one of dma channels is not defined (in dma engine config)
release
From: Ludovic Barre
This patch adds a boolean property to not read datacnt register.
Needed to support the STM32 sdmmc variant. MMCIDATACNT
register should be read only after the data transfer is completed.
When reading after an error event the read data count value may be
different from the real
From: Ludovic Barre
This patch adds a optional reset management.
Signed-off-by: Ludovic Barre
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mmc/mmci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt
b/Documentation/devicetree
From: Ludovic Barre
This patch adds a stm32 sdmmc variant, rev 1.1.
Introduces a new Manufacturer id "0x53, ascii 'S' to define
new stm32 sdmmc family with clean range of amba
revision/configurations bits (corresponding to sdmmc_ver
register with major/minor fields).
Add 2 variants properties:
-d
From: Ludovic Barre
This patch allows to define specific pio mask for variants.
Needed to support the STM32 sdmmc variant which has some bits
with different meaning (bits: 21,20,13,12,9)
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 13 +++--
drivers/mmc/host/mmci.h | 5 +
From: Ludovic Barre
This patch adds a optional reset management.
STM32 sdmmc variant needs to reset hardware block
during the power cycle procedure (for re-initialization).
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 7 +++
drivers/mmc/host/mmci.h | 2 ++
2 files changed, 9
From: Ludovic Barre
This patch adds a boolean property to allow to write datactrl
before to send command, whatever the command type (read or write).
Needed to support the STM32 sdmmc variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 6 --
drivers/mmc/host/mmci.h | 2 ++
2
From: Ludovic Barre
All variants don't pretend to have a startbiterr.
-While data error check, if status register return an error
(like MCI_DATACRCFAIL) we must avoid to check MCI_STARTBITERR
(if not desired).
-expand start_err to MCI_IRQENABLE to avoid to set this bit by default.
Signed-off-by
From: Ludovic Barre
This patch allows to define a datactrl block size
by variant, requested by STM32 sdmmc variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 13 +++--
drivers/mmc/host/mmci.h | 2 ++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/driv
From: Ludovic Barre
This patch adds datactrl variant property to define
dpsm enable bit. Needed to support the STM32 variant
(STM32 has no dpsm enable bit).
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 15 ---
drivers/mmc/host/mmci.h | 2 ++
2 files changed, 14 inser
From: Ludovic Barre
This patch adds properties for stm32 sdmmc variant.
Signed-off-by: Ludovic Barre
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mmc/mmci.txt | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt
b/Docum
From: Ludovic Barre
This patch adds command variant properties to define
cpsm enable bit and responses.
Needed to support the STM32 variant (shift of cpsm bit,
specific definition of commands response).
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 47 +
From: Ludovic Barre
This patch adds get_next_data callback to mmci_host_ops.
Generic mmci_get_next_data factorizes next_cookie check and
the host ops call.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 16 ++--
drivers/mmc/host/mmci.h | 2 ++
drivers
From: Ludovic Barre
This patch adds dma_release callback at mmci_host_ops
to allow to call specific variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 15 ---
drivers/mmc/host/mmci.h | 2 ++
drivers/mmc/host/mmci_qcom_dml.c | 1 +
3 files change
From: Ludovic Barre
This patch adds stm32 sdmmc specific registers.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.h | 56 +
1 file changed, 56 insertions(+)
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 1520289..5
Hi,
Can someone help me interpret this email? I was expecting this to be about a
dmesg change which is expected, but the content doesn't seem to indicate that.
For the record, the commit shouldn't really introduce any functional changes.
It merely avoids calling kcalloc with count==-EINVAL. I
find_lock_lowest_rq may or not releease rq lock, but it is fuzzy.
If not releasing rq lock, it is unnecessary to re-call
pick_next_pushable_task.
When CONFIG_PREEMPT=n, not releasing rq lock frequently happens
in a simple test case:
Four different rt priority tasks run on limited two cpus.
Signed-
Hi Thomas,
On Tue, Oct 02, 2018 at 12:44:36PM +0200, Thomas Gleixner wrote:
> On Tue, 2 Oct 2018, Feng Tang wrote:
> > On Tue, Oct 02, 2018 at 11:17:57AM +0200, Thomas Gleixner wrote:
> > > On Tue, 2 Oct 2018, Feng Tang wrote:
> > >
> > > > Hi Boris,
> > > >
> > > > On Mon, Oct 01, 2018 at 10:30
wt., 2 paź 2018 o 13:49 Srinivas Kandagatla
napisał(a):
>
>
>
> On 02/10/18 12:02, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski
> >
> > The following warning is produced when building nvmem core if
> > CONFIG_OF is disabled:
> >
> > drivers/nvmem/core.c:496:1: warning: 'nvmem_find_cel
On Sun, Sep 23, 2018 at 06:54:11AM -0700, Guenter Roeck wrote:
> The watchdog controller on NCT6796D, NCT6797D, and NCT6798D is compatible
> with the wtachdog controller on other Nuvoton chips.
>
> Signed-off-by: Guenter Roeck
Reviewed-by: Wim Van Sebroeck
> ---
> drivers/watchdog/w83627hf_w
Currently, no messages are printed when mounting a CIFS filesystem and
no debug configuration is enabled.
However, a CIFS mount information is valuable when troubleshooting
and/or forensic analyzing a system and finding out if was a CIFS
endpoint mount attempted.
Other filesystems such as XFS, EX
On Tue, Oct 02, 2018 at 02:29:49PM +0300, Tudor Ambarus wrote:
> at91sam9x5cm comes with a 2Gb NAND flash. Fix the rootfs size to
> match this limit.
>
> Signed-off-by: Tudor Ambarus
Acked-by: Ludovic Desroches
Thanks
> ---
> arch/arm/boot/dts/at91sam9x5cm.dtsi | 2 +-
> 1 file changed, 1 inse
On Tue, Oct 02, 2018 at 02:29:48PM +0300, Tudor Ambarus wrote:
> sama5d4_xplained comes with a 4Gb NAND flash. Increase the rootfs
> size to match this limit.
>
> Signed-off-by: Tudor Ambarus
Acked-by: Ludovic Desroches
Thanks
> ---
> arch/arm/boot/dts/at91-sama5d4_xplained.dts | 2 +-
> 1 fil
* Mel Gorman [2018-10-01 11:05:24]:
> Rate limiting of page migrations due to automatic NUMA balancing was
> introduced to mitigate the worst-case scenario of migrating at high
> frequency due to false sharing or slowly ping-ponging between nodes.
> Since then, a lot of effort was spent on correc
Fix a commit 8a8158c85e1e ("MIPS: memset.S: EVA & fault support for
small_memset") regression and remove assembly warnings:
arch/mips/lib/memset.S: Assembler messages:
arch/mips/lib/memset.S:243: Warning: Macro instruction expanded into multiple
instructions in a branch delay slot
triggering wi
On 02/10/18 12:02, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
The following warning is produced when building nvmem core if
CONFIG_OF is disabled:
drivers/nvmem/core.c:496:1: warning: 'nvmem_find_cell_by_index' defined but not
used [-Wunused-function]
nvmem_find_cell_by_index(s
Rewrite to use the `reorder' assembly mode and remove manually scheduled
delay slots except where GAS cannot schedule a delay-slot instruction
due to a data dependency or a section switch (as is the case with the EX
macro). No change in machine code produced.
Signed-off-by: Maciej W. Rozycki
Hi,
A recent change broke CPU_DADDI_WORKAROUNDS support in memset.S, due to a
delay-slot instruction expanding to multiple hardware operations for the
affected configurations.
The underlying cause is the excessive use of the `noreorder' assembly
mode, while it is only needed in couple of pla
RHEL / centos 6:
gcc-4.4.7
will check newer kernels too..
thanks
n.
On Tue, Oct 02, 2018 at 04:46:14AM -0700, Greg Kroah-Hartman wrote:
> On Tue, Oct 02, 2018 at 10:06:55AM +0200, Nikola Ciprich wrote:
> > Hi Greg and others,
> >
> > sorry for reporting this so late, but still...
> >
> > th
Hi Hoan,
On Wed, Sep 19, 2018 at 06:44:30PM +, Hoan Tran wrote:
> This patch adds CPU hotplug support where the PMU migrates the context to
> another online CPU when its CPU is offline.
>
> It fixes the below issue where the user does offline the CPU which is assigned
> to this PMU.
>
> Assu
On Tue, Oct 02, 2018 at 10:06:55AM +0200, Nikola Ciprich wrote:
> Hi Greg and others,
>
> sorry for reporting this so late, but still...
>
> this breaks build on older compilers, since it requires
> -mindirect-branch=thunk-inline -mindirect-branch-register even though
> retpoline support is disab
Hello,
On 02.10.2018 9:40, Thomas Gleixner wrote:
>
> Not only the user group, it really should do the full security checks which
> are done on open().
I expect it is already implemented by some internal kernel API so that
it could be reused.
>
>>b) then traditional checks against pe
On 02.10.2018 13:55, syzbot wrote:
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit: 62f3d25900c9 Add linux-next specific files for 20181002
> git tree: linux-next
> console output: https://syzkaller.appspot.com/x/log.txt?x=147d5eb940
&g
syzbot has found a reproducer for the following crash on:
HEAD commit:62f3d25900c9 Add linux-next specific files for 20181002
git tree: linux-next
console output: https://syzkaller.appspot.com/x/log.txt?x=16e2a94e40
kernel config: https://syzkaller.appspot.com/x/.config?x
Sorry for noticing this only now, but I have been fighting with
Xen PV qspinlocks last weekend:
On 02/10/2018 13:28, tip-bot for Yi Sun wrote:
> Commit-ID: aaa7fc34c003bd8133a49f7634480cef6288ad55
> Gitweb:
> https://git.kernel.org/tip/aaa7fc34c003bd8133a49f7634480cef6288ad55
> Author: Y
On Tue, 2 Oct 2018, Will Deacon wrote:
Subject prefix wants to be 'x86/pgtable:' please
> Now that the core code checks this for us, we don't need to do it in the
> backend.
According to Documentation changelogs want to be written in imperative
mood.
The core code has a check for pXd_none() a
sama5d4_xplained comes with a 4Gb NAND flash. Increase the rootfs
size to match this limit.
Signed-off-by: Tudor Ambarus
---
arch/arm/boot/dts/at91-sama5d4_xplained.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts
b/arch/arm/boo
at91sam9x5cm comes with a 2Gb NAND flash. Fix the rootfs size to
match this limit.
Signed-off-by: Tudor Ambarus
---
arch/arm/boot/dts/at91sam9x5cm.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi
b/arch/arm/boot/dts/at91sam9x5cm.dtsi
i
On Wed 26-09-18 08:06:24, Michal Hocko wrote:
> On Tue 25-09-18 15:04:06, Andrew Morton wrote:
> > On Tue, 25 Sep 2018 14:45:19 -0700 (PDT) David Rientjes
> > wrote:
> >
> > > > > It is also used in
> > > > > automated testing to ensure that vmas get disabled for thp
> > > > > appropriately
>
On Mon, Oct 01, 2018 at 04:16:48PM +0200, Torsten Duwe wrote:
> Check for compiler support of -fpatchable-function-entry and use it
> to intercept functions immediately on entry, saving the LR in x9.
> patchable-function-entry in GCC disables IPA-RA, which means ABI
> register calling conventions a
Commit-ID: 10d02e13385ce1e90abb49ef1e9a366a5d968157
Gitweb: https://git.kernel.org/tip/10d02e13385ce1e90abb49ef1e9a366a5d968157
Author: Yi Sun
AuthorDate: Thu, 27 Sep 2018 14:01:43 +0800
Committer: Thomas Gleixner
CommitDate: Tue, 2 Oct 2018 13:21:52 +0200
x86/hyperv: Add GUEST_IDLE_MS
Commit-ID: aaa7fc34c003bd8133a49f7634480cef6288ad55
Gitweb: https://git.kernel.org/tip/aaa7fc34c003bd8133a49f7634480cef6288ad55
Author: Yi Sun
AuthorDate: Thu, 27 Sep 2018 14:01:44 +0800
Committer: Thomas Gleixner
CommitDate: Tue, 2 Oct 2018 13:22:06 +0200
x86/hyperv: Enable PV qspinlo
On Fri, Sep 21, 2018 at 10:39:56PM +, Keith Busch wrote:
> Pinning pages from ZONE_DEVICE memory needs to check the backing device's
> live-ness, which is tracked in the device's dev_pagemap metadata. This
> metadata is stored in a radix tree and looking it up adds measurable
> software overhea
On Mon, Oct 01, 2018 at 04:49:32PM -0700, Saravana Kannan wrote:
> On 09/26/2018 07:48 AM, Sudeep Holla wrote:
> > On Wed, Sep 26, 2018 at 05:42:15PM +0300, Georgi Djakov wrote:
> > > Hi Rob,
> > >
> > > Thanks for the comments!
> > >
> > > On 09/25/2018 09:02 PM, Rob Herring wrote:
> > > > On Fr
On Tue, Oct 02, 2018 at 11:41:36AM +0100, John Garry wrote:
SNIP
> >
> >
> > ---
> > diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c
> > index 1ec1d9bc2d63..fb2a0dab3978 100644
> > --- a/tools/perf/util/header.c
> > +++ b/tools/perf/util/header.c
> > @@ -29,6 +29,7 @@
> > #inc
On Tue, 2 Oct 2018 at 09:57, Łukasz Stelmach wrote:
>
> Add binding documentation for the True Random Number Generator
> found on Samsung Exynos 5250+ SoCs.
>
> Signed-off-by: Łukasz Stelmach
> ---
> .../bindings/rng/samsung,exynos5250-trng.txt| 17 +
> 1 file changed, 17 ins
Certain devices don't work well when a transmit FIFO underrun or
receive FIFO overrun occurs. Example is the SAF400x radio chip when
running at high speed which leads to garbage being sent to/received from
the chip. In which case, it should stall waiting for further data to be
available before proc
Now that the core code checks this for us, we don't need to do it in the
backend.
Cc: Chintan Pandya
Cc: Toshi Kani
Cc: Thomas Gleixner
Cc: Michal Hocko
Cc: Andrew Morton
Reviewed-by: Toshi Kani
Signed-off-by: Will Deacon
---
arch/x86/mm/pgtable.c | 6 --
1 file changed, 6 deletions(-)
Hi all,
This is version two of the patches I previously posted here:
http://lkml.kernel.org/r/1536747974-25875-1-git-send-email-will.dea...@arm.com
Changes since v1 include:
* Fixed increment of the physical address around the mapping loops
* Added Reviewed-by tags from Toshi
All feedbac
On Fri, Sep 21, 2018 at 10:39:55PM +, Keith Busch wrote:
-ENOMSG
> Cc: Kirill Shutemov
> Cc: Dave Hansen
> Cc: Dan Williams
> Signed-off-by: Keith Busch
> ---
> tools/testing/selftests/vm/gup_benchmark.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/tools/
Whilst no architectures actually enable support for huge p4d mappings
in the vmap area, the code that is implemented should be using
break-before-make, as we do for pud and pmd huge entries.
Cc: Chintan Pandya
Cc: Toshi Kani
Cc: Thomas Gleixner
Cc: Michal Hocko
Cc: Andrew Morton
Reviewed-by:
The recently merged API for ensuring break-before-make on page-table
entries when installing huge mappings in the vmalloc/ioremap region is
fairly counter-intuitive, resulting in the arch freeing functions
(e.g. pmd_free_pte_page()) being called even on entries that aren't
present. This resulted in
The current ioremap() code uses a phys_addr variable at each level of
page table, which is confusingly offset by subtracting the base virtual
address being mapped so that adding the current virtual address back on
when iterating through the page table entries gives back the corresponding
physical a
Now that the core code checks this for us, we don't need to do it in the
backend.
Cc: Chintan Pandya
Cc: Toshi Kani
Cc: Thomas Gleixner
Cc: Michal Hocko
Cc: Andrew Morton
Signed-off-by: Will Deacon
---
arch/arm64/mm/mmu.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff -
On 2018-10-01 2:40 PM, Maciej Slodczyk wrote:
Hi Robin,
Thank you for having a look at my patchset.
On 27.09.2018 19:01, Robin Murphy wrote:
On 26/09/18 13:12, Maciej Slodczyk wrote:
[...]
@@ -38,16 +78,44 @@ int arch_uprobe_analyze_insn(struct arch_uprobe
*auprobe, struct mm_struct *mm,
On Fri, Sep 21, 2018 at 10:39:54PM +, Keith Busch wrote:
> The gup benchmark by default maps anonymous memory. This patch allows a
> user to specify a file to map, providing a means to test various
> file backings, like device and filesystem DAX.
>
> Cc: Kirill Shutemov
> Cc: Dave Hansen
> C
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