On Wed, Oct 03, 2018 at 10:24:09PM +, Winkler, Tomas wrote:
>
>
> > -Original Message-
> > From: Jarkko Sakkinen [mailto:jarkko.sakki...@linux.intel.com]
> > Sent: Wednesday, October 03, 2018 15:02
> > To: Winkler, Tomas
> > Cc: Jason Gunthorpe ; Nayna Jain
> > ; Usyskin, Alexander
On Wed, Oct 03, 2018 at 10:24:09PM +, Winkler, Tomas wrote:
>
>
> > -Original Message-
> > From: Jarkko Sakkinen [mailto:jarkko.sakki...@linux.intel.com]
> > Sent: Wednesday, October 03, 2018 15:02
> > To: Winkler, Tomas
> > Cc: Jason Gunthorpe ; Nayna Jain
> > ; Usyskin, Alexander
On Thu, Oct 4, 2018 at 12:50 PM Mark Brown wrote:
> On Thu, Oct 04, 2018 at 11:06:54AM +0200, Linus Walleij wrote:
>
> > Optional properties:
> > -- gpio: gpio to use for enable control
> > +- gpios: gpio to use for enable control
>
> Are we supposed to be able to have just plain gpios as a
On Thu, Oct 4, 2018 at 12:50 PM Mark Brown wrote:
> On Thu, Oct 04, 2018 at 11:06:54AM +0200, Linus Walleij wrote:
>
> > Optional properties:
> > -- gpio: gpio to use for enable control
> > +- gpios: gpio to use for enable control
>
> Are we supposed to be able to have just plain gpios as a
From: AD-Aleksandrov
Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT
module, DDR3 RAM and eMMC.
- add neutis n5 dtsi file for SoM needs
- add neutis devboard dts file
- add neutis devboard target to dtb makefile
- new vendor prefix - emlid
Signed-off-by: Aleksandr Aleksandrov
From: AD-Aleksandrov
Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT
module, DDR3 RAM and eMMC.
- add neutis n5 dtsi file for SoM needs
- add neutis devboard dts file
- add neutis devboard target to dtb makefile
- new vendor prefix - emlid
Signed-off-by: Aleksandr Aleksandrov
On Thu, 4 Oct 2018 16:42:22 +0530
Vignesh R wrote:
> On Thursday 04 October 2018 03:15 PM, Boris Brezillon wrote:
> > On Wed, 3 Oct 2018 22:26:01 +0530
> > Vignesh R wrote:
> >
> >> Micron's mt35xu512aba flash is an Octal flash that has x8 IO lines. It
> >> supports read/write over 8 IO
On Thu, 4 Oct 2018 16:42:22 +0530
Vignesh R wrote:
> On Thursday 04 October 2018 03:15 PM, Boris Brezillon wrote:
> > On Wed, 3 Oct 2018 22:26:01 +0530
> > Vignesh R wrote:
> >
> >> Micron's mt35xu512aba flash is an Octal flash that has x8 IO lines. It
> >> supports read/write over 8 IO
On Thu, 4 Oct 2018 16:05:36 +0530
Vignesh R wrote:
> >>
> >> .../devicetree/bindings/mtd/cadence-quadspi.txt | 1 +
> >> drivers/mtd/spi-nor/cadence-quadspi.c | 9 +
> >
> > On a slightly different topic, do you plan to convert the Cadence
> > driver to
On Thu, 4 Oct 2018 16:05:36 +0530
Vignesh R wrote:
> >>
> >> .../devicetree/bindings/mtd/cadence-quadspi.txt | 1 +
> >> drivers/mtd/spi-nor/cadence-quadspi.c | 9 +
> >
> > On a slightly different topic, do you plan to convert the Cadence
> > driver to
Enable the MMC phy implemented in the AM65xx SOC.
This phy is required for the sdhci host controller
driving the MMC ports.
Signed-off-by: Faiz Abbas
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
On Thu, Oct 04, 2018 at 01:00:42PM +0200, Paul Menzel wrote:
> While here you write, it did not.
Read again what I said:
> and I did try marking the ISA range RO in mark_rodata_ro() but the
> machine wouldn't boot after.
and the code I pasted has this:
// init_memory_mapping(0,
Add driver support for the MMC physical layer present
on TI's AM654 devices.
Signed-off-by: Faiz Abbas
Signed-off-by: Sekhar Nori
---
drivers/phy/ti/Kconfig | 7 +
drivers/phy/ti/Makefile| 1 +
drivers/phy/ti/phy-am654-mmc.c | 291 +
3 files
Enable the MMC phy implemented in the AM65xx SOC.
This phy is required for the sdhci host controller
driving the MMC ports.
Signed-off-by: Faiz Abbas
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
On Thu, Oct 04, 2018 at 01:00:42PM +0200, Paul Menzel wrote:
> While here you write, it did not.
Read again what I said:
> and I did try marking the ISA range RO in mark_rodata_ro() but the
> machine wouldn't boot after.
and the code I pasted has this:
// init_memory_mapping(0,
Add driver support for the MMC physical layer present
on TI's AM654 devices.
Signed-off-by: Faiz Abbas
Signed-off-by: Sekhar Nori
---
drivers/phy/ti/Kconfig | 7 +
drivers/phy/ti/Makefile| 1 +
drivers/phy/ti/phy-am654-mmc.c | 291 +
3 files
Add a new compatible to use the host controller driver with the
MMC PHY on TI's AM654 SOCs
Signed-off-by: Faiz Abbas
Signed-off-by: Sekhar Nori
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Add a new compatible to use the host controller driver with the
MMC PHY on TI's AM654 SOCs
Signed-off-by: Faiz Abbas
Signed-off-by: Sekhar Nori
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Currently, the driver passes platform data as a global structure
and uses the .data of of_device_id to pass the soc_ctl_map. To
make the implementation more flexible add a single data structure
that incorporates both of the above and pass it in the .data of
of_device_id.
Signed-off-by: Faiz Abbas
Add information to document bindings for the MMC PHY
on TI's AM654 devices.
Signed-off-by: Faiz Abbas
Signed-off-by: Sekhar Nori
---
.../devicetree/bindings/phy/am654-mmc-phy.txt | 42 +++
1 file changed, 42 insertions(+)
create mode 100644
The current arasan sdhci PHY configuration isn't compatible
with the PHY on TI's AM654 devices.
Therefore, add a new compatible, AM654 specific quirks
and a new AM654 specific set_clock function which
configures the PHY in a sane way.
Signed-off-by: Faiz Abbas
Signed-off-by: Sekhar Nori
---
Currently, the driver passes platform data as a global structure
and uses the .data of of_device_id to pass the soc_ctl_map. To
make the implementation more flexible add a single data structure
that incorporates both of the above and pass it in the .data of
of_device_id.
Signed-off-by: Faiz Abbas
Add information to document bindings for the MMC PHY
on TI's AM654 devices.
Signed-off-by: Faiz Abbas
Signed-off-by: Sekhar Nori
---
.../devicetree/bindings/phy/am654-mmc-phy.txt | 42 +++
1 file changed, 42 insertions(+)
create mode 100644
The current arasan sdhci PHY configuration isn't compatible
with the PHY on TI's AM654 devices.
Therefore, add a new compatible, AM654 specific quirks
and a new AM654 specific set_clock function which
configures the PHY in a sane way.
Signed-off-by: Faiz Abbas
Signed-off-by: Sekhar Nori
---
The following patches add driver support for MMC/SD in TI's
AM65x SOCs. There are two controller instances. Both are compatible
with eMMC5.1 Host Controller Standard Specification and SD Host
Controller Standard Specification 4.10.
DT Support patches will be posted separately.
Faiz Abbas (6):
The following patches add driver support for MMC/SD in TI's
AM65x SOCs. There are two controller instances. Both are compatible
with eMMC5.1 Host Controller Standard Specification and SD Host
Controller Standard Specification 4.10.
DT Support patches will be posted separately.
Faiz Abbas (6):
On Thu, Sep 20, 2018 at 05:02:53PM +0200, Jean-Jacques Hiblot wrote:
> This makes it easier to use pcitest in automated setups.
>
> Signed-off-by: Jean-Jacques Hiblot
> ---
> tools/pci/pcitest.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/tools/pci/pcitest.c
On Thursday 04 October 2018 03:15 PM, Boris Brezillon wrote:
> On Wed, 3 Oct 2018 22:26:01 +0530
> Vignesh R wrote:
>
>> Micron's mt35xu512aba flash is an Octal flash that has x8 IO lines. It
>> supports read/write over 8 IO lines simulatenously. Add support for
>> Octal read mode for Micron
On Thu, Sep 20, 2018 at 05:02:53PM +0200, Jean-Jacques Hiblot wrote:
> This makes it easier to use pcitest in automated setups.
>
> Signed-off-by: Jean-Jacques Hiblot
> ---
> tools/pci/pcitest.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/tools/pci/pcitest.c
On Thursday 04 October 2018 03:15 PM, Boris Brezillon wrote:
> On Wed, 3 Oct 2018 22:26:01 +0530
> Vignesh R wrote:
>
>> Micron's mt35xu512aba flash is an Octal flash that has x8 IO lines. It
>> supports read/write over 8 IO lines simulatenously. Add support for
>> Octal read mode for Micron
Dear Borislav,
On 10/04/18 12:54, Borislav Petkov wrote:
> On Thu, Oct 04, 2018 at 10:59:18AM +0200, Paul Menzel wrote:
>> I meant just the test you did.
>
> https://lkml.kernel.org/r/20181003212255.gb28...@zn.tnic
I see. But there you write, the machine does boot.
While here you write, it
On Thu, Oct 04, 2018 at 12:49:38PM +0200, Daniel Vetter wrote:
> On Thu, Oct 04, 2018 at 01:34:22PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 03, 2018 at 07:45:38PM +0300, Eugeniy Paltsev wrote:
> > > drm fbdev emulation doesn't support changing the pixel format at all,
> > > so reject all pixel
Dear Borislav,
On 10/04/18 12:54, Borislav Petkov wrote:
> On Thu, Oct 04, 2018 at 10:59:18AM +0200, Paul Menzel wrote:
>> I meant just the test you did.
>
> https://lkml.kernel.org/r/20181003212255.gb28...@zn.tnic
I see. But there you write, the machine does boot.
While here you write, it
On Thu, Oct 04, 2018 at 12:49:38PM +0200, Daniel Vetter wrote:
> On Thu, Oct 04, 2018 at 01:34:22PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 03, 2018 at 07:45:38PM +0300, Eugeniy Paltsev wrote:
> > > drm fbdev emulation doesn't support changing the pixel format at all,
> > > so reject all pixel
On Wed, Sep 12, 2018 at 10:13:08AM +0100, Quentin Perret wrote:
> Energy Aware Scheduling (EAS) is designed with the assumption that
> frequencies of CPUs follow their utilization value. When using a CPUFreq
> governor other than schedutil, the chances of this assumption being true
> are small, if
On Wed, Sep 12, 2018 at 10:13:08AM +0100, Quentin Perret wrote:
> Energy Aware Scheduling (EAS) is designed with the assumption that
> frequencies of CPUs follow their utilization value. When using a CPUFreq
> governor other than schedutil, the chances of this assumption being true
> are small, if
On Thursday 04 Oct 2018 at 12:41:07 (+0200), Peter Zijlstra wrote:
> Not sure, see what it looks like ;-) My main concern here was to get rid
> of that giant blob in select_task_rq_fair().
OK, got it. I'll probably just move the checks into the function and
merge that large comment into the
On Thursday 04 Oct 2018 at 12:41:07 (+0200), Peter Zijlstra wrote:
> Not sure, see what it looks like ;-) My main concern here was to get rid
> of that giant blob in select_task_rq_fair().
OK, got it. I'll probably just move the checks into the function and
merge that large comment into the
On Thu, Oct 04, 2018 at 10:59:18AM +0200, Paul Menzel wrote:
> I meant just the test you did.
https://lkml.kernel.org/r/20181003212255.gb28...@zn.tnic
> The SSD is also used in the Lenovo X60 and T60, which are
> 32-bit systems.
And what exactly is the problem when you access it on a 64-bit OS?
On Thu, Oct 04, 2018 at 10:59:18AM +0200, Paul Menzel wrote:
> I meant just the test you did.
https://lkml.kernel.org/r/20181003212255.gb28...@zn.tnic
> The SSD is also used in the Lenovo X60 and T60, which are
> 32-bit systems.
And what exactly is the problem when you access it on a 64-bit OS?
On Thu, Oct 04, 2018 at 11:06:54AM +0200, Linus Walleij wrote:
> Optional properties:
> -- gpio: gpio to use for enable control
> +- gpios: gpio to use for enable control
Are we supposed to be able to have just plain gpios as a standards
conforming property or would best practice be to call it
On Thu, Oct 04, 2018 at 11:06:54AM +0200, Linus Walleij wrote:
> Optional properties:
> -- gpio: gpio to use for enable control
> +- gpios: gpio to use for enable control
Are we supposed to be able to have just plain gpios as a standards
conforming property or would best practice be to call it
On Thu, Oct 04, 2018 at 11:27:22AM +0100, Quentin Perret wrote:
> > > + for_each_cpu_and(cpu, perf_domain_span(pd),
> > > sched_domain_span(sd)) {
> >
> > Which of the two masks do we expect to be the smallest?
>
> Typically, perf_domain_span is smaller.
OK, then the above expression
On Thu, Oct 04, 2018 at 11:27:22AM +0100, Quentin Perret wrote:
> > > + for_each_cpu_and(cpu, perf_domain_span(pd),
> > > sched_domain_span(sd)) {
> >
> > Which of the two masks do we expect to be the smallest?
>
> Typically, perf_domain_span is smaller.
OK, then the above expression
Hi,
On Thursday 04 October 2018 12:21 PM, Yogesh Narayan Gaur wrote:
> Hi Vignesh,
>
>> -Original Message-
>> From: Vignesh R [mailto:vigne...@ti.com]
>> Sent: Wednesday, October 3, 2018 10:26 PM
>> To: Boris Brezillon ; Marek Vasut
>> ; Rob Herring
>> Cc: Brian Norris ; Yogesh Narayan
Hi,
On Thursday 04 October 2018 12:21 PM, Yogesh Narayan Gaur wrote:
> Hi Vignesh,
>
>> -Original Message-
>> From: Vignesh R [mailto:vigne...@ti.com]
>> Sent: Wednesday, October 3, 2018 10:26 PM
>> To: Boris Brezillon ; Marek Vasut
>> ; Rob Herring
>> Cc: Brian Norris ; Yogesh Narayan
On Wed, Oct 03, 2018 at 02:48:04PM +0300, Andy Shevchenko wrote:
> On Tue, Oct 02, 2018 at 11:21:42AM +0300, Andy Shevchenko wrote:
>
> > I would rather go with two prototypes to get()/set() a clump in the bitmap
> > in a way when it's aligned and BITS_PER_LONG % clump_size == 0.
>
> To make
On Wed, Oct 03, 2018 at 02:48:04PM +0300, Andy Shevchenko wrote:
> On Tue, Oct 02, 2018 at 11:21:42AM +0300, Andy Shevchenko wrote:
>
> > I would rather go with two prototypes to get()/set() a clump in the bitmap
> > in a way when it's aligned and BITS_PER_LONG % clump_size == 0.
>
> To make
On Thursday 04 October 2018 12:50 AM, Boris Brezillon wrote:
> On Wed, 3 Oct 2018 22:26:00 +0530
> Vignesh R wrote:
>
>> This series adds support for octal mode of mt35x flash. Also, adds
>> support for OSPI version of Cadence QSPI controller.
>>
>> Based on top of patches adding basic support
On Thursday 04 October 2018 12:50 AM, Boris Brezillon wrote:
> On Wed, 3 Oct 2018 22:26:00 +0530
> Vignesh R wrote:
>
>> This series adds support for octal mode of mt35x flash. Also, adds
>> support for OSPI version of Cadence QSPI controller.
>>
>> Based on top of patches adding basic support
On Wed, Oct 03, 2018 at 07:39:26PM -0700, Nathan Chancellor wrote:
> Clang warns when one enumerated type is implicitly converted to another.
>
> drivers/spi/spi-ep93xx.c:342:62: warning: implicit conversion from
> enumeration type 'enum dma_transfer_direction' to different enumeration
Please
On Wed, Oct 03, 2018 at 07:39:26PM -0700, Nathan Chancellor wrote:
> Clang warns when one enumerated type is implicitly converted to another.
>
> drivers/spi/spi-ep93xx.c:342:62: warning: implicit conversion from
> enumeration type 'enum dma_transfer_direction' to different enumeration
Please
On Tue, Oct 02, 2018 at 11:21:42AM +0300, Andy Shevchenko wrote:
> On Tue, Oct 02, 2018 at 09:42:48AM +0200, Rasmus Villemoes wrote:
> > On 2018-10-02 03:13, William Breathitt Gray wrote:
>
> > The cover letter says
> >
> > The clump_size argument can be an arbitrary number of bits and is not
On Tue, Oct 02, 2018 at 11:21:42AM +0300, Andy Shevchenko wrote:
> On Tue, Oct 02, 2018 at 09:42:48AM +0200, Rasmus Villemoes wrote:
> > On 2018-10-02 03:13, William Breathitt Gray wrote:
>
> > The cover letter says
> >
> > The clump_size argument can be an arbitrary number of bits and is not
On 02/10/2018 02:08:37+0100, Maciej W. Rozycki wrote:
> Hi,
>
> This mini patch series fixes issues introduced recently for non-ACPI
> platforms using `rtc-cmos'. Please see individual change descriptions for
> details.
>
> These have been run-time verified with the DECstation
On 02/10/2018 02:08:37+0100, Maciej W. Rozycki wrote:
> Hi,
>
> This mini patch series fixes issues introduced recently for non-ACPI
> platforms using `rtc-cmos'. Please see individual change descriptions for
> details.
>
> These have been run-time verified with the DECstation
On Thursday 04 Oct 2018 at 11:44:12 (+0200), Peter Zijlstra wrote:
> On Wed, Sep 12, 2018 at 10:13:07AM +0100, Quentin Perret wrote:
> > + while (pd) {
> > + unsigned long cur_energy, spare_cap, max_spare_cap = 0;
> > + int max_spare_cap_cpu = -1;
> > +
> > +
On Mon 17-09-18 04:19:02, syzbot wrote:
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit:2e2a0c961a87 Merge branch 'progarray_mapinmap_dump'
> git tree: bpf-next
> console output: https://syzkaller.appspot.com/x/log.txt?x=1762281140
> kernel config:
On Mon 17-09-18 04:19:02, syzbot wrote:
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit:2e2a0c961a87 Merge branch 'progarray_mapinmap_dump'
> git tree: bpf-next
> console output: https://syzkaller.appspot.com/x/log.txt?x=1762281140
> kernel config:
On Thursday 04 Oct 2018 at 11:44:12 (+0200), Peter Zijlstra wrote:
> On Wed, Sep 12, 2018 at 10:13:07AM +0100, Quentin Perret wrote:
> > + while (pd) {
> > + unsigned long cur_energy, spare_cap, max_spare_cap = 0;
> > + int max_spare_cap_cpu = -1;
> > +
> > +
at 2:45 AM, Ingo Molnar wrote:
>
> * Nadav Amit wrote:
>
>>> Another, separate question I wanted to ask: how do we ensure that the
>>> kernel stays fixed?
>>> I.e. is there some tooling we can use to actually measure whether there's
>>> bad inlining decisions
>>> done, to detect all these
at 2:45 AM, Ingo Molnar wrote:
>
> * Nadav Amit wrote:
>
>>> Another, separate question I wanted to ask: how do we ensure that the
>>> kernel stays fixed?
>>> I.e. is there some tooling we can use to actually measure whether there's
>>> bad inlining decisions
>>> done, to detect all these
On Wed, Oct 03, 2018 at 06:08:09PM +, Leonard Crestez wrote:
> On Wed, 2018-10-03 at 13:10 +0100, Mark Brown wrote:
> > No, that's definitely not desired. We don't want to change the state of
> > the regulator at all if we can avoid it unless the user explicitly asked
> > for it.
> That
On Wed, Oct 03, 2018 at 06:08:09PM +, Leonard Crestez wrote:
> On Wed, 2018-10-03 at 13:10 +0100, Mark Brown wrote:
> > No, that's definitely not desired. We don't want to change the state of
> > the regulator at all if we can avoid it unless the user explicitly asked
> > for it.
> That
* Waiman Long wrote:
> diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
> index b0d0b51c4d85..1fd82ff99c65 100644
> --- a/include/linux/lockdep.h
> +++ b/include/linux/lockdep.h
> @@ -99,13 +99,8 @@ struct lock_class {
>*/
> unsigned intversion;
* Waiman Long wrote:
> diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
> index b0d0b51c4d85..1fd82ff99c65 100644
> --- a/include/linux/lockdep.h
> +++ b/include/linux/lockdep.h
> @@ -99,13 +99,8 @@ struct lock_class {
>*/
> unsigned intversion;
On 4 October 2018 at 11:32, Rafael J. Wysocki wrote:
> On Thu, Oct 4, 2018 at 11:04 AM Rafael J. Wysocki wrote:
>>
>> On Thursday, October 4, 2018 10:58:53 AM CEST Ulf Hansson wrote:
>> > On 4 October 2018 at 10:39, Rafael J. Wysocki wrote:
>> > > On Wed, Oct 3, 2018 at 4:39 PM Ulf Hansson
>>
On 4 October 2018 at 11:32, Rafael J. Wysocki wrote:
> On Thu, Oct 4, 2018 at 11:04 AM Rafael J. Wysocki wrote:
>>
>> On Thursday, October 4, 2018 10:58:53 AM CEST Ulf Hansson wrote:
>> > On 4 October 2018 at 10:39, Rafael J. Wysocki wrote:
>> > > On Wed, Oct 3, 2018 at 4:39 PM Ulf Hansson
>>
This struct does not seem to be used anywhere on the code
Signed-off-by: Ricardo Ribalda Delgado
---
drivers/mtd/maps/physmap_of_gemini.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/mtd/maps/physmap_of_gemini.c
b/drivers/mtd/maps/physmap_of_gemini.c
index
This struct does not seem to be used anywhere on the code
Signed-off-by: Ricardo Ribalda Delgado
---
drivers/mtd/maps/physmap_of_gemini.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/mtd/maps/physmap_of_gemini.c
b/drivers/mtd/maps/physmap_of_gemini.c
index
Commit-ID: 9c2298aad355d8c1957df3015448fef333526934
Gitweb: https://git.kernel.org/tip/9c2298aad355d8c1957df3015448fef333526934
Author: Rafael J. Wysocki
AuthorDate: Thu, 4 Oct 2018 11:05:14 +0200
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 11:25:56 +0200
sched/core: Fix
Commit-ID: 494b5168f2de009eb80f198f668da374295098dd
Gitweb: https://git.kernel.org/tip/494b5168f2de009eb80f198f668da374295098dd
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:57 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 11:25:00 +0200
x86/paravirt: Work around GCC
Commit-ID: 494b5168f2de009eb80f198f668da374295098dd
Gitweb: https://git.kernel.org/tip/494b5168f2de009eb80f198f668da374295098dd
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:57 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 11:25:00 +0200
x86/paravirt: Work around GCC
Commit-ID: 9c2298aad355d8c1957df3015448fef333526934
Gitweb: https://git.kernel.org/tip/9c2298aad355d8c1957df3015448fef333526934
Author: Rafael J. Wysocki
AuthorDate: Thu, 4 Oct 2018 11:05:14 +0200
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 11:25:56 +0200
sched/core: Fix
Commit-ID: f81f8ad56fd1c7b99b2ed1c314527f7d9ac447c6
Gitweb: https://git.kernel.org/tip/f81f8ad56fd1c7b99b2ed1c314527f7d9ac447c6
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:56 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 11:25:00 +0200
x86/bug: Macrofy the BUG
Commit-ID: f81f8ad56fd1c7b99b2ed1c314527f7d9ac447c6
Gitweb: https://git.kernel.org/tip/f81f8ad56fd1c7b99b2ed1c314527f7d9ac447c6
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:56 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 11:25:00 +0200
x86/bug: Macrofy the BUG
Commit-ID: 77f48ec28e4ccff94d2e5f4260a83ac27a7f3099
Gitweb: https://git.kernel.org/tip/77f48ec28e4ccff94d2e5f4260a83ac27a7f3099
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:55 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 11:24:59 +0200
x86/alternatives: Macrofy
Commit-ID: 77f48ec28e4ccff94d2e5f4260a83ac27a7f3099
Gitweb: https://git.kernel.org/tip/77f48ec28e4ccff94d2e5f4260a83ac27a7f3099
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:55 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 11:24:59 +0200
x86/alternatives: Macrofy
On Tue, Oct 02, 2018 at 09:42:48AM +0200, Rasmus Villemoes wrote:
> On 2018-10-02 03:13, William Breathitt Gray wrote:
> > This macro iterates for each group of bits (clump) with set bits, within
> > a bitmap memory region. For each iteration, "clump" is set to the found
> > clump index, "index"
On Tue, Oct 02, 2018 at 09:42:48AM +0200, Rasmus Villemoes wrote:
> On 2018-10-02 03:13, William Breathitt Gray wrote:
> > This macro iterates for each group of bits (clump) with set bits, within
> > a bitmap memory region. For each iteration, "clump" is set to the found
> > clump index, "index"
Commit-ID: 77b0bf55bc675233d22cd5df97605d516d64525e
Gitweb: https://git.kernel.org/tip/77b0bf55bc675233d22cd5df97605d516d64525e
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:52 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 10:57:09 +0200
kbuild/Makefile: Prepare for
Commit-ID: 77b0bf55bc675233d22cd5df97605d516d64525e
Gitweb: https://git.kernel.org/tip/77b0bf55bc675233d22cd5df97605d516d64525e
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:52 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 10:57:09 +0200
kbuild/Makefile: Prepare for
Commit-ID: 9e1725b410594911cc5981b6c7b4cea4ec054ca8
Gitweb: https://git.kernel.org/tip/9e1725b410594911cc5981b6c7b4cea4ec054ca8
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:54 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 11:24:59 +0200
x86/refcount: Work around GCC
Commit-ID: 9e1725b410594911cc5981b6c7b4cea4ec054ca8
Gitweb: https://git.kernel.org/tip/9e1725b410594911cc5981b6c7b4cea4ec054ca8
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:54 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 11:24:59 +0200
x86/refcount: Work around GCC
Commit-ID: c06c4d8090513f2974dfdbed2ac98634357ac475
Gitweb: https://git.kernel.org/tip/c06c4d8090513f2974dfdbed2ac98634357ac475
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:53 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 11:24:58 +0200
x86/objtool: Use asm macros
Commit-ID: c06c4d8090513f2974dfdbed2ac98634357ac475
Gitweb: https://git.kernel.org/tip/c06c4d8090513f2974dfdbed2ac98634357ac475
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:53 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 11:24:58 +0200
x86/objtool: Use asm macros
Commit-ID: 35e76b99ddf20405a6196bb7c9eb152675c93106
Gitweb: https://git.kernel.org/tip/35e76b99ddf20405a6196bb7c9eb152675c93106
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:51 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 10:05:38 +0200
kbuild/arch/xtensa: Define
Commit-ID: 35e76b99ddf20405a6196bb7c9eb152675c93106
Gitweb: https://git.kernel.org/tip/35e76b99ddf20405a6196bb7c9eb152675c93106
Author: Nadav Amit
AuthorDate: Wed, 3 Oct 2018 14:30:51 -0700
Committer: Ingo Molnar
CommitDate: Thu, 4 Oct 2018 10:05:38 +0200
kbuild/arch/xtensa: Define
On Wednesday 03 Oct 2018 at 18:24:35 (+0200), Peter Zijlstra wrote:
> Yeah, sysctl, see for example: sysctl.kernel.numa_balancing and the
> sched_numa_balancing static_key that goes with it.
OK, that works for me.
> I would default enable EAS if the EM is there and valid, but allow
> people to
On 3 October 2018 at 19:34, Bryan Gurney wrote:
> On Wed, Oct 3, 2018 at 11:53 AM, Paolo Valente
> wrote:
>>
>>
>>> Il giorno 03 ott 2018, alle ore 10:28, Linus Walleij
>>> ha scritto:
>>>
>>> On Wed, Oct 3, 2018 at 9:42 AM Damien Le Moal wrote:
>>>
There is another class of outliers:
On Wednesday 03 Oct 2018 at 18:24:35 (+0200), Peter Zijlstra wrote:
> Yeah, sysctl, see for example: sysctl.kernel.numa_balancing and the
> sched_numa_balancing static_key that goes with it.
OK, that works for me.
> I would default enable EAS if the EM is there and valid, but allow
> people to
On 3 October 2018 at 19:34, Bryan Gurney wrote:
> On Wed, Oct 3, 2018 at 11:53 AM, Paolo Valente
> wrote:
>>
>>
>>> Il giorno 03 ott 2018, alle ore 10:28, Linus Walleij
>>> ha scritto:
>>>
>>> On Wed, Oct 3, 2018 at 9:42 AM Damien Le Moal wrote:
>>>
There is another class of outliers:
On Wed, 2018-09-26 at 15:20 +0200, Geert Uytterhoeven wrote:
> Signed-off-by: Geert Uytterhoeven
> ---
> include/linux/reset.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/linux/reset.h b/include/linux/reset.h
> index 09732c36f3515a1e..29af6d6b2f4b8103 100644
Hi Lukas,
Lukas Braun writes:
> Userspace can create a memslot with memory backed by (transparent)
> hugepages, but with bounds that do not align with hugepages.
> In that case, we cannot map the entire region in the guest as hugepages
> without exposing additional host memory to the guest and
Hi Dinh,
On Mon, 2018-09-17 at 09:50 -0500, Dinh Nguyen wrote:
> Create a separate reset driver that uses the reset operations in reset-simple.
> The reset driver for the SoCFPGA platform needs to register early in order to
> be able bring online timers that needed early in the kernel bootup.
>
On Wed, 2018-09-26 at 15:20 +0200, Geert Uytterhoeven wrote:
> Signed-off-by: Geert Uytterhoeven
> ---
> include/linux/reset.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/linux/reset.h b/include/linux/reset.h
> index 09732c36f3515a1e..29af6d6b2f4b8103 100644
Hi Lukas,
Lukas Braun writes:
> Userspace can create a memslot with memory backed by (transparent)
> hugepages, but with bounds that do not align with hugepages.
> In that case, we cannot map the entire region in the guest as hugepages
> without exposing additional host memory to the guest and
Hi Dinh,
On Mon, 2018-09-17 at 09:50 -0500, Dinh Nguyen wrote:
> Create a separate reset driver that uses the reset operations in reset-simple.
> The reset driver for the SoCFPGA platform needs to register early in order to
> be able bring online timers that needed early in the kernel bootup.
>
On 02/10/2018 17:00, Oscar Salvador wrote:
> From: Oscar Salvador
>
> This patch is only a preparation for the following-up patches.
> The idea of passing the nid is that will allow us to get rid
> of the zone parameter in the patches that follow
>
> Signed-off-by: Oscar Salvador
> ---
>
On 02/10/2018 17:00, Oscar Salvador wrote:
> From: Oscar Salvador
>
> This patch is only a preparation for the following-up patches.
> The idea of passing the nid is that will allow us to get rid
> of the zone parameter in the patches that follow
>
> Signed-off-by: Oscar Salvador
> ---
>
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