Initialize the Intel PT configuration when cpuid update.
Include cpuid inforamtion, rtit_ctl bit mask and the number of
address ranges.
Signed-off-by: Luwei Kang
---
arch/x86/kvm/vmx.c | 73 ++
1 file changed, 73 insertions(+)
diff --git
From: Chao Peng
To save performance overhead, disable intercept Intel PT MSRs
read/write when Intel PT is enabled in guest.
MSR_IA32_RTIT_CTL is an exception that will always be intercepted.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
arch/x86/kvm/vmx.c | 23
From: Chao Peng
This patch implement Intel Processor Trace MSRs read/write
emulation.
Intel PT MSRs read/write need to be emulated when Intel PT
MSRs is intercepted in guest and during live migration.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
arch/x86/include/asm/intel_pt.h |
From: Chao Peng
Expose Intel Processor Trace to guest only when
the PT works in Host-Guest mode.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/cpuid.c| 22 --
arch/x86/kvm/svm.c | 6
Initialize the Intel PT configuration when cpuid update.
Include cpuid inforamtion, rtit_ctl bit mask and the number of
address ranges.
Signed-off-by: Luwei Kang
---
arch/x86/kvm/vmx.c | 73 ++
1 file changed, 73 insertions(+)
diff --git
From: Chao Peng
To save performance overhead, disable intercept Intel PT MSRs
read/write when Intel PT is enabled in guest.
MSR_IA32_RTIT_CTL is an exception that will always be intercepted.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
arch/x86/kvm/vmx.c | 23
From: Chao Peng
This patch implement Intel Processor Trace MSRs read/write
emulation.
Intel PT MSRs read/write need to be emulated when Intel PT
MSRs is intercepted in guest and during live migration.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
arch/x86/include/asm/intel_pt.h |
From: Chao Peng
Expose Intel Processor Trace to guest only when
the PT works in Host-Guest mode.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/cpuid.c| 22 --
arch/x86/kvm/svm.c | 6
From: Chao Peng
Intel Processor Trace virtualization can be work in one
of 2 possible modes:
a. System-Wide mode (default):
When the host configures Intel PT to collect trace packets
of the entire system, it can leave the relevant VMX controls
clear to allow VMX-specific packets to
Currently, Intel Processor Trace do not support tracing in L1 guest
VMX operation(IA32_VMX_MISC[bit 14] is 0). As mentioned in SDM,
on these type of processors, execution of the VMXON instruction will
clears IA32_RTIT_CTL.TraceEn and any attempt to write IA32_RTIT_CTL
causes a general-protection
From: Chao Peng
Load/Store Intel Processor Trace register in context switch.
MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS.
In Host-Guest mode, we need load/resore PT MSRs only when PT
is enabled in guest.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
Currently, Intel Processor Trace do not support tracing in L1 guest
VMX operation(IA32_VMX_MISC[bit 14] is 0). As mentioned in SDM,
on these type of processors, execution of the VMXON instruction will
clears IA32_RTIT_CTL.TraceEn and any attempt to write IA32_RTIT_CTL
causes a general-protection
From: Chao Peng
Load/Store Intel Processor Trace register in context switch.
MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS.
In Host-Guest mode, we need load/resore PT MSRs only when PT
is enabled in guest.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
From: Chao Peng
Intel Processor Trace virtualization can be work in one
of 2 possible modes:
a. System-Wide mode (default):
When the host configures Intel PT to collect trace packets
of the entire system, it can leave the relevant VMX controls
clear to allow VMX-specific packets to
Add bit definitions for Intel PT MSRs to support trace output
directed to the memeory subsystem and holds a count if packet
bytes that have been sent out.
These are required by the upcoming PT support in KVM guests
for MSRs read/write emulation.
Signed-off-by: Luwei Kang
---
intel_pt_validate_hw_cap() validates whether a given PT capability is
supported by the hardware. It checks the PT capability array which
reflects the capabilities of the hardware on which the code is executed.
For setting up PT for KVM guests this is not correct as the capability
array for the
From: Chao Peng
The Intel Processor Trace (PT) MSR bit defines are in a private
header. The upcoming support for PT virtualization requires these defines
to be accessible from KVM code.
Move them to the global MSR header file.
Reviewed-by: Thomas Gleixner
Signed-off-by: Chao Peng
This adds support for "output to Trace Transport subsystem"
capability of Intel PT. It means that PT can output its
trace to an MMIO address range rather than system memory buffer.
Acked-by: Song Liu
Signed-off-by: Luwei Kang
---
arch/x86/events/intel/pt.c | 1 +
This adds support for "output to Trace Transport subsystem"
capability of Intel PT. It means that PT can output its
trace to an MMIO address range rather than system memory buffer.
Acked-by: Song Liu
Signed-off-by: Luwei Kang
---
arch/x86/events/intel/pt.c | 1 +
Add bit definitions for Intel PT MSRs to support trace output
directed to the memeory subsystem and holds a count if packet
bytes that have been sent out.
These are required by the upcoming PT support in KVM guests
for MSRs read/write emulation.
Signed-off-by: Luwei Kang
---
intel_pt_validate_hw_cap() validates whether a given PT capability is
supported by the hardware. It checks the PT capability array which
reflects the capabilities of the hardware on which the code is executed.
For setting up PT for KVM guests this is not correct as the capability
array for the
From: Chao Peng
The Intel Processor Trace (PT) MSR bit defines are in a private
header. The upcoming support for PT virtualization requires these defines
to be accessible from KVM code.
Move them to the global MSR header file.
Reviewed-by: Thomas Gleixner
Signed-off-by: Chao Peng
From: Chao Peng
pt_cap_get() is required by the upcoming PT support in KVM guests.
Export it and move the capabilites enum to a global header.
As a global functions, "pt_*" is already used for ptrace and
other things, so it makes sense to use "intel_pt_*" as a prefix.
Acked-by: Song Liu
From: Chao Peng
pt_cap_get() is required by the upcoming PT support in KVM guests.
Export it and move the capabilites enum to a global header.
As a global functions, "pt_*" is already used for ptrace and
other things, so it makes sense to use "intel_pt_*" as a prefix.
Acked-by: Song Liu
>From V12
- Refine the title and description of patch 1~3. -- Thomas Gleixner
- Rename the function of validate the capabilities of Intel PT. -- Thomas
Gleixner
- Add more description of Intel PT work mode. -- Alexander Shishkin
>From V11:
- In patch 3, arguments caps vs. cap is not good.
>From V12
- Refine the title and description of patch 1~3. -- Thomas Gleixner
- Rename the function of validate the capabilities of Intel PT. -- Thomas
Gleixner
- Add more description of Intel PT work mode. -- Alexander Shishkin
>From V11:
- In patch 3, arguments caps vs. cap is not good.
The function sdhci_allocate_bounce_buffer() always return zero at
present, so there's no need to have a return value, that will also make
error path easier.
CC: Linus Walleij
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c | 15 +--
1 file changed, 5 insertions(+), 10
The function sdhci_allocate_bounce_buffer() always return zero at
present, so there's no need to have a return value, that will also make
error path easier.
CC: Linus Walleij
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c | 15 +--
1 file changed, 5 insertions(+), 10
Enable the runtime pm for lpspi module
BuildInfo:
- U-Boot 2018.03-imx_4.14.y
Signed-off-by: Han Xu
Reviewed-by: Frank Li
Signed-off-by: Xiaoning Wang
---
V2:
- Add pinctrl/consumer.h include to fix the Warning error: implicit
declaration of function
Enable the runtime pm for lpspi module
BuildInfo:
- U-Boot 2018.03-imx_4.14.y
Signed-off-by: Han Xu
Reviewed-by: Frank Li
Signed-off-by: Xiaoning Wang
---
V2:
- Add pinctrl/consumer.h include to fix the Warning error: implicit
declaration of function
Add both ipg and per clock for lpspi to support i.MX8QM/QXP boards.
Signed-off-by: Xiaoning Wang
---
V2:
- No changes.
---
drivers/spi/spi-fsl-lpspi.c | 52 +
1 file changed, 41 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-fsl-lpspi.c
Remove Reset operation in fsl_lpspi_config(). This RST may cause both CLK
and CS pins go from high to low level under cs-gpio mode.
Add fsl_lpspi_reset() function after one message transfer to clear all
flags in use.
Signed-off-by: Xiaoning Wang
Reviewed-by: Fugang Duan
---
V2:
- Wrong place
Add both ipg and per clock for lpspi to support i.MX8QM/QXP boards.
Signed-off-by: Xiaoning Wang
---
V2:
- No changes.
---
drivers/spi/spi-fsl-lpspi.c | 52 +
1 file changed, 41 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-fsl-lpspi.c
Remove Reset operation in fsl_lpspi_config(). This RST may cause both CLK
and CS pins go from high to low level under cs-gpio mode.
Add fsl_lpspi_reset() function after one message transfer to clear all
flags in use.
Signed-off-by: Xiaoning Wang
Reviewed-by: Fugang Duan
---
V2:
- Wrong place
Use SR_TDF to judge if need send data, and SR_FCF to judge if
transmission end to replace the waiting after transmission end. This
waiting has no actual meaning, for the real end will set the FCF
flag.
Resolved an issue that could cause a transmission timeout when
transferring large amounts of
Use SR_TDF to judge if need send data, and SR_FCF to judge if
transmission end to replace the waiting after transmission end. This
waiting has no actual meaning, for the real end will set the FCF
flag.
Resolved an issue that could cause a transmission timeout when
transferring large amounts of
Add SPI slave mode support for imx7ulp, in PIO mode.
Add "spi-slave" attribute in spi node of dts file to boot.
For now, slave has to send the message which is same as the length of
message master sent.
Wire connection:
GND, SCK, MISO(to MISO of slave), MOSI(to MOSI of slave), SCS
Hello!
Typo in the subject: s/xxxsetbitsi/xxxsetbits/.
On 24.10.2018 10:35, Corentin Labbe wrote:
This patch converts ahci_sunxi to use xxxsetbits_le32 functions
Signed-off-by: Corentin Labbe
[...]
MBR, Sergei
Add SPI slave mode support for imx7ulp, in PIO mode.
Add "spi-slave" attribute in spi node of dts file to boot.
For now, slave has to send the message which is same as the length of
message master sent.
Wire connection:
GND, SCK, MISO(to MISO of slave), MOSI(to MOSI of slave), SCS
Hello!
Typo in the subject: s/xxxsetbitsi/xxxsetbits/.
On 24.10.2018 10:35, Corentin Labbe wrote:
This patch converts ahci_sunxi to use xxxsetbits_le32 functions
Signed-off-by: Corentin Labbe
[...]
MBR, Sergei
On Wed, Oct 24, 2018 at 9:50 AM Amir Goldstein wrote:
>
> On Tue, Oct 23, 2018 at 11:19 PM Phillip Potter wrote:
> >
> > Deduplicate the ext2 file type conversion implementation.
> >
> > Original patch by Amir Goldstein.
> >
> > v2:
> > - Rebased against Linux 4.19 by Phillip Potter
> > - This
On Wed, Oct 24, 2018 at 9:50 AM Amir Goldstein wrote:
>
> On Tue, Oct 23, 2018 at 11:19 PM Phillip Potter wrote:
> >
> > Deduplicate the ext2 file type conversion implementation.
> >
> > Original patch by Amir Goldstein.
> >
> > v2:
> > - Rebased against Linux 4.19 by Phillip Potter
> > - This
On 2018-09-08 at 02:03:28 +0800, Zhang Yi wrote:
> PageReserved() is already checked inside kvm_is_reserved_pfn(),
> remove it from kvm_set_pfn_dirty().
>
> Signed-off-by: Zhang Yi
> Signed-off-by: Zhang Yu
> Reviewed-by: David Hildenbrand
> Acked-by: Pankaj Gupta
> ---
> virt/kvm/kvm_main.c
On 2018-09-08 at 02:03:28 +0800, Zhang Yi wrote:
> PageReserved() is already checked inside kvm_is_reserved_pfn(),
> remove it from kvm_set_pfn_dirty().
>
> Signed-off-by: Zhang Yi
> Signed-off-by: Zhang Yu
> Reviewed-by: David Hildenbrand
> Acked-by: Pankaj Gupta
> ---
> virt/kvm/kvm_main.c
The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
it impossible to use the ICAP interface for partial reconfiguration.
This patch changes the driver to only activate PR over PCAP while the
device is actively being accessed by the driver for programming.
This allows both
The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
it impossible to use the ICAP interface for partial reconfiguration.
This patch changes the driver to only activate PR over PCAP while the
device is actively being accessed by the driver for programming.
This allows both
Would you mind opening a report at https://bugzilla.kernel.org? I'm
not sure if anybody will be able to do anything about this, but it's
always possible.
Submitted now, https://bugzilla.kernel.org/show_bug.cgi?id=201503
A complete dmesg log and "sudo lspci -vv" output from a successful
boot
Would you mind opening a report at https://bugzilla.kernel.org? I'm
not sure if anybody will be able to do anything about this, but it's
always possible.
Submitted now, https://bugzilla.kernel.org/show_bug.cgi?id=201503
A complete dmesg log and "sudo lspci -vv" output from a successful
boot
On Wed, 10 Oct 2018 19:49:23 +0200,
Connor McAdams wrote:
>
> The following changes since commit c6b6265d718d118e28e1ce8f91769aa886b54c94:
>
> Merge tag 'iwlwifi-fw-2018-10-03' of
> git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/linux-firmware
> (2018-10-08 09:23:53 -0400)
>
> are
On Wed, 10 Oct 2018 19:49:23 +0200,
Connor McAdams wrote:
>
> The following changes since commit c6b6265d718d118e28e1ce8f91769aa886b54c94:
>
> Merge tag 'iwlwifi-fw-2018-10-03' of
> git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/linux-firmware
> (2018-10-08 09:23:53 -0400)
>
> are
This patch convert meson DRM driver to use all xxxsetbits_le32 functions.
Signed-off-by: Corentin Labbe
Reviewed-by: Neil Armstrong
Tested-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_crtc.c | 14 +++---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 33 +++--
This patch convert meson DRM driver to use all xxxsetbits_le32 functions.
Signed-off-by: Corentin Labbe
Reviewed-by: Neil Armstrong
Tested-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_crtc.c | 14 +++---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 33 +++--
This patch convert dwmac-sun8i driver to use all xxxsetbits_le32 functions.
Signed-off-by: Corentin Labbe
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 62 +--
1 file changed, 16 insertions(+), 46 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
Since setbits32/clrbits32 work on be32, it's better to remove ambiguity on
the used data type.
Signed-off-by: Corentin Labbe
---
arch/powerpc/include/asm/fsl_lbc.h| 2 +-
arch/powerpc/include/asm/io.h | 4 +-
arch/powerpc/platforms/44x/canyonlands.c | 4 +-
This patch adds setbits_le32/clrbits_le32/clrsetbits_le32 and
setbits_le64/clrbits_le64/clrsetbits_le64 in linux/setbits.h header.
Signed-off-by: Corentin Labbe
---
include/linux/setbits.h | 84 +
1 file changed, 84 insertions(+)
create mode 100644
This patch convert dwmac-sun8i driver to use all xxxsetbits_le32 functions.
Signed-off-by: Corentin Labbe
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 62 +--
1 file changed, 16 insertions(+), 46 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
Since setbits32/clrbits32 work on be32, it's better to remove ambiguity on
the used data type.
Signed-off-by: Corentin Labbe
---
arch/powerpc/include/asm/fsl_lbc.h| 2 +-
arch/powerpc/include/asm/io.h | 4 +-
arch/powerpc/platforms/44x/canyonlands.c | 4 +-
This patch adds setbits_le32/clrbits_le32/clrsetbits_le32 and
setbits_le64/clrbits_le64/clrsetbits_le64 in linux/setbits.h header.
Signed-off-by: Corentin Labbe
---
include/linux/setbits.h | 84 +
1 file changed, 84 insertions(+)
create mode 100644
This series of patches are created On top of the
below repo.
//git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
BRANCH: next/drivers.
Nava kishore Manne (3):
firmware: xilinx: Add fpga API's
dt-bindings: fpga: Add bindings for ZynqMP fpga driver
fpga manager: Adding FPGA Manager
On Tue, Oct 23, 2018 at 01:32:56PM -0500, Rob Herring wrote:
> On Tue, Oct 23, 2018 at 4:21 AM Johan Hovold wrote:
> >
> > Hi Rob,
> >
> > On Tue, Sep 04, 2018 at 03:05:57PM +0200, Johan Hovold wrote:
> > > I think Rob will be picking up any patches that remain by the end of the
> > > release
This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.
Signed-off-by: Nava kishore Manne
---
This patch depends on the below series of patches
https://lkml.org/lkml/2018/9/12/983
Which is got integrated into the below upstream repo.
Hello
This patchset adds a new set of functions which are open-coded in lot of
place.
Basicly the pattern is always the same, "read, modify a bit, write"
some driver and the powerpc arch already have thoses pattern them as functions.
(like ahci_sunxi.c or dwmac-meson8b)
The first patch rename
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-Removed "" separators.
Changes for v1:
-Created a Seperate(New) DT binding file as
suggested by Rob.
Changes for RFC-V2:
This patch adds FPGA Manager support for the Xilinx
ZynqMP chip.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-Fixed some minor coding issues as suggested by
Moritz
Changes for v1:
-None.
Changes for RFC-V2:
-Updated the
This series of patches are created On top of the
below repo.
//git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
BRANCH: next/drivers.
Nava kishore Manne (3):
firmware: xilinx: Add fpga API's
dt-bindings: fpga: Add bindings for ZynqMP fpga driver
fpga manager: Adding FPGA Manager
On Tue, Oct 23, 2018 at 01:32:56PM -0500, Rob Herring wrote:
> On Tue, Oct 23, 2018 at 4:21 AM Johan Hovold wrote:
> >
> > Hi Rob,
> >
> > On Tue, Sep 04, 2018 at 03:05:57PM +0200, Johan Hovold wrote:
> > > I think Rob will be picking up any patches that remain by the end of the
> > > release
This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.
Signed-off-by: Nava kishore Manne
---
This patch depends on the below series of patches
https://lkml.org/lkml/2018/9/12/983
Which is got integrated into the below upstream repo.
Hello
This patchset adds a new set of functions which are open-coded in lot of
place.
Basicly the pattern is always the same, "read, modify a bit, write"
some driver and the powerpc arch already have thoses pattern them as functions.
(like ahci_sunxi.c or dwmac-meson8b)
The first patch rename
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-Removed "" separators.
Changes for v1:
-Created a Seperate(New) DT binding file as
suggested by Rob.
Changes for RFC-V2:
This patch adds FPGA Manager support for the Xilinx
ZynqMP chip.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-Fixed some minor coding issues as suggested by
Moritz
Changes for v1:
-None.
Changes for RFC-V2:
-Updated the
On 22-10-18, 14:29, Ross Zwisler wrote:
> From: Ricky Liang
>
> Add thermal logs in devfreq_cooling and cpu_cooling.
Why should we add them ?
> Also add logging to
> power_allocator when it starts to control power.
>
> These changes can lead to excessive log spam when running up against
>
On 22-10-18, 14:29, Ross Zwisler wrote:
> From: Ricky Liang
>
> Add thermal logs in devfreq_cooling and cpu_cooling.
Why should we add them ?
> Also add logging to
> power_allocator when it starts to control power.
>
> These changes can lead to excessive log spam when running up against
>
The function sdhci_allocate_bounce_buffer() always return zero at
present, so there's no need to have a return value, that will also make
error path easier.
CC: Linus Walleij
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c | 15 +--
1 file changed, 5 insertions(+), 10
The function sdhci_allocate_bounce_buffer() always return zero at
present, so there's no need to have a return value, that will also make
error path easier.
CC: Linus Walleij
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c | 15 +--
1 file changed, 5 insertions(+), 10
On Thu, Oct 18, 2018 at 9:57 AM Guo Ren wrote:
>
> On Thu, Oct 18, 2018 at 10:34:00AM +0200, Arnd Bergmann wrote:
> > On Thu, Oct 18, 2018 at 5:41 AM Guo Ren wrote:
> > >
> > > On Wed, Oct 17, 2018 at 05:44:17PM +0200, Arnd Bergmann wrote:
> > > > On Tue, Oct 16, 2018 at 5:33 AM Guo Ren wrote:
On Thu, Oct 18, 2018 at 9:57 AM Guo Ren wrote:
>
> On Thu, Oct 18, 2018 at 10:34:00AM +0200, Arnd Bergmann wrote:
> > On Thu, Oct 18, 2018 at 5:41 AM Guo Ren wrote:
> > >
> > > On Wed, Oct 17, 2018 at 05:44:17PM +0200, Arnd Bergmann wrote:
> > > > On Tue, Oct 16, 2018 at 5:33 AM Guo Ren wrote:
/0day-ci/linux/commits/Clark-Wang/spi-lpspi-Add-slave-mode-support-for-imx7ulp/20181024-125200
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save
/0day-ci/linux/commits/Clark-Wang/spi-lpspi-Add-slave-mode-support-for-imx7ulp/20181024-125200
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save
On Sun, 16 Sep 2018, srinivas.kandaga...@linaro.org wrote:
> From: Srinivas Kandagatla
>
> Qualcomm WCD9335 Codec is a standalone Hi-Fi audio codec IC,
> It has mulitple blocks like Soundwire controller, codec,
> Codec processing engine, ClassH controller, interrupt mux.
> It supports both
On Sun, 16 Sep 2018, srinivas.kandaga...@linaro.org wrote:
> From: Srinivas Kandagatla
>
> Qualcomm WCD9335 Codec is a standalone Hi-Fi audio codec IC,
> It has mulitple blocks like Soundwire controller, codec,
> Codec processing engine, ClassH controller, interrupt mux.
> It supports both
/0day-ci/linux/commits/Clark-Wang/spi-lpspi-Add-slave-mode-support-for-imx7ulp/20181024-125200
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
config: xtensa-allyesconfig (attached as .config)
compiler: xtensa-linux-gcc (GCC) 8.1.0
reproduce:
wget
https
/0day-ci/linux/commits/Clark-Wang/spi-lpspi-Add-slave-mode-support-for-imx7ulp/20181024-125200
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
config: xtensa-allyesconfig (attached as .config)
compiler: xtensa-linux-gcc (GCC) 8.1.0
reproduce:
wget
https
On paź 24, 2018 00:34, Nishad Kamdar wrote:
> Use the gpiod interface instead of the deprecated old non-descriptor
> interface.
Hi Nishad
Few more comments from me below.
> Signed-off-by: Nishad Kamdar
> ---
> Changes in v3:
> - Use a pointer to pointer for gpio_desc in
>struct
On paź 24, 2018 00:34, Nishad Kamdar wrote:
> Use the gpiod interface instead of the deprecated old non-descriptor
> interface.
Hi Nishad
Few more comments from me below.
> Signed-off-by: Nishad Kamdar
> ---
> Changes in v3:
> - Use a pointer to pointer for gpio_desc in
>struct
On Tue, Oct 23, 2018 at 03:35:31PM -0500, Dinh Nguyen wrote:
>
>
> On 10/23/2018 09:44 AM, Clément Péron wrote:
> > HI Dinh,
> >
> > On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen wrote:
> >>
> >> Hi Clément,
> >>
> >> On 10/09/2018 06:28 AM, Clément Péron wrote:
> >>> Cyclone5 and Arria10 doesn't
On Tue, Oct 23, 2018 at 03:35:31PM -0500, Dinh Nguyen wrote:
>
>
> On 10/23/2018 09:44 AM, Clément Péron wrote:
> > HI Dinh,
> >
> > On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen wrote:
> >>
> >> Hi Clément,
> >>
> >> On 10/09/2018 06:28 AM, Clément Péron wrote:
> >>> Cyclone5 and Arria10 doesn't
On Wed 2018-10-24 11:40:07, Nickhu wrote:
> There are three sleep states in nds32:
> suspend to idle,
> suspend to standby,
> suspend to ram
>
> In suspend to ram, we use the 'standby' instruction to emulate
> power management device to hang the system util wakeup source
> send
On Wed 2018-10-24 11:40:07, Nickhu wrote:
> There are three sleep states in nds32:
> suspend to idle,
> suspend to standby,
> suspend to ram
>
> In suspend to ram, we use the 'standby' instruction to emulate
> power management device to hang the system util wakeup source
> send
On Tue, Oct 23, 2018 at 11:19 PM Phillip Potter wrote:
>
> Deduplicate the ext2 file type conversion implementation.
>
> Original patch by Amir Goldstein.
>
> v2:
> - Rebased against Linux 4.19 by Phillip Potter
> - This version does not remove EXT2_FT_x enum from fs/ext2/ext2.h,
> as these
On Tue, Oct 23, 2018 at 11:19 PM Phillip Potter wrote:
>
> Deduplicate the ext2 file type conversion implementation.
>
> Original patch by Amir Goldstein.
>
> v2:
> - Rebased against Linux 4.19 by Phillip Potter
> - This version does not remove EXT2_FT_x enum from fs/ext2/ext2.h,
> as these
Hi Alan,
Thanks for the quick response..
Please find my response inline.
> -Original Message-
> From: Alan Tull [mailto:at...@kernel.org]
> Sent: Monday, October 22, 2018 11:12 PM
> To: Nava kishore Manne
> Cc: Moritz Fischer ; Rob Herring ;
> Mark Rutland ; Michal Simek ;
> Rajan Vaja
Hi Alan,
Thanks for the quick response..
Please find my response inline.
> -Original Message-
> From: Alan Tull [mailto:at...@kernel.org]
> Sent: Monday, October 22, 2018 11:12 PM
> To: Nava kishore Manne
> Cc: Moritz Fischer ; Rob Herring ;
> Mark Rutland ; Michal Simek ;
> Rajan Vaja
On Tue, Oct 23, 2018 at 11:19 PM Phillip Potter wrote:
>
> This cleanup series is a respin of Amir Goldstein's work, created
> in late 2016. It removes several instances of duplicated code. Most
> of the duplication dates back to git pre-historic era.
>
> The controversial aspect of this cleanup
On Tue, Oct 23, 2018 at 11:19 PM Phillip Potter wrote:
>
> This cleanup series is a respin of Amir Goldstein's work, created
> in late 2016. It removes several instances of duplicated code. Most
> of the duplication dates back to git pre-historic era.
>
> The controversial aspect of this cleanup
On Mon, Apr 02, 2018 at 11:20:00AM +0800, Ye, Xiaolong wrote:
>
> Greeting,
>
> FYI, we noticed a -9.9% regression of unixbench.score due to commit:
>
>
> commit: d519329f72a6f36bc4f2b85452640cfe583b4f81 ("sched/fair: Update
> util_est only on util_avg updates")
>
On 22-10-18, 15:12, Dmitry Osipenko wrote:
> Because there is one Tegra20 board (tegra20-trimslice) that doesn't declare
> necessary regulators, but we want to have CPU frequency scaling. I couldn't
> find board schematics and so don't know if CPU / CORE voltages are fixed on
> Trim-Slice or it is
On Mon, Apr 02, 2018 at 11:20:00AM +0800, Ye, Xiaolong wrote:
>
> Greeting,
>
> FYI, we noticed a -9.9% regression of unixbench.score due to commit:
>
>
> commit: d519329f72a6f36bc4f2b85452640cfe583b4f81 ("sched/fair: Update
> util_est only on util_avg updates")
>
On 22-10-18, 15:12, Dmitry Osipenko wrote:
> Because there is one Tegra20 board (tegra20-trimslice) that doesn't declare
> necessary regulators, but we want to have CPU frequency scaling. I couldn't
> find board schematics and so don't know if CPU / CORE voltages are fixed on
> Trim-Slice or it is
The thermal driver is a standalone driver for monitoring SoC temperature
by enabling thermal sensor, so it can be enabled even when CONFIG_CPU_FREQ
is NOT set. So remove the dependency with CPU_THERMAL.
Add CONFIG_CPU_FREQ check for cpu-freq related operation in thermal
driver to make thermal
The thermal driver is a standalone driver for monitoring SoC temperature
by enabling thermal sensor, so it can be enabled even when CONFIG_CPU_FREQ
is NOT set. So remove the dependency with CPU_THERMAL.
Add CONFIG_CPU_FREQ check for cpu-freq related operation in thermal
driver to make thermal
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