On Sun, Nov 04, 2018 at 10:54:56AM -0500, thesve...@gmail.com wrote:
> From: Sven Van Asbroeck
>
> Add a driver for the Arcx anybus bridge.
>
> This chip embeds up to two Anybus-S application connectors
> (slots), and connects to the SoC via a parallel memory bus.
> There is also a CAN power rea
On 11/5/18 8:55 AM, Daniel Jordan wrote:
> Motivates and explains the ktask API for kernel clients.
>
> Signed-off-by: Daniel Jordan
> ---
> Documentation/core-api/index.rst | 1 +
> Documentation/core-api/ktask.rst | 213 +++
> 2 files changed, 214 insertions(+)
>
On Mon, Nov 05, 2018 at 06:11:52PM +0200, Tomer Maimon wrote:
> Modify Nuvoton watchdog Kconfig default supported architecture
> name to ARCH_NPCM7XX because ARCH_NPCM750 architecture name
> is not supported.
>
> Signed-off-by: Tomer Maimon
Reviewed-by: Guenter Roeck
> ---
> drivers/watchdog/
This patch introduces a new iterator for_each_free_mem_pfn_range_in_zone.
This iterator will take care of making sure a given memory range provided
is in fact contained within a zone. It takes are of all the bounds checking
we were doing in deferred_grow_zone, and deferred_init_memmap. In addition
On Mon, Nov 05, 2018 at 04:13:56PM -0300, Arnaldo Carvalho de Melo wrote:
>
> I did the tests and it seems to work, its the same method used by the
> kernel sources, so I have this in place now:
>
> commit e2c39f36c354a06c6e9d32d4fdf8660b41803d82
> Author: Arnaldo Carvalho de Melo
> Date: Mon
On 11/5/18, Andy Shevchenko wrote:
> On Mon, Nov 5, 2018 at 7:19 PM Pierre-Louis Bossart
> wrote:
>>
>>
>> >>> We have this ("strange") lines over the drivers:
>> >>>
>> >>> config BAR
>> >>> depends on FOO || FOO=n
>> >>>
>> >>> which guarantees that FOO will be not module when BAR is built-in.
On Mon, Nov 05, 2018 at 12:18:33PM -0800, Andrew Morton wrote:
> > +++ b/mm/mmu_notifier.c
>
> But as it has no callers, why retain it?
... and this patch missed the declaration of mmu_notifier_synchronize
in include/linux/mmu_notifier.h (whether we delete it or rename it,
that mention of it need
On Mon, 5 Nov 2018 12:40:00 -0800 Bart Van Assche wrote:
> This patch suppresses the following sparse warning:
>
> ./include/linux/slab.h:332:43: warning: dubious: x & !y
>
> ...
>
> --- a/include/linux/slab.h
> +++ b/include/linux/slab.h
> @@ -329,7 +329,7 @@ static __always_inline enum kmall
This patch is meant to try and consolidate all of the locking and unlocking
of both the parent and device when attaching or removing a driver from a
given device.
To do that I first consolidated the lock pattern into two functions
__device_driver_lock and __device_driver_unlock. After doing that I
This patch moves the async_synchronize_full call out of
__device_release_driver and into driver_detach.
The idea behind this is that the async_synchronize_full call will only
guarantee that any existing async operations are flushed. This doesn't do
anything to guarantee that a hotplug event that m
Hi,
On Mon, Nov 5, 2018 at 12:37 PM Rob Herring wrote:
>
> On Thu, Nov 01, 2018 at 01:29:54PM -0700, Doug Anderson wrote:
> > Hi,
> >
> > On Thu, Nov 1, 2018 at 5:07 AM Veerabhadrarao Badiganti
> > wrote:
> > >
> > > For SDM845 SOC, new compatible string "qcom,sdm845-sdhci" is added.
> > >
> >
This patch introduces four new variants of the async_schedule_ functions
that allow scheduling on a specific NUMA node.
The first two functions are async_schedule_near and
async_schedule_near_domain which end up mapping to async_schedule and
async_schedule_domain but provide NUMA node specific fun
As per upstream discussion [1], we should have an SoC-specific
compatible string for Qualcomm's SDHCI nodes. Let's add it.
[1] https://lkml.kernel.org/r/20181105203657.GA32282@bogus
Signed-off-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/ms
As per upstream discussion [1], we should have an SoC-specific
compatible string for Qualcomm's SDHCI nodes. Let's add it.
[1] https://lkml.kernel.org/r/20181105203657.GA32282@bogus
Signed-off-by: Douglas Anderson
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 4 ++--
arch/arm/boot/dts/qcom-msm897
On 03-Nov-18 12:02 AM, Andy Shevchenko wrote:
On Fri, Nov 2, 2018 at 12:37 PM Rajneesh Bhardwaj
wrote:
The LTR values follow PCIE LTR encoding format and can be decoded as per
https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf
This adds suppo
On 5 November 2018 at 21:51, Florian Fainelli wrote:
> On 11/5/18 12:44 PM, Ard Biesheuvel wrote:
>> On 5 November 2018 at 21:41, Florian Fainelli wrote:
>>> On 11/5/18 12:39 PM, Ard Biesheuvel wrote:
Hi Florian,
On 31 October 2018 at 20:28, Florian Fainelli wrote:
> ARM64 is
Thanks again for your time. My response inline.
On 02-Nov-18 11:57 PM, Andy Shevchenko wrote:
On Fri, Nov 2, 2018 at 12:29 PM Rajneesh Bhardwaj
wrote:
This adds support to show the Latency Tolerance Reporting for the IPs on
the PCH as reported by the PMC. The format shown here is raw LTR data
On 11/5/18, David Abdurachmanov wrote:
> Marcin Juszkiewicz reported issues while generating syscall table for riscv
> using 4.20-rc1. The patch refactors our unistd.h files to match some other
> architectures.
>
> - Add asm/unistd.h UAPI header, which has __ARCH_WANT_NEW_STAT
> - Remove asm/sysca
On 11/5/18 8:55 AM, Daniel Jordan wrote:
> diff --git a/init/Kconfig b/init/Kconfig
> index 41583f468cb4..ed82f76ed0b7 100644
> --- a/init/Kconfig
> +++ b/init/Kconfig
> @@ -346,6 +346,17 @@ config AUDIT_TREE
> depends on AUDITSYSCALL
> select FSNOTIFY
>
> +config KTASK
> + bool "
On Fri, Nov 02, 2018 at 06:56:50PM +0100, Milian Wolff wrote:
SNIP
> > >
> > > Note how precise levels 0 and 1 do not produce any samples where unwinding
> > > fails. But precise level 2 produces some, and precise level 3 increases
> > > the
> > > amount (by ca. ~2x).
> > >
> > > I can reproduc
On Mon, Nov 05, 2018 at 12:18:33PM -0800, Andrew Morton wrote:
> On Mon, 5 Nov 2018 11:29:55 -0800 Sean Christopherson
> wrote:
>
> > ...and update its comment to explicitly reference its association with
> > mmu_notifier_call_srcu().
> >
> > Contrary to its name, mmu_notifier_synchronize() do
On Mon, Nov 5, 2018 at 7:19 PM Pierre-Louis Bossart
wrote:
>
>
> >>> We have this ("strange") lines over the drivers:
> >>>
> >>> config BAR
> >>> depends on FOO || FOO=n
> >>>
> >>> which guarantees that FOO will be not module when BAR is built-in.
> >> That's what I normally use, but I could not
On Sun, 4 Nov 2018 10:54:58 -0500, thesve...@gmail.com wrote:
> From: Sven Van Asbroeck
>
> This patch adds devicetree binding documentation for the
> Arcx anybus bridge.
>
> Signed-off-by: Sven Van Asbroeck
> ---
> .../bindings/misc/arcx,anybus-bridge.txt | 34 +++
> 1 f
On 5 November 2018 at 21:41, Florian Fainelli wrote:
> On 11/5/18 12:39 PM, Ard Biesheuvel wrote:
>> Hi Florian,
>>
>> On 31 October 2018 at 20:28, Florian Fainelli wrote:
>>> ARM64 is the only architecture that re-defines
>>> __early_init_dt_declare_initrd() in order for that function to populat
On Sun, 4 Nov 2018 10:54:57 -0500, thesve...@gmail.com wrote:
> From: Sven Van Asbroeck
>
> arcx Inc. is an engineering company which provides advanced
> embedded systems and consulting services.
>
> Archronix is a technology design and product engineering firm
> specializing in hardware contro
On Mon, Nov 05, 2018 at 12:38:05PM -0800, Olof Johansson wrote:
> Yeah, that's the way we've been trying to do for various subsystems
> and it's been working pretty well. Of course, if there's need to
> coordinate more closely for something in the future we'll be happy to
> do so.
Goodie. Let's do
On Fri Oct 19 18, Stefan Berger wrote:
Extend the documentation for trusted keys with documentation for how to
set up a key for a TPM 2.0 so it can be used with a TPM 2.0 as well.
Signed-off-by: Stefan Berger
Reviewed-by: Mimi Zohar
---
.../security/keys/trusted-encrypted.rst | 31 ++
On Mon, Nov 5, 2018 at 7:30 PM Jarkko Sakkinen
wrote:
>
> On Sat, Nov 03, 2018 at 03:17:35PM +0200, Andy Shevchenko wrote:
> > On Sat, Nov 3, 2018 at 1:18 AM Jarkko Sakkinen
> > wrote:
> > >
> > > ENCLS is an umbrella instruction for a variety of cpl0 SGX functions.
> > > The ENCLS function that
This patch suppresses the following sparse warning:
./include/linux/slab.h:332:43: warning: dubious: x & !y
Fixes: 1291523f2c1d ("mm, slab/slub: introduce kmalloc-reclaimable caches")
Cc: Vlastimil Babka
Cc: Mel Gorman
Cc: Christoph Lameter
Cc: Roman Gushchin
Signed-off-by: Bart Van Assche
-
In two of the gen5 socfpga devicetree files, there are some lines
indented using spaces instead of tabs.
Fix this by correctly indenting them with tabs.
Signed-off-by: Simon Goldschmidt
---
arch/arm/boot/dts/socfpga.dtsi | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 4 ++-
On Mon, 29 Oct 2018 09:55:23 -0700, Florian Fainelli
wrote:
> All boards replicate the aliases node, move the aliases node to
> bcm-nsp.dtsi and add all the serial and ethernet ports such that a boot
> program like u-boot can populate MAC addresses accordingly.
>
> Signed-off-by: Florian Fainell
On Mon, Nov 5, 2018 at 11:47 AM Borislav Petkov wrote:
>
> Hi Olof,
>
> On Mon, Nov 05, 2018 at 06:51:26AM -0800, Olof Johansson wrote:
> > In general, for new functionality where needing both the driver change
> > and a DT change to enable it (or a driver change and a config change
> > to enable
On Thu, Nov 01, 2018 at 01:29:54PM -0700, Doug Anderson wrote:
> Hi,
>
> On Thu, Nov 1, 2018 at 5:07 AM Veerabhadrarao Badiganti
> wrote:
> >
> > For SDM845 SOC, new compatible string "qcom,sdm845-sdhci" is added.
> >
> > Signed-off-by: Veerabhadrarao Badiganti
> > ---
> > Documentation/device
On Sun, Nov 04, 2018 at 04:50:39PM -0800, David Miller wrote:
> From: Jiri Olsa
> Date: Sun, 4 Nov 2018 21:18:21 +0100
>
> > do you have some code I could check on?
>
> All I have is this patch which parallelizes the mmap readers in perf
> top.
I put something together.. still testing, but it's
Em Mon, Nov 05, 2018 at 07:53:17PM +, Hunter, Adrian escreveu:
> > -Original Message-
> > From: Arnaldo Carvalho de Melo [mailto:a...@kernel.org]
> > Sent: Monday, November 5, 2018 9:36 PM
> > To: Hunter, Adrian
> > Cc: Jiri Olsa ; Andi Kleen ; linux-
> > ker...@vger.kernel.org; leo...
On 11/5/18 2:27 PM, Simon Goldschmidt wrote:
> Follow the recent trend for the license description.
>
> This is also in an effort to fully sync the devicetrees with U-Boot.
>
> Signed-off-by: Simon Goldschmidt
> ---
> Resending this as requested by Dinh. It still applies on top of
> 4.20-rc1
On Mon, 5 Nov 2018, Andy Lutomirski wrote:
> On Mon, Nov 5, 2018 at 11:25 AM Nadav Amit wrote:
> Linus, hpa, or Dave, a question for you: suppose I map some page
> writably, write to it, then upgrade permissions to allow execute.
> Must I force all CPUs that might execute from it without first
> s
Follow the recent trend for the license description.
This is also in an effort to fully sync the devicetrees with U-Boot.
Signed-off-by: Simon Goldschmidt
---
Resending this as requested by Dinh. It still applies on top of
4.20-rc1 as it only touches the file headers and nothing has changed
ther
Commit-ID: 63ecd3b13d5cf07959a2315ec62a7c62e20df114
Gitweb: https://git.kernel.org/tip/63ecd3b13d5cf07959a2315ec62a7c62e20df114
Author: Borislav Petkov
AuthorDate: Thu, 1 Nov 2018 16:24:43 +0100
Committer: Borislav Petkov
CommitDate: Mon, 5 Nov 2018 21:18:31 +0100
x86/gart: Rewrite ear
On Mon, Nov 05, 2018 at 04:35:40PM +0100, Ingo Molnar wrote:
> s/shutdown
> /shut down
Fixed.
Thx.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
Commit-ID: 43500e6f294d175602606c77bfb0d8cd4ea88b4f
Gitweb: https://git.kernel.org/tip/43500e6f294d175602606c77bfb0d8cd4ea88b4f
Author: Sean Christopherson
AuthorDate: Mon, 5 Nov 2018 10:57:25 -0800
Committer: Borislav Petkov
CommitDate: Mon, 5 Nov 2018 20:54:20 +0100
x86/cpufeatures:
Add schedstats to measure the effectiveness of searching for idle CPUs
and stealing tasks. This is a temporary patch intended for use during
development only. SCHEDSTAT_VERSION is bumped to 16, and the following
fields are added to the per-CPU statistics of /proc/schedstat:
field 10: # of times
On 11/5/18 10:35 AM, Linus Torvalds wrote:
On Mon, Nov 5, 2018 at 10:28 AM Yang Shi wrote:
Actually, the commit is mainly for optimizing the long stall time caused
by holding mmap_sem by write when unmapping or shrinking large mapping.
It downgrades write mmap_sem to read when zapping pages.
From: Steve Sistare
Provide struct sparsemask and functions to manipulate it. A sparsemask is
a sparse bitmap. It reduces cache contention vs the usual bitmap when many
threads concurrently set, clear, and visit elements, by reducing the number
of significant bits per cacheline. For each 64 by
The STEAL feature causes regressions on hackbench on larger NUMA systems,
so disable it on systems with more than sched_steal_node_limit nodes
(default 2). Note that the feature remains enabled as seen in features.h
and /sys/kernel/debug/sched_features, but stealing is only performed if
nodes <= s
The detach_task function takes a struct lb_env argument, but only needs a
few of its members. Pass the rq and cpu arguments explicitly so the
function may be called from code that is not based on lb_env. No
functional change.
Signed-off-by: Steve Sistare
---
kernel/sched/fair.c | 14 +++---
On Mon, 5 Nov 2018 11:29:55 -0800 Sean Christopherson
wrote:
> ...and update its comment to explicitly reference its association with
> mmu_notifier_call_srcu().
>
> Contrary to its name, mmu_notifier_synchronize() does not synchronize
> the notifier's SRCU instance, but rather waits for RCU c
From: Steve Sistare
Define and initialize a sparse bitmap of overloaded CPUs, per
last-level-cache scheduling domain, for use by the CFS scheduling class.
Save a pointer to cfs_overload_cpus in the rq for efficient access.
Signed-off-by: Steve Sistare
---
include/linux/sched/topology.h | 1 +
An overloaded CPU has more than 1 runnable task. When a CFS task wakes
on a CPU, if h_nr_running transitions from 1 to more, then set the CPU in
the cfs_overload_cpus bitmap. When a CFS task sleeps, if h_nr_running
transitions from 2 to less, then clear the CPU in cfs_overload_cpus.
Signed-off-b
When a CPU has no more CFS tasks to run, and idle_balance() fails to find a
task, then attempt to steal a task from an overloaded CPU in the same LLC,
using the cfs_overload_cpus bitmap to efficiently identify candidates. To
minimize search time, steal the first migratable task that is found when
Move the update of idle_stamp from idle_balance to the call site in
pick_next_task_fair, to prepare for a future patch that adds work to
pick_next_task_fair which must be included in the idle_stamp interval.
No functional change.
Signed-off-by: Steve Sistare
---
kernel/sched/fair.c | 22
When CONFIG_X86_INTEL_MID is set pci_root_ops is written to inside
intel_mid_pci_init(which is marked __init) and not modified after. This
makes pci_root_ops a suitable candidate for annotating as
__ro_after_init.
Signed-off-by: Zubin Mithra
---
arch/x86/pci/common.c | 2 +-
1 file changed, 1 in
Define a simpler version of can_migrate_task called can_migrate_task_llc
which does not require a struct lb_env argument, and judges whether a
migration from one CPU to another within the same LLC should be allowed.
Signed-off-by: Steve Sistare
---
kernel/sched/fair.c | 28 ++
Add functions sd_llc_alloc_all() and sd_llc_free_all() to allocate and
free data pointed to by struct sched_domain_shared at the last-level-cache
domain. sd_llc_alloc_all() is called after the SD hierarchy is known, to
eliminate the unnecessary allocations that would occur if we instead
allocated
When a CPU has no more CFS tasks to run, and idle_balance() fails to
find a task, then attempt to steal a task from an overloaded CPU in the
same LLC. Maintain and use a bitmap of overloaded CPUs to efficiently
identify candidates. To minimize search time, steal the first migratable
task that is f
On 11/5/18 6:50 PM, Linus Torvalds wrote:
> On Sun, Nov 4, 2018 at 9:08 PM kernel test robot
> wrote:
>>
>> FYI, we noticed a -64.1% regression of will-it-scale.per_thread_ops
>> due to commit 9bc8039e715d ("mm: brk: downgrade mmap_sem to read when
>> shrinking")
>
> Ugh. That looks pretty bad.
On Mon, Nov 5, 2018 at 1:39 PM Palmer Dabbelt wrote:
>
> On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh...@kernel.org wrote:
> > On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote:
> >>
> >> Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
> >> But it doesn't need a separate thr
On 11/2/2018 7:39 PM, Subhra Mazumdar wrote:
> On 10/22/18 7:59 AM, Steve Sistare wrote:
>> When a CPU has no more CFS tasks to run, and idle_balance() fails to
>> find a task, then attempt to steal a task from an overloaded CPU in the
>> same LLC. Maintain and use a bitmap of overloaded CPUs to ef
From: Dinh Nguyen
Create a separate reset driver that uses the reset operations in
reset-simple. The reset driver for the SoCFPGA platform needs to
register early in order to be able bring online timers that needed
early in the kernel bootup.
We do not need this early reset driver for Stratix10,
"altr,stratix10-rst-mgr" is used for the Stratix10 reset manager.
Signed-off-by: Dinh Nguyen
---
Documentation/devicetree/bindings/reset/socfpga-reset.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/reset/socfpga-reset.txt
b/Documentat
From: Dinh Nguyen
The standard reset-simple driver the uses the "altr,rst-mgr" binding is
not getting initialized early enough in the boot process, so timers
that the kernel needs are still left in reset. Thus an early
reset driver was created. This early reset driver is only for the
SoCFPGA 32-b
On Mon, Nov 5, 2018 at 11:25 AM Nadav Amit wrote:
>
> From: Andy Lutomirski
> Sent: November 5, 2018 at 7:03:49 PM GMT
> > To: Nadav Amit
> > Cc: Peter Zijlstra , Ingo Molnar ,
> > LKML , X86 ML , H. Peter
> > Anvin , Thomas Gleixner , Borislav
> > Petkov , Dave Hansen , Andy
> > Lutomirski ,
This can be accomplished with multidimensional binary trees and basic functions
that search the shape of the binary tree
I’ve figured a revolving dma to keep memory usuage lean, but that really taxes
the cpu I think
I’m sorry I have to read like 3 nix kernels and no one wants to talk to me :(
> -Original Message-
> From: Arnaldo Carvalho de Melo [mailto:a...@kernel.org]
> Sent: Monday, November 5, 2018 9:36 PM
> To: Hunter, Adrian
> Cc: Jiri Olsa ; Andi Kleen ; linux-
> ker...@vger.kernel.org; leo@linaro.org; David Miller
> ; Mathieu Poirier
> Subject: Re: [PATCH 1/5] perf
* Thomas Gleixner wrote:
> Add SPDX identifiers to all files in kernel/time and remove the license
> boiler plates.
>
> Aside of that use the chance to get rid of (stale) file references and tidy
> up the top of file comments as they are touched anyway by this work.
>
> This work is based on
+++ Will Deacon [05/11/18 19:26 +]:
On Mon, Nov 05, 2018 at 07:53:23PM +0100, Jessica Yu wrote:
Instead of saving a pointer to the .plt and .init.plt sections to apply
plt-based relocations, save and use their section indices instead.
The mod->arch.{core,init}.plt pointers were problematic
Hi Olof,
On Mon, Nov 05, 2018 at 06:51:26AM -0800, Olof Johansson wrote:
> In general, for new functionality where needing both the driver change
> and a DT change to enable it (or a driver change and a config change
> to enable it), we have been merging the changes separately between
> driver tre
Add a generic clk property for clks which are not intended to be used by
the OS due to security restrictions put in place by firmware. For
example, on some Qualcomm firmwares reading or writing certain clk
registers causes the entire system to reboot, but on other firmwares
reading and writing thos
Certain firmware configurations "protect" clks and cause the entire
system to reboot when a non-secure OS such as Linux tries to read or
write protected clk registers. But other firmware configurations allow
reading or writing the same registers, and they may actually require
that the OS use the ot
See full explanation in patch #1. It looks like on qcom platforms
we're increasing the number of situations where we need to have
a set of clks that aren't touched by the OS because firmware
wants them for itself. This series introduces a method to do that
by specifying in DT what clks shouldn't be
Hello Vincent,
Στις 2018-10-31 12:35, Vincent Chen έγραψε:
RISC-V permits each vendor to develop respective extension ISA based
on RISC-V standard ISA. This means that these vendor-specific features
may be compatible to their compiler and CPU. Therefore, each vendor may
be considered a sub-archi
On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh...@kernel.org wrote:
On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote:
Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
But it doesn't need a separate thread node for defining SMT systems.
Multiple cpu phandle properties can be
b43 wireless driver includes an internal implementation of
cordic algorithm, although there's a common cordic library
which was split out from brcmsmac driver. Use that and drop
internal implementation.
During the process, brcmfmac was driver was also cleaned up.
Please note that this series is o
Current driver includes macro that is available from general cordic
library. Use that and drop unused duplicate and unneeded internal
definitions.
Signed-off-by: Priit Laes
---
v2: Use single patch instead of change/removal patches.
---
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_i
Also append CORDIC_ prefix to nonprefixed macros.
Signed-off-by: Priit Laes
---
include/linux/cordic.h | 9 +
lib/cordic.c | 23 +++
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/include/linux/cordic.h b/include/linux/cordic.h
index cf68c
Em Mon, Nov 05, 2018 at 07:21:44PM +, Hunter, Adrian escreveu:
> > In Monday, November 5, 2018 7:30 PM, Arnaldo Carvalho de Melo wrote
> > > +struct map *thread__find_map_fallback(struct thread *thread, u8
> > cpumode,
> > > + u64 addr, struct addr_location *al) {
On Thu, 1 Nov 2018 11:02:10 +0100, Lars Poeschel wrote:
> Add a simple binding doc for the pn532.
>
> Signed-off-by: Lars Poeschel
> ---
> Changes in v4:
> - Add documentation about reg property in case of i2c
>
> Changes in v3:
> - seperate binding doc instead of entry in trivial-devices.txt
>
...and update its comment to explicitly reference its association with
mmu_notifier_call_srcu().
Contrary to its name, mmu_notifier_synchronize() does not synchronize
the notifier's SRCU instance, but rather waits for RCU callbacks to
finished, i.e. it invokes rcu_barrier(). The RCU documentation
On Sun, 2018-11-04 at 17:31 +0100, Rafael J. Wysocki wrote:
> From: Rafael J. Wysocki
>
> The venerable menu governor does some thigns that are quite
> questionable in my view. First, it includes timer wakeups in
> the pattern detection data and mixes them up with wakeups from
> other sources wh
On Mon, Nov 05, 2018 at 07:53:23PM +0100, Jessica Yu wrote:
> Instead of saving a pointer to the .plt and .init.plt sections to apply
> plt-based relocations, save and use their section indices instead.
>
> The mod->arch.{core,init}.plt pointers were problematic for livepatch
> because they pointe
On Fri, 2 Nov 2018 15:42:07 +0800, Song Qiang wrote:
> Signed-off-by: Song Qiang
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring
From: Andy Lutomirski
Sent: November 5, 2018 at 7:03:49 PM GMT
> To: Nadav Amit
> Cc: Peter Zijlstra , Ingo Molnar ,
> LKML , X86 ML , H. Peter Anvin
> , Thomas Gleixner , Borislav Petkov
> , Dave Hansen , Andy Lutomirski
> , Kees Cook , Dave Hansen
> , Masami Hiramatsu
> Subject: Re: [PATCH
On Mon, Nov 5, 2018 at 9:20 AM Dave Hansen wrote:
>
>
> On 11/4/18 9:14 PM, Andy Lutomirski wrote:
> > I should add: if this patch is *not* applied, then I think we'll
> > need to replace the sw_error_code check with user_mode(regs) to avoid
> > an info leak if CET is enabled. Because, with CET,
> -Original Message-
> From: Arnaldo Carvalho de Melo [mailto:a...@kernel.org]
> Sent: Monday, November 5, 2018 7:30 PM
> To: Hunter, Adrian
> Cc: Jiri Olsa ; Andi Kleen ; linux-
> ker...@vger.kernel.org; leo@linaro.org; David Miller
> ; Mathieu Poirier
> Subject: Re: [PATCH 1/5] perf
Tim,
On Mon, 5 Nov 2018, Tim Chen wrote:
> On 11/03/2018 11:07 AM, Thomas Gleixner wrote:
> >>case X86_BUG_SPECTRE_V2:
> >>return sprintf(buf, "%s%s%s%s%s%s\n",
> >> spectre_v2_strings[spectre_v2_enabled],
> >> - boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB
On Sun, Oct 14, 2018 at 08:22:19PM -0700, frowand.l...@gmail.com wrote:
> From: Frank Rowand
>
> The todo.txt file was created by a previous maintainer and has
> never been updated by the current OPEN FIRMWARE AND FLATTENED
> DEVICE TREE maintainers. Remove the out of date file.
>
> Signed-off-
This patch removes the unnecessary field int_vref_mv in ad7780_state
referring to the device's voltage.
Signed-off-by: Renato Lui Geh
---
Changes in v3:
- removed unnecessary int_vref_mv from ad7780_state
Changes in v4:
- removed voltage reading on probe
drivers/staging/iio/adc/
The ad7780 driver previously did not read the correct device output, as
it read an outdated value set at initialization. It now updates its
voltage on read.
Signed-off-by: Renato Lui Geh
---
Changes in v3:
- removed initialization (int voltage_uv = 0)
- returns error when voltage
The purpose of this series is to correct an issue in the driver's raw
read function and remove an unnecessary struct field.
Changelog:
*v2
- separated original patch into two patches
(https://marc.info/?l=linux-iio&m=154047435605492)
*v3
- reordered patches so that fixes
Em Mon, Nov 05, 2018 at 03:46:12PM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Mon, Nov 05, 2018 at 02:11:40PM -0300, Arnaldo Carvalho de Melo escreveu:
> > Em Mon, Nov 05, 2018 at 07:44:33AM -0800, Guenter Roeck escreveu:
> > > On Wed, Oct 31, 2018 at 01:44:59PM -0300, Arnaldo Carvalho de Melo
On Mon 05 Nov 07:45 PST 2018, Vinod Koul wrote:
> PMS405 also features PON block, so add PON and PWRKEY nodes
>
> Signed-off-by: Vinod Koul
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/pms405.dtsi | 16
> 1 file changed, 16 insertions(+)
>
>
Hi, I'm wondering if there is any update for the patch.
Thanks!
On Wed, Oct 31, 2018 at 2:36 AM Jessica Yu wrote:
>
> +++ Ke Wu [22/10/18 15:26 -0700]:
> >Make mod_verify_sig to use all trusted keys. This allows keys in
> >secondary_trusted_keys to be used to verify PKCS#7 signature on a
> >kern
On Fri, 2018-11-02 at 08:39 -0700, Doug Smythies wrote:
>
> I have been testing this V2 against a baseline that includes all
> of the pending menu patches. My baseline kernel is somewhere
> after 4.19, at 345671e.
>
> A side note:
> Recall that with the menu patch set tests, I found that the base
On 11/03/2018 11:07 AM, Thomas Gleixner wrote:
> Tim,
>
> On Tue, 30 Oct 2018, Tim Chen wrote:
>> Extract the logic to show IBPB, STIBP usages in cpu_show_common()
>> into helper functions.
>>
>> Later patches will add other userspace Spectre v2 mitigation modes.
>> This patch makes it easy to sho
On Mon 05 Nov 07:45 PST 2018, Vinod Koul wrote:
> We can use BAM DAM for serial UART data transfers, so add it
>
> Signed-off-by: Vinod Koul
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/a
On Mon 05 Nov 07:45 PST 2018, Vinod Koul wrote:
> Add the BAM DMA instance found in BLSP1 node of the QCS404
What about blsp2 bam?
>
> Signed-off-by: Vinod Koul
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 13 +
> 1 file changed, 1
On Mon 05 Nov 07:45 PST 2018, Vinod Koul wrote:
> RNG hardware in QCS404 features (Execution Environment) EE for
> HLOS to use, add the node for prng-ee for QCS404.
>
> Signed-off-by: Vinod Koul
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++
On Sun, 2018-11-04 at 11:06 +0100, Rafael J. Wysocki wrote:
> On Wednesday, October 31, 2018 7:36:21 PM CET Giovanni Gherdovich wrote:
>
> [...]
> You can use the cpu_idle trace point to correlate the selected state index
> with the observed idle duration (that's what Doug did IIUC).
True, that wo
On Mon 05 Nov 07:45 PST 2018, Vinod Koul wrote:
> From: Bjorn Andersson
>
> Add the TrustZone based remoteproc nodes and their glink edges for
> adsp, cdsp and wcss.
>
> Signed-off-by: Bjorn Andersson
> Signed-off-by: Vinod Koul
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 87
> ++
On Mon 05 Nov 07:45 PST 2018, Vinod Koul wrote:
> Add the GPIOs present on PMS405 chip.
>
> Signed-off-by: Vinod Koul
> ---
> arch/arm64/boot/dts/qcom/pms405.dtsi | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi
> b/arch/arm64/boo
201 - 300 of 726 matches
Mail list logo
