On Tue, 20 Nov 2018 11:55:21 +
wrote:
> +
> + /*
> + * We set nor->addr_width here to skip spi_nor_set_4byte_opcodes()
> + * later because this latest function implements a legacy quirk for
> + * the erase size of Spansion memory. However this quirk is no longer
> + *
On Tue, 20 Nov 2018 11:55:21 +
wrote:
> +
> + /*
> + * We set nor->addr_width here to skip spi_nor_set_4byte_opcodes()
> + * later because this latest function implements a legacy quirk for
> + * the erase size of Spansion memory. However this quirk is no longer
> + *
On 11/16/2018 2:38 PM, Jarkko Sakkinen wrote:
On Wed, Nov 14, 2018 at 04:31:03PM +0100, Roberto Sassu wrote:
tcg_efi_specid_event and tcg_pcr_event2 declaration contains static arrays
for a list of hash algorithms used for event logs and event log digests.
However, according to TCG EFI
On 11/16/2018 2:38 PM, Jarkko Sakkinen wrote:
On Wed, Nov 14, 2018 at 04:31:03PM +0100, Roberto Sassu wrote:
tcg_efi_specid_event and tcg_pcr_event2 declaration contains static arrays
for a list of hash algorithms used for event logs and event log digests.
However, according to TCG EFI
This patch adds a DT binding documentation for the MT7629 soc.
Signed-off-by: Leilk Liu
---
v3:
remove cover-letter.
v2:
remove "mediatek,mt7629-spi" compatible according Matthias's advice.
v1:
This series are based on 4.20-rc1 and provide two patches to support mt7629 IC.
---
This patch adds a DT binding documentation for the MT7629 soc.
Signed-off-by: Leilk Liu
---
v3:
remove cover-letter.
v2:
remove "mediatek,mt7629-spi" compatible according Matthias's advice.
v1:
This series are based on 4.20-rc1 and provide two patches to support mt7629 IC.
---
Ping?
Hi Tom,
This series, especially [09/12] tracing: Remove unneeded synth_event_mutex
will effect your current working series. Please tell me your opinion.
Thank you,
On Mon, 5 Nov 2018 17:59:46 +0900
Masami Hiramatsu wrote:
> Hi,
>
> This is v2 series of unifying dynamic event
Ping?
Hi Tom,
This series, especially [09/12] tracing: Remove unneeded synth_event_mutex
will effect your current working series. Please tell me your opinion.
Thank you,
On Mon, 5 Nov 2018 17:59:46 +0900
Masami Hiramatsu wrote:
> Hi,
>
> This is v2 series of unifying dynamic event
It`s possible ip overrun in lzo1x_1_do_compress() when compressed page is
point to the end of memory and which virtual address is 0xf000.
Leading to a NULL pointer access during the get_unaligned_le32(ip).
Fix this panic:
[ 2738.034508] Unable to handle kernel NULL pointer dereference
It`s possible ip overrun in lzo1x_1_do_compress() when compressed page is
point to the end of memory and which virtual address is 0xf000.
Leading to a NULL pointer access during the get_unaligned_le32(ip).
Fix this panic:
[ 2738.034508] Unable to handle kernel NULL pointer dereference
The Firefly-RK3399 DeviceTree
(`arch/arm64/boot/dts/rockchip/rk3399-firefly.dts`) defines a
`simple-audio-card` device which selects a `realtek,rt5640` codec.
This codec however is inaccessible in the kernel configuration
(`SND_SOC_RT5640`) and thus cannot be used.
This patch adds a new
The Firefly-RK3399 DeviceTree
(`arch/arm64/boot/dts/rockchip/rk3399-firefly.dts`) defines a
`simple-audio-card` device which selects a `realtek,rt5640` codec.
This codec however is inaccessible in the kernel configuration
(`SND_SOC_RT5640`) and thus cannot be used.
This patch adds a new
Add support to perf report annotate view or perf annotate --stdio2 to
aggregate the IPC derived from timed LBRs per symbol. We compute the
average IPC and the IPC coverage percentage.
For example,
$ perf annotate --stdio2
Percent IPC Cycle (Average IPC: 2.30, IPC Coverage: 54.8%)
Add support to perf report annotate view or perf annotate --stdio2 to
aggregate the IPC derived from timed LBRs per symbol. We compute the
average IPC and the IPC coverage percentage.
For example,
$ perf annotate --stdio2
Percent IPC Cycle (Average IPC: 2.30, IPC Coverage: 54.8%)
Support displaying the average IPC and IPC coverage per symbol
in perf report TUI and stdio modes.
For example,
$ perf record -b ...
$ perf report -s symbol
Overhead Symbol IPC [IPC Coverage]
39.60% [.] __random 2.30 [ 54.8%]
18.02% [.]
Support displaying the average IPC and IPC coverage per symbol
in perf report TUI and stdio modes.
For example,
$ perf record -b ...
$ perf report -s symbol
Overhead Symbol IPC [IPC Coverage]
39.60% [.] __random 2.30 [ 54.8%]
18.02% [.]
We often use the symbol__annotate2() to annotate a specified symbol.
While annotating may take some time, so in order to avoid annotating
the same symbol repeatedly, the patch creates a new flag to indicate
the symbol has been annotated.
Signed-off-by: Jin Yao
---
tools/perf/util/annotate.c | 1
Add supporting of displaying the average IPC and IPC coverage
percentage per function.
For example,
$ perf record -b ...
$ perf report -s symbol or
perf report -s symbol --stdio
Overhead Symbol IPC [IPC Coverage]
39.60% [.] __random 2.30 [
We often use the symbol__annotate2() to annotate a specified symbol.
While annotating may take some time, so in order to avoid annotating
the same symbol repeatedly, the patch creates a new flag to indicate
the symbol has been annotated.
Signed-off-by: Jin Yao
---
tools/perf/util/annotate.c | 1
Add supporting of displaying the average IPC and IPC coverage
percentage per function.
For example,
$ perf record -b ...
$ perf report -s symbol or
perf report -s symbol --stdio
Overhead Symbol IPC [IPC Coverage]
39.60% [.] __random 2.30 [
On Wed, Nov 28, 2018 at 08:55:26AM +0800, Pan Bian wrote:
> The function sis_find_family drops lpc_bridge reference via pci_dev_put,
> however, after that, field lpc_bridge->revision is read. This may result
> in a use after free bug. The patch moves the put operation after the
> condition check.
Looks good,
Reviewed-by: Christoph Hellwig
On Wed, Nov 28, 2018 at 08:55:26AM +0800, Pan Bian wrote:
> The function sis_find_family drops lpc_bridge reference via pci_dev_put,
> however, after that, field lpc_bridge->revision is read. This may result
> in a use after free bug. The patch moves the put operation after the
> condition check.
Looks good,
Reviewed-by: Christoph Hellwig
On Wed, Nov 28, 2018 at 06:32:27AM +, David CARLIER wrote:
> Bad entrance with bad idea I m afraid :-) sorry for the noise.
We all start somewhere, no worries :)
--
Cheers,
Joey Pabalinas
signature.asc
Description: PGP signature
On Wed, Nov 28, 2018 at 06:32:27AM +, David CARLIER wrote:
> Bad entrance with bad idea I m afraid :-) sorry for the noise.
We all start somewhere, no worries :)
--
Cheers,
Joey Pabalinas
signature.asc
Description: PGP signature
Quoting Bjorn Andersson (2018-11-21 23:30:43)
> On Wed 21 Nov 01:01 PST 2018, Stephen Boyd wrote:
>
> > Quoting Bjorn Andersson (2018-11-05 21:50:13)
> > > As of v4.20-rc1 probing the GCC driver on a SDM845 device with the
> > > standard security implementation causes an access violation and an
>
Quoting Bjorn Andersson (2018-11-21 23:30:43)
> On Wed 21 Nov 01:01 PST 2018, Stephen Boyd wrote:
>
> > Quoting Bjorn Andersson (2018-11-05 21:50:13)
> > > As of v4.20-rc1 probing the GCC driver on a SDM845 device with the
> > > standard security implementation causes an access violation and an
>
Bad entrance with bad idea I m afraid :-) sorry for the noise.
Bad entrance with bad idea I m afraid :-) sorry for the noise.
On Tue 27-11-18 14:50:05, Linus Torvalds wrote:
> On Tue, Nov 27, 2018 at 12:57 PM Andrea Arcangeli wrote:
> >
> > This difference can only happen with defrag=always, and that's not the
> > current upstream default.
>
> Ok, thanks. That makes it a bit less critical.
>
> > That MADV_HUGEPAGE
On Tue 27-11-18 14:50:05, Linus Torvalds wrote:
> On Tue, Nov 27, 2018 at 12:57 PM Andrea Arcangeli wrote:
> >
> > This difference can only happen with defrag=always, and that's not the
> > current upstream default.
>
> Ok, thanks. That makes it a bit less critical.
>
> > That MADV_HUGEPAGE
> >
> > Hrm, converting unconditionally with msleep() looks too drastic.
>
> Yes, it looks drastic. But, IMHO, I can't say busy-spin is not
non-drastic.
Fix typo in this comment:
I can't say busy-spin is not drastic.
Thanks
Chanho
> >
> > Hrm, converting unconditionally with msleep() looks too drastic.
>
> Yes, it looks drastic. But, IMHO, I can't say busy-spin is not
non-drastic.
Fix typo in this comment:
I can't say busy-spin is not drastic.
Thanks
Chanho
Hi Willy,
On 2018/11/28 12:08, Willy Tarreau wrote:
> Hi Yueyi,
>
> On Tue, Nov 27, 2018 at 10:34:26AM +, Yueyi Li wrote:
>> It`s possible ip overrun in lzo1x_1_do_compress() when compressed page is
>> point to the end of memory and which virtual address is 0xf000.
>> Leading to
Hi Willy,
On 2018/11/28 12:08, Willy Tarreau wrote:
> Hi Yueyi,
>
> On Tue, Nov 27, 2018 at 10:34:26AM +, Yueyi Li wrote:
>> It`s possible ip overrun in lzo1x_1_do_compress() when compressed page is
>> point to the end of memory and which virtual address is 0xf000.
>> Leading to
On Tue, 27 Nov 2018, Thomas Gleixner wrote:
> > Does it really have to?
> >
> > We need this special handling only if the next task has TIF_SPEC_UPDATE
> > set, which is one-off event globally (when seccomp marks all its threads
> > so due to seccomp filter change), and once all the
On Tue, 27 Nov 2018, Thomas Gleixner wrote:
> > Does it really have to?
> >
> > We need this special handling only if the next task has TIF_SPEC_UPDATE
> > set, which is one-off event globally (when seccomp marks all its threads
> > so due to seccomp filter change), and once all the
This patch enables CONFIG_IMX_SC_THERMAL as module.
Signed-off-by: Anson Huang
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index abd80c5..9f12324 100644
--- a/arch/arm64/configs/defconfig
+++
This patch enables CONFIG_IMX_SC_THERMAL as module.
Signed-off-by: Anson Huang
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index abd80c5..9f12324 100644
--- a/arch/arm64/configs/defconfig
+++
Add i.MX8QXP CPU thermal zone support.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index
Add i.MX8QXP CPU thermal zone support.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index
NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as
system controller, the system controller is in charge of system
power, clock and thermal sensors etc. management, Linux kernel
has to communicate with system controller via MU (message unit)
IPC to get temperature from thermal sensors,
NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as
system controller, the system controller is in charge of system
power, clock and thermal sensors etc. management, Linux kernel
has to communicate with system controller via MU (message unit)
IPC to get temperature from thermal sensors,
i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller
inside, the system controller is in charge of controlling power,
clock and thermal sensors etc..
This patch adds i.MX system controller thermal driver support,
Linux kernel has to communicate with system controller via MU
(message
i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller
inside, the system controller is in charge of controlling power,
clock and thermal sensors etc..
This patch adds i.MX system controller thermal driver support,
Linux kernel has to communicate with system controller via MU
(message
i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller
inside, the system controller is in charge of controlling power,
clock and thermal sensors etc..
This patch adds i.MX system controller thermal driver support,
Linux kernel has to communicate with system controller via MU
(message
i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller
inside, the system controller is in charge of controlling power,
clock and thermal sensors etc..
This patch adds i.MX system controller thermal driver support,
Linux kernel has to communicate with system controller via MU
(message
Hi Daniel,
I updated my patch to parse the sensor id, please take a look.
Wei.
On 28/11/2018 1:44 PM, Wei Ni wrote:
> Since different platforms may not support all 4
> sensors, so the sensor registration may be failed.
> Add codes to parse dt to find sensor id which
> need to be registered. So
Hi Daniel,
I updated my patch to parse the sensor id, please take a look.
Wei.
On 28/11/2018 1:44 PM, Wei Ni wrote:
> Since different platforms may not support all 4
> sensors, so the sensor registration may be failed.
> Add codes to parse dt to find sensor id which
> need to be registered. So
Since different platforms may not support all 4
sensors, so the sensor registration may be failed.
Add codes to parse dt to find sensor id which
need to be registered. So that the registration
can be successful on all platform.
Signed-off-by: Wei Ni
---
drivers/thermal/tegra/soctherm.c | 46
Fix memory allocation to store the pointers to
thermal_zone_device.
Signed-off-by: Wei Ni
Acked-by: Thierry Reding
---
drivers/thermal/tegra/soctherm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
index
Since different platforms may not support all 4
sensors, so the sensor registration may be failed.
Add codes to parse dt to find sensor id which
need to be registered. So that the registration
can be successful on all platform.
Signed-off-by: Wei Ni
---
drivers/thermal/tegra/soctherm.c | 46
Fix memory allocation to store the pointers to
thermal_zone_device.
Signed-off-by: Wei Ni
Acked-by: Thierry Reding
---
drivers/thermal/tegra/soctherm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
index
This series fixed some issues for Tegra soctherm
Main changes from v2:
1. add codes to parse sensor id to avoid registration
failure.
Main changes from v1:
1. Acked by Thierry Reding for the patch
"thermal: tegra: fix memory allocation".
2. Print out the sensor name when register failed.
2.
Convert warnings to info as not all platforms may
have all the thresholds and sensors enabled.
Signed-off-by: Wei Ni
---
drivers/thermal/tegra/soctherm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
This series fixed some issues for Tegra soctherm
Main changes from v2:
1. add codes to parse sensor id to avoid registration
failure.
Main changes from v1:
1. Acked by Thierry Reding for the patch
"thermal: tegra: fix memory allocation".
2. Print out the sensor name when register failed.
2.
Convert warnings to info as not all platforms may
have all the thresholds and sensors enabled.
Signed-off-by: Wei Ni
---
drivers/thermal/tegra/soctherm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
The Denali NAND IP has no way to read out the current signal level
of the R/B# pin. Instead, denali_dev_ready() checks if the R/B#
transition has already happened. (The INTR__INT_ACT interrupt is
asserted at the rising edge of the R/B# pin.) It is not a correct
way to implement the ->dev_ready()
I sent this series on September,
and Miquel replied this series was applied:
http://patchwork.ozlabs.org/patch/967242/
But, It turned out not applied.
I rebased it and resending now.
Masahiro Yamada (2):
mtd: rawnand: denali: remove ->dev_ready() hook
mtd: rawnand: denali: remove
The Denali NAND IP has no way to read out the current signal level
of the R/B# pin. Instead, denali_dev_ready() checks if the R/B#
transition has already happened. (The INTR__INT_ACT interrupt is
asserted at the rising edge of the R/B# pin.) It is not a correct
way to implement the ->dev_ready()
I sent this series on September,
and Miquel replied this series was applied:
http://patchwork.ozlabs.org/patch/967242/
But, It turned out not applied.
I rebased it and resending now.
Masahiro Yamada (2):
mtd: rawnand: denali: remove ->dev_ready() hook
mtd: rawnand: denali: remove
In nand_scan_ident(), the controller driver resets every NAND chip.
This is done by sending NAND_CMD_RESET. The Denali IP provides
another way to do the equivalent thing; if a bit is set in the
DEVICE_RESET register, the controller sends the RESET command to
the corresponding device.
In nand_scan_ident(), the controller driver resets every NAND chip.
This is done by sending NAND_CMD_RESET. The Denali IP provides
another way to do the equivalent thing; if a bit is set in the
DEVICE_RESET register, the controller sends the RESET command to
the corresponding device.
Hi all,
Changes since 20181127:
The vfs tree gained a conflict against the ext3 tree.
Non-merge commits (relative to Linus' tree): 5084
5241 files changed, 259238 insertions(+), 151877 deletions(-)
I have created
Hi all,
Changes since 20181127:
The vfs tree gained a conflict against the ext3 tree.
Non-merge commits (relative to Linus' tree): 5084
5241 files changed, 259238 insertions(+), 151877 deletions(-)
I have created
NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as
system controller, the system controller is in charge of system
power, clock and secure RTC etc. management, Linux kernel
has to communicate with system controller via MU (message unit)
IPC to do RTC operation.
Since the RTC set time
NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as
system controller, the system controller is in charge of system
power, clock and secure RTC etc. management, Linux kernel
has to communicate with system controller via MU (message unit)
IPC to do RTC operation, this patch adds binding
Add i.MX8QXP system controller RTC support.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 9155d45..ef57db6 100644
i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller
inside, the system controller is in charge of controlling power,
clock and secure rtc etc..
This patch adds i.MX system controller RTC driver support,
Linux kernel has to communicate with system controller via MU
(message unit) IPC
This patch enables CONFIG_RTC_DRV_IMX_SC as module by default.
Signed-off-by: Anson Huang
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6d224f7..e3df5dd 100644
---
NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as
system controller, the system controller is in charge of system
power, clock and secure RTC etc. management, Linux kernel
has to communicate with system controller via MU (message unit)
IPC to do RTC operation.
Since the RTC set time
NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as
system controller, the system controller is in charge of system
power, clock and secure RTC etc. management, Linux kernel
has to communicate with system controller via MU (message unit)
IPC to do RTC operation, this patch adds binding
Add i.MX8QXP system controller RTC support.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 9155d45..ef57db6 100644
i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller
inside, the system controller is in charge of controlling power,
clock and secure rtc etc..
This patch adds i.MX system controller RTC driver support,
Linux kernel has to communicate with system controller via MU
(message unit) IPC
This patch enables CONFIG_RTC_DRV_IMX_SC as module by default.
Signed-off-by: Anson Huang
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6d224f7..e3df5dd 100644
---
Hi Florian,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on gpio/for-next]
[also build test ERROR on v4.20-rc4 next-20181127]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
Hi Florian,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on gpio/for-next]
[also build test ERROR on v4.20-rc4 next-20181127]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
On Sat, Nov 24, 2018 at 08:45:34AM -0800, Jarkko Sakkinen wrote:
> On Fri, Nov 23, 2018 at 04:39:23AM -0600, Dr. Greg wrote:
> > Jarkko, when this driver lands it will set the SGX ABI in stone for
> > Linux. It would be very, very helpful to the development community if
> > there was some
On Sat, Nov 24, 2018 at 08:45:34AM -0800, Jarkko Sakkinen wrote:
> On Fri, Nov 23, 2018 at 04:39:23AM -0600, Dr. Greg wrote:
> > Jarkko, when this driver lands it will set the SGX ABI in stone for
> > Linux. It would be very, very helpful to the development community if
> > there was some
Kees Cook writes:
> On Tue, Nov 27, 2018 at 4:38 PM, Kees Cook wrote:
>> On Tue, Nov 27, 2018 at 3:21 PM, Tycho Andersen wrote:
>>> On Mon, Nov 12, 2018 at 12:24:43PM -0700, Tycho Andersen wrote:
On Mon, Nov 12, 2018 at 11:55:38AM -0700, Tycho Andersen wrote:
> I haven't manage to
Kees Cook writes:
> On Tue, Nov 27, 2018 at 4:38 PM, Kees Cook wrote:
>> On Tue, Nov 27, 2018 at 3:21 PM, Tycho Andersen wrote:
>>> On Mon, Nov 12, 2018 at 12:24:43PM -0700, Tycho Andersen wrote:
On Mon, Nov 12, 2018 at 11:55:38AM -0700, Tycho Andersen wrote:
> I haven't manage to
Hello Kees,
On 2018/11/28 6:38, Kees Cook wrote:
> On Thu, Nov 22, 2018 at 11:54 PM, Wang Dongsheng
> wrote:
>> When select ARCH_TASK_STRUCT_ON_STACK the first of thread_info variable
>> is overwritten by STACK_END_MAGIC. In fact, the ARCH_TASK_STRUCT_ON_STACK
>> is not a real task on stack,
Hi all,
On Tue, 27 Nov 2018 20:14:58 -0800 Randy Dunlap wrote:
>
> On 11/26/18 8:25 PM, Stephen Rothwell wrote:
> > Hi all,
> >
> > Changes since 20181126:
> >
>
> on i386:
>
> ERROR: "__udivdi3" [drivers/scsi/aha1542.ko] undefined!
>
> somewhere in aha1542_interrupt() according to
Hello Kees,
On 2018/11/28 6:38, Kees Cook wrote:
> On Thu, Nov 22, 2018 at 11:54 PM, Wang Dongsheng
> wrote:
>> When select ARCH_TASK_STRUCT_ON_STACK the first of thread_info variable
>> is overwritten by STACK_END_MAGIC. In fact, the ARCH_TASK_STRUCT_ON_STACK
>> is not a real task on stack,
Hi all,
On Tue, 27 Nov 2018 20:14:58 -0800 Randy Dunlap wrote:
>
> On 11/26/18 8:25 PM, Stephen Rothwell wrote:
> > Hi all,
> >
> > Changes since 20181126:
> >
>
> on i386:
>
> ERROR: "__udivdi3" [drivers/scsi/aha1542.ko] undefined!
>
> somewhere in aha1542_interrupt() according to
The driver now supports i.MX8MQ, so update bindings accordingly.
Cc: p.za...@pengutronix.de
Cc: Fabio Estevam
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Cc: linux-...@nxp.com
Cc:
Add bits and pieces needed to support IP block variant found on
i.MX8MQ SoCs.
Cc: p.za...@pengutronix.de
Cc: Fabio Estevam
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Cc: linux-...@nxp.com
In order to enable supporting i.MX8MQ with this driver, convert it to
expect variant specific bits to be passed via driver data.
Cc: p.za...@pengutronix.de
Cc: Fabio Estevam
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: Rob Herring
The driver now supports i.MX8MQ, so update bindings accordingly.
Cc: p.za...@pengutronix.de
Cc: Fabio Estevam
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Cc: linux-...@nxp.com
Cc:
Add bits and pieces needed to support IP block variant found on
i.MX8MQ SoCs.
Cc: p.za...@pengutronix.de
Cc: Fabio Estevam
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Cc: linux-...@nxp.com
In order to enable supporting i.MX8MQ with this driver, convert it to
expect variant specific bits to be passed via driver data.
Cc: p.za...@pengutronix.de
Cc: Fabio Estevam
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: Rob Herring
Everyone:
This patch contains changes I made in order to add support for i.MX8MQ
to reset-imx7.c in order to enable support of PCIE IP block on i.MX8MQ
SoCs (full tree can be found at [github-v1]).
NOTE: This patch depens on CONFIG_ARCH_IMX8MQ introduced in [imx8mq]
Feedback is welcome!
Everyone:
This patch contains changes I made in order to add support for i.MX8MQ
to reset-imx7.c in order to enable support of PCIE IP block on i.MX8MQ
SoCs (full tree can be found at [github-v1]).
NOTE: This patch depens on CONFIG_ARCH_IMX8MQ introduced in [imx8mq]
Feedback is welcome!
Hi,
> -Original Message-
> From: Alex Williamson
> Sent: Tuesday, November 27, 2018 9:39 PM
> To: Bjorn Helgaas
> Cc: Bharat Bhushan ; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org; bharatb.ya...@gmail.com; David Daney
> ; Jan Glauber ; Maik
> Broemme ; Chris Blake
>
>
In preparation to enabling -Wimplicit-fallthrough, mark switch cases
where we are expecting to fall through.
Signed-off-by: Gustavo A. R. Silva
---
drivers/scsi/lpfc/lpfc_nportdisc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/scsi/lpfc/lpfc_nportdisc.c
Hi,
> -Original Message-
> From: Alex Williamson
> Sent: Tuesday, November 27, 2018 9:39 PM
> To: Bjorn Helgaas
> Cc: Bharat Bhushan ; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org; bharatb.ya...@gmail.com; David Daney
> ; Jan Glauber ; Maik
> Broemme ; Chris Blake
>
>
In preparation to enabling -Wimplicit-fallthrough, mark switch cases
where we are expecting to fall through.
Signed-off-by: Gustavo A. R. Silva
---
drivers/scsi/lpfc/lpfc_nportdisc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/scsi/lpfc/lpfc_nportdisc.c
Hi,
On Thu, Nov 15, 2018 at 5:36 PM Chen-Yu Tsai wrote:
>
> Hi everyone,
>
> This is v2 of my Broadcom-based Bluetooth controllers on Allwinner SoC-
> based SBCs series.
>
> Changes since v1:
>
> - Collected tags
> - Re-organize dt binding clocks and clock-names properties
> - Simplify
Hi,
On Thu, Nov 15, 2018 at 5:36 PM Chen-Yu Tsai wrote:
>
> Hi everyone,
>
> This is v2 of my Broadcom-based Bluetooth controllers on Allwinner SoC-
> based SBCs series.
>
> Changes since v1:
>
> - Collected tags
> - Re-organize dt binding clocks and clock-names properties
> - Simplify
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