This patch avoids that sparse complains about a missing declaration for
the lock_classes array when building with CONFIG_DEBUG_LOCKDEP=n.
Cc: Peter Zijlstra
Cc: Waiman Long
Cc: Johannes Berg
Signed-off-by: Bart Van Assche
---
kernel/locking/lockdep.c | 3 +++
1 file changed, 3 insertions(+)
On Thu, 6 Dec 2018 11:20:31 -0800
Olof Johansson wrote:
> On Thu, Dec 6, 2018 at 2:26 AM David Abdurachmanov
> wrote:
> >
> > Noticed while building kernel-4.20.0-0.rc5.git2.1.fc30 for
> > Fedora 30/RISCV.
> >
> > [..]
> > BUILDSTDERR: arch/riscv/kernel/ftrace.c: In function
> > 'prepare_ftrace
This converts license boilerplate to SPDX identifier, and removes
unnecessary lines.
Signed-off-by: Kunihiko Hayashi
---
drivers/thermal/uniphier_thermal.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/thermal/uniphier_thermal.c
b/drivers/thermal/unip
On Thu, Dec 06, 2018 at 12:32:47PM +, Kieran Bingham wrote:
> My main initial idea for a libumlinux is to provide infrastructure such
> as our linked-lists and other kernel formatting so that we can take
> kernel code directly to userspace for test and debug (assuming that
> there are no hardwa
On Thu, Dec 06, 2018 at 04:34:54PM -0800, Daniel Colascione wrote:
> On Thu, Dec 6, 2018 at 4:31 PM Serge E. Hallyn wrote:
> >
> > On Fri, Dec 07, 2018 at 12:17:45AM +0100, Christian Brauner wrote:
> > > On Thu, Dec 06, 2018 at 11:39:48PM +0100, Christian Brauner wrote:
> > > > On Thu, Dec 06, 201
Hi all,
Today's linux-next merge of the jc_docs tree got a conflict in:
Documentation/filesystems/index.rst
between commit:
1b71a6809f96 ("fs-verity: add a documentation file")
from the fscrypt tree and commit:
7bbfd9ad8eb2 ("Documentation: convert path-lookup from markdown to
resturct
Add DT bindings for PCIe controller implemented in UniPhier SoCs when
configured in Root Complex (host) mode. This controller is based on
the DesignWare PCIe core.
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/uniphier-pcie.txt | 81 ++
This introduces specific glue layer for UniPhier platform to support
PCIe host controller that is based on the DesignWare PCIe core, and
this driver supports Root Complex (host) mode.
Signed-off-by: Kunihiko Hayashi
---
MAINTAINERS| 7 +
drivers/pci/controller/d
This series adds PCIe host controller driver for Socionext UniPhier SoCs.
This controller is based on the DesignWare PCIe core. This driver
supports LD20 and PXs3 SoCs.
v4: https://www.spinics.net/lists/linux-pci/msg78278.html
About legacy IRQ, it might be necessary to share common view from
keys
Use devm_regmap_add_irq_chip and clean up error path in probe.
Hence clean up the probe error path and the remove function.
Reported-by: Christian Hohnstaedt
Signed-off-by: Keerthy
---
Changes in v2:
* Cleaned up remove function as well.
drivers/mfd/tps65218.c | 18 +++---
1 fi
On Thu, 6 Dec 2018, Rob Herring wrote:
> On Wed, Nov 21, 2018 at 05:06:56PM -0800, Paul Walmsley wrote:
> >
> > For IP blocks that are generated from the public, open-source
> > sifive-blocks repository, describe the version numbering policy
> > that its maintainers intend to use, upon request
On Wed, Dec 5, 2018 at 5:43 PM Brendan Higgins
wrote:
>
> On Tue, Dec 4, 2018 at 5:41 AM Rob Herring wrote:
> >
> > On Mon, Dec 3, 2018 at 6:14 PM Brendan Higgins
> > wrote:
> > >
> > > On Thu, Nov 29, 2018 at 4:40 PM Randy Dunlap
> > > wrote:
> > > >
> > > > On 11/28/18 12:56 PM, Rob Herring
On Thu, Dec 6, 2018 at 4:31 PM Serge E. Hallyn wrote:
>
> On Fri, Dec 07, 2018 at 12:17:45AM +0100, Christian Brauner wrote:
> > On Thu, Dec 06, 2018 at 11:39:48PM +0100, Christian Brauner wrote:
> > > On Thu, Dec 06, 2018 at 03:46:53PM -0600, Eric W. Biederman wrote:
> > > > Christian Brauner wr
On Fri, Dec 07, 2018 at 12:17:45AM +0100, Christian Brauner wrote:
> On Thu, Dec 06, 2018 at 11:39:48PM +0100, Christian Brauner wrote:
> > On Thu, Dec 06, 2018 at 03:46:53PM -0600, Eric W. Biederman wrote:
> > > Christian Brauner writes:
> > >
> > > >> Your intention is to add the thread case to
On 12/7/2018 2:21 AM, Sebastian Reichel wrote:
Hi,
On Thu, Dec 06, 2018 at 11:07:44PM +0530, Keerthy wrote:
Use devm_regmap_add_irq_chip and clean up error path in probe.
Reported-by: Christian Hohnstaedt
Signed-off-by: Keerthy
---
Boot tested on am437x-gp-evm.
This is missing cleanup
On Thu, Dec 06, 2018 at 04:48:57PM -0700, Logan Gunthorpe wrote:
>
>
> On 2018-12-06 4:38 p.m., Dave Hansen wrote:
> > On 12/6/18 3:28 PM, Logan Gunthorpe wrote:
> >> I didn't think this was meant to describe actual real world performance
> >> between all of the links. If that's the case all of t
Could you please take a look at this bug and code review?
We are seeing more instances of this bug and found that reconnect_work
could hang as well, as can be seen from below stacktrace.
Workqueue: nvme-wq nvme_rdma_reconnect_ctrl_work [nvme_rdma]
Call Trace:
__schedule+0x2ab/0x880
schedule+0
On Thu, Dec 06, 2018 at 03:09:21PM -0800, Dave Hansen wrote:
> On 12/6/18 2:39 PM, Jerome Glisse wrote:
> > No if the 4 sockets are connect in a ring fashion ie:
> > Socket0 - Socket1
> >| |
> > Socket3 - Socket2
> >
> > Then you have 4 links:
> > link0: socket0
On Tue, Dec 04, 2018 at 08:37:30AM +0200, Kalle Valo wrote:
> Brian Norris writes:
>
> > Here's a v2 that combines both sets of strings in that way. I'm not
> > resending the other patches, since they were only related in concept
> > (since I was referring to debugfs for implementing the nl80211
Comparing the existing TX_BITRATE parsing code (in
mwifiex_parse_htinfo()) with the RX bitrate histograms in debugfs.c, it
appears that the rxpd_rate and rxpd_htinfo fields have the same format.
At least, they give reasonable results when I parse them this way.
So this patch adds support for RX_BI
This function converts some firmware-specific parameters into cfg80211
'rate_info' structures. It currently assumes it's dealing only with TX
bitrate, but the RX bitrate looks to be the same, so refactor this
function to be reusable.
Signed-off-by: Brian Norris
---
v2:
* no change - just split u
Hi,
On Wed, Dec 5, 2018 at 12:00 AM Taniya Das wrote:
>
> This adds the low pass audio clock controller node to sdm845 based on
> the example in the bindings.
>
> Signed-off-by: Taniya Das
> ---
> arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 4 +++-
> arch/arm64/boot/dts/qcom/sdm845.dtsi| 8 ++
On Wed, Nov 21, 2018 at 05:06:56PM -0800, Paul Walmsley wrote:
>
> For IP blocks that are generated from the public, open-source
> sifive-blocks repository, describe the version numbering policy
> that its maintainers intend to use, upon request from Rob
> Herring .
>
> Cc: Rob Herring
> Cc: Pal
On Thu 06 Dec 10:45 PST 2018, Evan Green wrote:
> Enable support for one of the micro SD slots on the MTP.
>
> Signed-off-by: Evan Green
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
>
> Changes in v2:
> - Fixed alphabetization of node placement in sdm845-mtp.dtsi (Doug)
> - Fixed car
On Thu 06 Dec 10:45 PST 2018, Evan Green wrote:
> Add one of the two SD controllers to SDM845.
>
> Signed-off-by: Evan Green
> Reviewed-by: Douglas Anderson
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
>
> Changes in v2:
> - Reworded commit message to note that there are multiple SD
Commit f149b3155744 ("signal: Never allocate siginfo for SIGKILL or SIGSTOP")
means that the seccomp selftest cannot check si_pid under SIGSTOP anymore.
Since it's believed[1] there are no other userspace things depending on the
old behavior, this removes the behavioral check in the selftest, since
On 2018-12-06 4:38 p.m., Dave Hansen wrote:
> On 12/6/18 3:28 PM, Logan Gunthorpe wrote:
>> I didn't think this was meant to describe actual real world performance
>> between all of the links. If that's the case all of this seems like a
>> pipe dream to me.
>
> The HMAT discussions (that I was
The intent of invoking configfs_depend_item in commit 7474f52a82d51
("tcm_qla2xxx: Perform configfs depend/undepend for base_tpg")
was to prevent a physical Fibre Channel port removal when
virtual (NPIV) ports announced through that physical port are active.
The change does not work as expected: it
On Thu, 6 Dec 2018, Michal Hocko wrote:
> MADV_HUGEPAGE changes the picture because the caller expressed a need
> for THP and is willing to go extra mile to get it. That involves
> allocation latency and as of now also a potential remote access. We do
> not have complete agreement on the later but
On Wed, Nov 21, 2018 at 08:48:00AM +, eugen.hris...@microchip.com wrote:
> From: Cristian Birsan
>
> PDA 91-00156-A0 5.0 is a 5.0" WVGA TFT LCD panel.
> This panel with backlight is found in PDA 5" LCD screen (TM5000 series or
> AC320005-5).
> Adding Device Tree bindings for this panel.
>
>
From: Mian Yousaf Kaukab
Add is_meltdown_safe() which is a whitelist of known safe cores.
Signed-off-by: Mian Yousaf Kaukab
[Moved location of function]
Signed-off-by: Jeremy Linton
---
arch/arm64/kernel/cpufeature.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
dif
On Wed, 21 Nov 2018 08:47:57 +, wrote:
> Precision Design Associates, Inc. (PDA) manufactures standard and custom
> capacitive touch screens, LCD's embedded controllers and custom embedded
> software. They specialize in industrial, rugged and outdoor applications.
> Website: http://www.pdaatl.
Add a simple state machine which will track whether
all the online cores in a machine are vulnerable.
Once that is done we have a fairly authoritative view
of the machine vulnerability, which allows us to make a
judgment about machine safety if it hasn't been mitigated.
Signed-off-by: Jeremy Lint
From: Mian Yousaf Kaukab
spectre v1, has been mitigated, and the mitigation is
always active.
Signed-off-by: Mian Yousaf Kaukab
Signed-off-by: Jeremy Linton
---
arch/arm64/kernel/cpu_errata.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch
Add code to track whether all the cores in the machine are
vulnerable, and whether all the vulnerable cores have been
mitigated.
Once we have that information we can add the sysfs stub and
provide an accurate view of what is known about the machine.
Signed-off-by: Jeremy Linton
---
arch/arm64/k
Hi,
On Thu, Dec 6, 2018 at 10:46 AM Evan Green wrote:
>
> Enable support for one of the micro SD slots on the MTP.
>
> Signed-off-by: Evan Green
> ---
>
> Changes in v2:
> - Fixed alphabetization of node placement in sdm845-mtp.dtsi (Doug)
> - Fixed card detect name to match schematics (Doug).
From: Mian Yousaf Kaukab
Return status based no ssbd_state and the arm64 SSBS feature.
Return string "Unknown" in case CONFIG_ARM64_SSBD is
disabled or arch workaround2 is not available
in the firmware.
Signed-off-by: Mian Yousaf Kaukab
[Added SSBS logic]
Signed-off-by: Jeremy Linton
---
arch
From: Mian Yousaf Kaukab
Enable CPU vulnerabilty show functions for spectre_v1, spectre_v2,
meltdown and store-bypass.
Signed-off-by: Mian Yousaf Kaukab
Signed-off-by: Jeremy Linton
---
arch/arm64/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kcon
Part of this series was originally by Mian Yousaf Kaukab.
Arm64 machines should be displaying a human readable
vulnerability status to speculative execution attacks in
/sys/devices/system/cpu/vulnerabilities
This series enables that behavior by providing the expected
functions. Those functions e
On Wed, 5 Dec 2018, Linus Torvalds wrote:
> > Ok, I've applied David's latest patch.
> >
> > I'm not at all objecting to tweaking this further, I just didn't want
> > to have this regression stand.
>
> Hmm. Can somebody (David?) also perhaps try to state what the
> different latency impacts end u
On Wednesday, December 5, 2018 3:33:03 PM CET Borislav Petkov wrote:
> On Wed, Dec 05, 2018 at 01:15:10PM +0100, Rafael J. Wysocki wrote:
> > After commit
> >
> > commit 4cd24de3a0980bf3100c9dcb08ef65ca7c31af48
> > Author: Zhenzhong Duan
> > Date: Fri Nov 2 01:45:41 2018 -0700
> >
> > x86/
On Thu, Dec 6, 2018 at 3:34 PM Doug Anderson wrote:
>
> Hi,
> On Thu, Dec 6, 2018 at 10:45 AM Evan Green wrote:
> >
> > In sdhci-msm-v5 and beyond, the MCI registers are removed, so there is only
> > one register region required.
> >
> > Signed-off-by: Evan Green
> > ---
> >
> > Changes in v2: N
On 12/6/18 3:28 PM, Logan Gunthorpe wrote:
> I didn't think this was meant to describe actual real world performance
> between all of the links. If that's the case all of this seems like a
> pipe dream to me.
The HMAT discussions (that I was a part of at least) settled on just
trying to describe w
On 06/12/2018 23:30, Paolo Bonzini wrote:
> On 07/12/18 00:11, Boris Ostrovsky wrote:
>> On 12/6/18 5:49 PM, Paolo Bonzini wrote:
>>> On 06/12/18 23:34, Boris Ostrovsky wrote:
On 12/6/18 5:11 PM, Paolo Bonzini wrote:
> and also
>
> depends on !EFI
>
> because even th
Hi,
On Thu, Dec 6, 2018 at 10:45 AM Evan Green wrote:
>
> In sdhci-msm-v5 and beyond, the MCI registers are removed, so there is only
> one register region required.
>
> Signed-off-by: Evan Green
> ---
>
> Changes in v2: None
>
> Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 2 +-
> 1 fi
On 12/6/18 3:28 PM, Logan Gunthorpe wrote:
> These patches are really tied to world view #1. But, the HMAT is really
> tied to world view #1.
Whoops, should have been "the HMAT is really tied to world view #2"
On Wed, Dec 5, 2018 at 8:32 PM Shawn Guo wrote:
>
> On Mon, Dec 03, 2018 at 03:32:07PM -0600, Rob Herring wrote:
> > Convert Freescale SoC bindings to DT schema format using json-schema.
> >
> > Cc: Shawn Guo
> > Cc: Mark Rutland
> > Cc: devicet...@vger.kernel.org
> > Signed-off-by: Rob Herring
Add register regions for the second lane of dual-lane nodes.
This additional specification is needed so that the driver can stop
reaching beyond the tx and rx register allocations to get at the
second lane registers in a dual-lane PHY.
While in there, document #clock-cells as optional for PHYs tha
From: Can Guo
Enable the UFS host controller and PHY on sdm845-mtp.
Signed-off-by: Can Guo
Signed-off-by: Evan Green
Reviewed-by: Vivek Gautam
Reviewed-by: Douglas Anderson
---
Changes in v6:
- Fix renamed nodes in MTP (Bjorn)
Changes in v5: None
Changes in v4: None
Changes in v3: None
Ch
Update the device tree bindings for the QMP PHY to properly
specify the registers for dual-lane PHYs. Update the driver to use
those new registers. Add the DT nodes for UFS on SDM845 and MTP.
Finally, fix up the USB3 PHY on SDM845, which also has a dual-lane phy
Andy/Kishon,
Just a heads up that t
Utilize the newly fixed up DT bindings to get the tx2 and rx2 register
regions for the second lane of dual-lane PHYs. Before this change,
the driver was simply using lane one's register region and adding
0x400, which reached well beyond the DT-specified register
allocation. This would have been a c
Add the second lane registers for the USB PHY, now that the
QMP phy bindings have been updated. This way the driver can stop
reaching beyond its register region to get at the second lane.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
Reviewed-by: Bjorn Andersson
---
Changes in v6: No
Add the UFS controller and PHY to SDM845.
Signed-off-by: Evan Green
Signed-off-by: Douglas Anderson
Reviewed-by: Bjorn Andersson
---
As Doug mentioned in v2, this should land after (or with) the driver fix
in this series.
Changes in v6:
- Removed resets and reset-names (Bjorn)
- Renamed nodes
On 07/12/18 00:11, Boris Ostrovsky wrote:
> On 12/6/18 5:49 PM, Paolo Bonzini wrote:
>> On 06/12/18 23:34, Boris Ostrovsky wrote:
>>> On 12/6/18 5:11 PM, Paolo Bonzini wrote:
>>>
and also
depends on !EFI
because even though in principle it would be possible to write a PV
On 2018-12-06 4:09 p.m., Dave Hansen wrote:
> This looks great. But, we don't _have_ this kind of information for any
> system that I know about or any system available in the near future.
>
> We basically have two different world views:
> 1. The system is described point-to-point. A connects
Hi Robert,
On Fri, Dec 7, 2018 at 12:13 AM Robert Abel wrote:
>
> Hi Miguel,
>
> On 05 Dec 2018 17:47, Miguel Ojeda wrote:> Hi Mans,
> >
> > [CC'ing a few people involved previously on this]
>
> Thanks for CC'ing me!
>
> On 06 Dec 2018 11:06, Miguel Ojeda wrote [to Mans Rullgard]:
> > Are you abl
On Thu, Dec 06, 2018 at 11:39:48PM +0100, Christian Brauner wrote:
> On Thu, Dec 06, 2018 at 03:46:53PM -0600, Eric W. Biederman wrote:
> > Christian Brauner writes:
> >
> > >> Your intention is to add the thread case to support pthreads once the
> > >> process case is sorted out. So this is som
Hi Miguel,
On 05 Dec 2018 17:47, Miguel Ojeda wrote:> Hi Mans,
>
> [CC'ing a few people involved previously on this]
Thanks for CC'ing me!
On 06 Dec 2018 11:06, Miguel Ojeda wrote [to Mans Rullgard]:
> Are you able to test this?
It's unfortunate that my original comment got ignored back when th
On Thu, 6 Dec 2018, Marc Zyngier wrote:
> On 05/12/2018 21:31, Linus Walleij wrote:
> > On Thu, Nov 29, 2018 at 6:03 PM Thierry Reding
> > wrote:
> >
> >> From: Thierry Reding
> >>
> >> Interrupt controllers in a hierarchy want to use this function to
> >> propogate ->irq_set_wake() operations
On 12/6/18 5:49 PM, Paolo Bonzini wrote:
> On 06/12/18 23:34, Boris Ostrovsky wrote:
>> On 12/6/18 5:11 PM, Paolo Bonzini wrote:
>>
>>> and also
>>>
>>> depends on !EFI
>>>
>>> because even though in principle it would be possible to write a PVH
>>> loader for UEFI, PVH's start info does not su
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can spend the rest of my life with, someone who is loving, caring, honest and
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Hi Minas,
I tried your new patch on top of the other 2 patches for a couple of days now
and I do not see the issue that Marek encountered. Of course, I did not see it
also on the original two patches you created. I also do not see the original
FIFO map warning issue that I have with all 3 patch
On 12/6/18 2:39 PM, Jerome Glisse wrote:
> No if the 4 sockets are connect in a ring fashion ie:
> Socket0 - Socket1
>| |
> Socket3 - Socket2
>
> Then you have 4 links:
> link0: socket0 socket1
> link1: socket1 socket2
> link3: socket2 socket3
> link4: socket3 s
On Sun, Nov 25, 2018 at 08:45:00PM +0530, Nayna Jain wrote:
> On secure boot enabled systems, the bootloader verifies the kernel
> image and possibly the initramfs signatures based on a set of keys. A
> soft reboot(kexec) of the system, with the same kernel image and
> initramfs, requires access to
Hi Rob,
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Wednesday, December 05, 2018 2:21 PM
> To: Jolly Shah
> Cc: mark.rutl...@arm.com; devicet...@vger.kernel.org; Nava kishore Manne
> ; linux-kernel@vger.kernel.org; Rajan Vaja
> ; Michal Simek ; linux-arm-
> k
> On Dec 6, 2018, at 12:17 PM, Andy Lutomirski wrote:
>
> On Thu, Dec 6, 2018 at 11:39 AM Nadav Amit wrote:
>>> On Dec 6, 2018, at 11:19 AM, Andy Lutomirski wrote:
>>>
>>> On Thu, Dec 6, 2018 at 11:01 AM Tycho Andersen wrote:
On Thu, Dec 06, 2018 at 10:53:50AM -0800, Andy Lutomirski wrot
Hi Arnd,
On Thu, 6 Dec 2018 23:09:01 +0100 Arnd Bergmann wrote:
>
> On Thu, Dec 6, 2018 at 9:12 PM Stephen Rothwell wrote:
> >
> > The y2038 tree contains a merge of next-20181206. I cannot use a tree
> > that includes a version of linux-next. I assume that this was j
From: Kan Liang
When a task, which is sampled by a PEBS event with a fixed period, is
sched_in, the fixed period will always be used as new period for
counter. It's inaccurate, because the left period from last sched_out
isn't taken into account.
The auto-reload feature is implicitly enabled for
Hi all,
Today's linux-next merge of the risc-v tree got a conflict in:
Documentation/features/io/sg-chain/arch-support.txt
between commit:
7c703e54cc71 ("arch: switch the default on ARCH_HAS_SG_CHAIN")
from the dma-mapping tree and commits:
1df4d3866118 ("doc: features-refresh.sh for cs
On Thu, Dec 6, 2018 at 2:43 PM Eric W. Biederman wrote:
>
> Kees Cook writes:
> > What should we do for v4.20? I need to have the selftests actually
> > passing. :)
>
> For v4.20 we need to do one of two things.
> 1) Present a plausible case that someone will could care about,
>we document it
On Wed, Dec 05, 2018 at 10:42:21AM +1000, Peter Hutterer wrote:
> This event code represents scroll reports from high-resolution wheels and
> is modelled after the approach Windows uses. The value 120 is one detent
> (wheel click) of movement. Mice with higher-resolution scrolling can send
> fracti
On Fri, Dec 07, 2018 at 08:46:05AM +1000, Peter Hutterer wrote:
> On Thu, Dec 06, 2018 at 10:24:11AM +0100, Benjamin Tissoires wrote:
> > On Thu, Dec 6, 2018 at 9:36 AM Martin Kepplinger
> > wrote:
> > >
> > > On 06.12.18 00:03, Peter Hutterer wrote:
> > > > ABS_RESERVED was added in d9ca1c990a7 a
On Thu, Dec 06, 2018 at 10:24:11AM +0100, Benjamin Tissoires wrote:
> On Thu, Dec 6, 2018 at 9:36 AM Martin Kepplinger
> wrote:
> >
> > On 06.12.18 00:03, Peter Hutterer wrote:
> > > ABS_RESERVED was added in d9ca1c990a7 and accidentally removed as part of
> > > ffe0e7cf290f5c9 when the high-resol
On Thu, Dec 06, 2018 at 06:29:20PM -0300, Arnaldo Carvalho de Melo wrote:
> Em Thu, Dec 06, 2018 at 12:51:48PM -0800, Andi Kleen escreveu:
> > On Thu, Dec 06, 2018 at 02:01:40PM -0300, Arnaldo Carvalho de Melo wrote:
> > > Em Mon, Nov 19, 2018 at 09:06:17PM -0800, Andi Kleen escreveu:
> > > > From:
On Thu, Dec 6, 2018 at 2:19 PM Sean Christopherson
wrote:
>
+
> + /*
> +* Invoke the caller's exit handler if one was provided. The return
> +* value tells us whether to re-enter the enclave (EENTER or ERESUME)
> +* or to return (EEXIT).
> +*/
> + if (
On 06/12/18 23:34, Boris Ostrovsky wrote:
> On 12/6/18 5:11 PM, Paolo Bonzini wrote:
>> On 06/12/18 07:04, Maran Wilson wrote:
>>> +config PVH
>>> + bool "Support for running PVH guests"
>>> + ---help---
>>> + This option enables the PVH entry point for guest virtual machines
>>> + as s
Hi all,
Commit
d569b5efedfd ("dm flakey: Properly corrupt multi-page bios.")
is missing a Signed-off-by from its author.
--
Cheers,
Stephen Rothwell
pgpwh3Rpn5zR_.pgp
Description: OpenPGP digital signature
On Thu, Dec 6, 2018 at 2:22 PM Eric W. Biederman wrote:
>
> Daniel Colascione writes:
>
> > On Thu, Dec 6, 2018 at 12:29 PM Eric W. Biederman
> > wrote:
> >> Christian Brauner writes:
> >>
> >> > [1]: You cannot replicate certain aspects of kill *yet*. We have
> >> > established this before. I
Kees Cook writes:
> On Thu, Dec 6, 2018 at 1:11 PM Eric W. Biederman
> wrote:
>>
>> Tycho Andersen writes:
>>
>> > On Thu, Dec 06, 2018 at 10:48:39AM -0800, Linus Torvalds wrote:
>> >> On Thu, Dec 6, 2018 at 6:40 AM Eric W. Biederman
>> >> wrote:
>> >> >
>> >> > We have in the past had ptrac
On Thu, Dec 06, 2018 at 03:46:53PM -0600, Eric W. Biederman wrote:
> Christian Brauner writes:
>
> >> Your intention is to add the thread case to support pthreads once the
> >> process case is sorted out. So this is something that needs to be made
> >> clear. Did I miss how you plan to handle t
On Thu, Dec 06, 2018 at 02:04:46PM -0800, Dave Hansen wrote:
> On 12/6/18 12:11 PM, Logan Gunthorpe wrote:
> >> My concern with having folks do per-program parsing, *and* having a huge
> >> amount of data to parse makes it unusable. The largest systems will
> >> literally have hundreds of thousand
On Tue, Dec 4, 2018 at 2:50 AM Thierry Reding wrote:
>
> On Mon, Dec 03, 2018 at 03:32:19PM -0600, Rob Herring wrote:
> > Convert Tegra SoC bindings to DT schema format using json-schema.
> >
> > Cc: Mark Rutland
> > Cc: Thierry Reding
> > Cc: Jonathan Hunter
> > Cc: devicet...@vger.kernel.org
On 12/6/18 5:11 PM, Paolo Bonzini wrote:
> On 06/12/18 07:04, Maran Wilson wrote:
>> +config PVH
>> +bool "Support for running PVH guests"
>> +---help---
>> + This option enables the PVH entry point for guest virtual machines
>> + as specified in the x86/HVM direct boot ABI.
>> +
On Thu, Dec 06, 2018 at 10:30:40AM -0800, Kees Cook wrote:
> On Thu, Dec 6, 2018 at 9:41 AM Christian Brauner wrote:
> > I feel changing the name around by a single persons preferences is not
> > really a nice thing to do community-wise. So I'd like to hear other
> > people chime in first before I
ret is assigned later, no need to initialize it.
Signed-off-by: Ladislav Michl
---
CHANGES:
-v2: add missing Signed-off-by
(I'm sorry for that...)
sound/soc/codecs/max9867.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/sound/soc/codecs/max9867.c b/sound/soc/codec
Jeff Moyer writes:
> Matthew Wilcox writes:
>
>> This custom resizing array was vulnerable to a Spectre attack (speculating
>> off the end of an array to a user-controlled offset). The XArray is
>> not vulnerable to Spectre as it always masks its lookups to be within
>> the bounds of the array.
On Tue, Dec 04, 2018 at 02:49:31PM -0800, Andrew Morton wrote:
> On Fri, 30 Nov 2018 14:58:08 -0500 Josef Bacik wrote:
>
> > Now that we have proper isolation in place with cgroups2 we have started
> > going
> > through and fixing the various priority inversions. Most are all gone now,
> > but
The LLVM/Clang project provides many tools for analyzing C source code.
Many of these tools are based on LibTooling
(https://clang.llvm.org/docs/LibTooling.html), which depends on a
database of compiler flags. The standard container for this database is
compile_commands.json, which consists of a li
At the end of regulator_resolve_supply() we have historically turned
on our supply in some cases. This could be for one of two reasons:
1. If resolving supplies was happening before the call to
set_machine_constraints() we needed to predict if
set_machine_constraints() was going to turn the
Daniel Colascione writes:
> On Thu, Dec 6, 2018 at 12:29 PM Eric W. Biederman
> wrote:
>> Christian Brauner writes:
>>
>> > [1]: You cannot replicate certain aspects of kill *yet*. We have
>> > established this before. If we want process group support later we do
>> > have the flags argument t
Matthew Wilcox writes:
> This custom resizing array was vulnerable to a Spectre attack (speculating
> off the end of an array to a user-controlled offset). The XArray is
> not vulnerable to Spectre as it always masks its lookups to be within
> the bounds of the array.
I'm not a big fan of compl
This version is almost entirely about the vDSO function itself,
i.e. patch 4/4. Feel free to ignore patches 2/4 and 3/4, I need
to do (a lot) more legwork to address feedback and improve their
changelogs. I'm expecting that to take a fair amount of time and
wanted to get the alternative exit hand
Call fixup_vdso_exception() in the SIGSEGV and SIGBUS paths of the
page fault handler immediately prior to signaling. If the fault is
fixed, return cleanly and do not generate a signal.
The goal of vDSO fixup is not to fixup all faults, nor is it to avoid
all signals, but rather to report faults
The basic concept and implementation is very similar to the kernel's
exception fixup mechanism. The key differences are that the kernel
handler is hardcoded and the fixup entry addresses are relative to
the overall table as opposed to individual entries.
Hardcoding the kernel handler avoids the n
Call fixup_vdso_exception() in all trap flows that generate signals to
userspace immediately prior to generating any such signal. If the
exception is fixed, return cleanly and do not generate a signal.
The goal of vDSO fixup is not to fixup all faults, nor is it to avoid
all signals, but rather t
Intel Software Guard Extensions (SGX) SGX introduces a new CPL3-only
enclave mode that runs as a sort of black box shared object that is
hosted by an untrusted normal CPL3 process.
Enclave transitions have semantics that are a lovely blend of SYCALL,
SYSRET and VM-Exit. In a non-faulting scenario
Hi all,
Today's linux-next merge of the arm64 tree got a conflict in:
arch/arm64/kernel/cpu_errata.c
between commit:
ce8c80c536da ("arm64: Add workaround for Cortex-A76 erratum 1286807")
from Linus' tree and commit:
c9460dcb06ee ("arm64: capabilities: Merge entries for
ARM64_WORKAROUND
On 2018-12-06 1:46 p.m., Bjorn Helgaas wrote:
> On Fri, Nov 30, 2018 at 03:59:11PM -0700, Logan Gunthorpe wrote:
>> "mm-hmm-mark-hmm_devmem_add-add_resource-export_symbol_gpl.patch" in the
>> mm tree breaks p2pdma. The patch was written and reviewed before p2pdma
>> was merged so the necessary c
On Thu, 6 Dec 2018 13:54:57 -0800
Andrew Morton wrote:
> > Acked-by: Oleg Nesterov
> > Reviewed-by: Srikar Dronamraju
> > Reported-by: syzbot+cb1fb754b771caca0...@syzkaller.appspotmail.com
> > Fixes: 1cc33161a83d ("uprobes: Support SDT markers having reference
> > co
On 06/12/18 22:58, Boris Ostrovsky wrote:
> On 12/6/18 4:37 PM, Borislav Petkov wrote:
>> On Thu, Dec 06, 2018 at 10:21:12PM +0100, Paolo Bonzini wrote:
>>> Thanks! I should be able to post a Tested-by next Monday. Boris, are
>>> you going to pick it up for 4.21?
>> Boris me or Boris O.?
>>
>> :-
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