Hi Geert,
The below patch comes about from the build regressions and improvements
list you've sent out, but something doesn't add up that we'd be testing
with an old compiler where initialization with { 0 } generates a
"missing braces around initialization" warning. Is this really the
case or
姜智伟 writes:
> Will do, thanks!
Also don't send HTML mail :) Maillists drop those automatically.
--
Kalle Valo
Hi Viresh,
On Fri, 18 Jan 2019 11:08:02 +0530 Viresh Kumar wrote:
>
> I missed looking into that. You must be running some sort of sanity
> checks on the branch itself, can I know what exactly are you doing so
> that I can try the same.
I have attached my current script. I run this on the
On Wed, Jan 23, 2019 at 01:03:46AM +0800, Tiwei Bie wrote:
> This patch introduces the support for VIRTIO_F_ORDER_PLATFORM.
> When this feature is negotiated, driver will use the barriers
> suitable for hardware devices.
>
> Signed-off-by: Tiwei Bie
Could you pls add a bit more explanation in
On 1/22/19 9:08 PM, Kirill A. Shutemov wrote:
> On Tue, Jan 22, 2019 at 03:31:25PM +0800, Cao jin wrote:
>> Hi, Kirll,
>>
>>> 2.
>>> Why gdt64 has following definition?:
>>>
>>> gdt64:
>>> .word gdt_end - gdt
>>> .long 0
>>> .word 0
>>> .quad 0
>>>
>>> obviously, gdt64
On Wed, Jan 23, 2019 at 11:08:04AM +0800, Jason Wang wrote:
>
> On 2019/1/23 上午1:03, Tiwei Bie wrote:
> > This patch introduces the support for VIRTIO_F_ORDER_PLATFORM.
> > When this feature is negotiated, driver will use the barriers
> > suitable for hardware devices.
> >
> > Signed-off-by:
Some of the statistics counts are for PV qspinlocks only and are not
applicable if PARAVIRT_SPINLOCKS aren't configured. So make those counts
dependent on the PARAVIRT_SPINLOCKS config option now.
Signed-off-by: Waiman Long
---
kernel/locking/qspinlock_stat.h | 129
v2:
- Use the simple trylock loop as suggested by PeterZ.
The current allows up to 4 levels of nested slowpath spinlock calls.
That should be enough for the process, soft irq, hard irq, and nmi.
With the unfortunate event of nested NMIs happening with slowpath
spinlock call in each of the
The QUEUED_LOCK_STAT option to report queued spinlocks statistics was
previously allowed only on x86 architecture. Now queued spinlocks are
used in multiple architectures, we now allow QUEUED_LOCK_STAT to be
enabled for all those architectures that use queued spinlocks. This
option is listed as
Track the number of slowpath locking operations that are being done
without any MCS node available as well renaming lock_index[123] to make
them more descriptive.
Using these stat counters is one way to find out if a code path is
being exercised.
Signed-off-by: Waiman Long
---
Four queue nodes per cpu are allocated to enable up to 4 nesting levels
using the per-cpu nodes. Nested NMIs are possible in some architectures.
Still it is very unlikely that we will ever hit more than 4 nested
levels with contention in the slowpath.
When that rare condition happens, however, it
On Mon, 14 Jan 2019, Mathieu Malaterre wrote:
> There is a plan to build the kernel with -Wimplicit-fallthrough and
> this place in the code produced a warning (W=1).
>
> In this particular case change put the fall through comment on a single
> line so as to match the regular expression expected
The interconnect framework is designed to provide a
standard kernel interface to control the settings of
the interconnects on a SoC.
The interconnect API uses a consumer/provider-based model,
where the providers are the interconnect buses and the
consumers could be various drivers.
MDSS is one
On Tue, 2019-01-22 at 21:41 -0500, Martin K. Petersen wrote:
> Ching,
>
> > This patch series are against to mkp's 5.1/scsi-queue.
>
> Applied to 5.1/scsi-queue. Thank you.
>
> PS. Your file permissions are odd. I always have to change your diffs
> from 755 to 644 before applying.
>
Thanks
Add interconnect properties such as interconnect provider specifier
, the edge source and destination ports which are required by the
interconnect API to configure interconnect path for MDSS.
Changes in v2:
- none
Changes in v3:
- Remove common property definitions (Rob Herring)
The interconnect API provides an interface for consumer drivers to express
their bandwidth needs in the SoC. This data is aggregated and the on-chip
interconnect hardware is configured to the appropriate power/performance
profile.
MDSS is one of the interconnect consumers which uses the
Since the upstream interconnect bus framework has landed
upstream, the existing references of custom bus scaling
needs to be cleaned up.
Changes in v2:
- Fixed build error due to partial clean up
Changes in v3:
- Condense multiple lines into a single line (Sean Paul)
Changes in
On Jan 22, 2019, at 8:13 PM, He Zhe wrote:
>
>
> LTP case read_all_proc(read_all -d /proc -q -r 10) often, but not every time,
> fails with the following call traces, since 600335205b8d "ide: convert to
> blk-mq"(5.0-rc1) till now(5.0-rc3).
>
> qemu-system-x86_64 -drive
The interconnect framework is designed to provide a
standard kernel interface to control the settings of
the interconnects on a SoC.
The interconnect API uses a consumer/provider-based model,
where the providers are the interconnect buses and the
consumers could be various drivers.
MDSS is one
Since the upstream interconnect bus framework has landed
upstream, the existing references of custom bus scaling
needs to be cleaned up.
Changes in v2:
- Fixed build error due to partial clean up
Changes in v3:
- Condense multiple lines into a single line (Sean Paul)
Changes in
Add interconnect properties such as interconnect provider specifier
, the edge source and destination ports which are required by the
interconnect API to configure interconnect path for MDSS.
Changes in v2:
- none
Changes in v3:
- Remove common property definitions (Rob Herring)
The interconnect API provides an interface for consumer drivers to express
their bandwidth needs in the SoC. This data is aggregated and the on-chip
interconnect hardware is configured to the appropriate power/performance
profile.
MDSS is one of the interconnect consumers which uses the
On Tue, Jan 22, 2019 at 04:42:19PM +0800, Su Yue wrote:
> Thanks for your quick reply! Paul
>
> On 1/22/19 12:01 PM, Paul E. McKenney wrote:
> >On Tue, Jan 22, 2019 at 11:40:53AM +0800, Su Yue wrote:
> >>Hi, guys
> >> While running rcutorture tests with "onoff_interval", some tests
> >>failed
Make pvpanic acpi driver as seperate file and modify code
in order to adapt the framework.
Signed-off-by: Peng Hao
---
drivers/misc/pvpanic/Kconfig| 9 +
drivers/misc/pvpanic/Makefile | 1 +
drivers/misc/pvpanic/pvpanic-acpi.c | 77 +
3
Preparing for pvpanic driver framework. Create a pvpanic driver
directory and move current driver file to new directory.
Signed-off-by: Peng Hao
---
drivers/misc/Kconfig | 9 +
drivers/misc/Makefile| 2 +-
drivers/misc/pvpanic/Kconfig | 7 +++
Make pvpanic mmioi driver as seperate file and modify code
in order to adapt the framework.
Signed-off-by: Peng Hao
---
drivers/misc/pvpanic/Kconfig | 4 +++
drivers/misc/pvpanic/Makefile | 1 +
drivers/misc/pvpanic/pvpanic-of.c | 53 +++
3 files
QEMU community requires additional PCI devices to simulate PVPANIC
devices so that some architectures can not occupy precious less than 4G
of memory space.
Previously, I added PCI driver directly to the original version of the driver,
which made the whole driver file look a bit cluttered. So
Add new pvpanic pci driver to pvpanic driver framework.
Signed-off-by: Peng Hao
---
drivers/misc/pvpanic/Kconfig | 5
drivers/misc/pvpanic/Makefile | 1 +
drivers/misc/pvpanic/pvpanic-pci.c | 56 ++
3 files changed, 62 insertions(+)
create
Add pvpanic driver framework. Split the original pvpanic acpi/of
driver as the two seperate files and modify code for adaptation framework
in follow-up patches.
Signed-off-by: Peng Hao
---
drivers/misc/pvpanic/pvpanic.c | 171 ++---
1 file changed, 39
Add pvpanic_add/remove_device API. Follow-up patches will use them to
add/remove specific drivers into framework.
Signed-off-by: Peng Hao
---
drivers/misc/pvpanic/pvpanic.c | 32
drivers/misc/pvpanic/pvpanic.h | 14 ++
2 files changed, 46
LTP case read_all_proc(read_all -d /proc -q -r 10) often, but not every time,
fails with the following call traces, since 600335205b8d "ide: convert to
blk-mq"(5.0-rc1) till now(5.0-rc3).
qemu-system-x86_64 -drive file=rootfs.ext4,if=virtio,format=raw -object
On 2019/1/23 上午1:03, Tiwei Bie wrote:
This patch introduces the support for VIRTIO_F_ORDER_PLATFORM.
When this feature is negotiated, driver will use the barriers
suitable for hardware devices.
Signed-off-by: Tiwei Bie
---
drivers/virtio/virtio_ring.c | 8
On Tue, Jan 22, 2019 at 11:59:31AM -0800, Stefano Stabellini wrote:
> On Mon, 21 Jan 2019, Peng Fan wrote:
> > on i.MX8QM, M4_1 is communicating with DomU using rpmsg with a fixed
> > address as the dma mem buffer which is predefined.
> >
> > Without this patch, the flow is:
> > vring_map_one_sg
Hi, Linus,
Please pull from
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux.git for-rc
to receive the latest Thermal management updates for v5.0-rc4 with
top-most commit 129699bb8c7572106b5bbb2407c2daee4727ccad:
drivers: thermal: int340x_thermal: Fix sysfs race condition
On Tue, 2019-01-22 at 21:18 -0500, Matt McCoy wrote:
> Remove unnecessary parentheses reported by checkpatch.
[]
> diff --git a/drivers/staging/ks7010/ks_hostif.c
> b/drivers/staging/ks7010/ks_hostif.c
[]
> @@ -171,7 +171,7 @@ int get_current_ap(struct ks_wlan_private *priv, struct
>
On Tue, 22 Jan 2019 at 18:17, Faiz Abbas wrote:
>
> Hi Chunyan,
>
> +Rob Herring
>
> On 22/01/19 2:17 PM, Chunyan Zhang wrote:
> > sdhci-omap can support both external dma controller via dmaengine
> > framework as well as ADMA which standard SD host controller
> > provides.
> >
> > Signed-off-by:
On Wed, Jan 23, 2019 at 10:17:45AM +0800, Peter Xu wrote:
> On Tue, Jan 22, 2019 at 12:02:24PM -0500, Jerome Glisse wrote:
> > On Tue, Jan 22, 2019 at 05:39:35PM +0800, Peter Xu wrote:
> > > On Mon, Jan 21, 2019 at 09:05:35AM -0500, Jerome Glisse wrote:
> > >
> > > [...]
> > >
> > > > > +
Hi Vinod,
Today's linux-next merge of the slave-dma tree got a conflict in:
drivers/dma/imx-sdma.c
between commit:
750afb08ca71 ("cross-tree: phase out dma_zalloc_coherent()")
from Linus' tree and commit:
ceaf52265148 ("dmaengine: imx-sdma: pass ->dev to dma_alloc_coherent() API")
Ching,
> This patch series are against to mkp's 5.1/scsi-queue.
Applied to 5.1/scsi-queue. Thank you.
PS. Your file permissions are odd. I always have to change your diffs
from 755 to 644 before applying.
--
Martin K. Petersen Oracle Linux Engineering
On Wed, Jan 23, 2019 at 10:12:41AM +0800, Peter Xu wrote:
> On Tue, Jan 22, 2019 at 11:53:10AM -0500, Jerome Glisse wrote:
> > On Tue, Jan 22, 2019 at 04:22:38PM +0800, Peter Xu wrote:
> > > On Mon, Jan 21, 2019 at 10:55:36AM -0500, Jerome Glisse wrote:
> > > > On Mon, Jan 21, 2019 at 03:57:01PM
On 01/21/19 at 05:59pm, Kairui Song wrote:
> This patch let kexec_file_load makes use of .platform keyring as fall
> back if it failed to verify a PE signed image against secondary or
> builtin key ring, make it possible to verify kernel image signed with
> preboot keys as well.
>
> This commit
Remove unnecessary parentheses reported by checkpatch.
Signed-off-by: Matt McCoy
---
drivers/staging/ks7010/ks_hostif.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/ks7010/ks_hostif.c
b/drivers/staging/ks7010/ks_hostif.c
index 065bce1..d938b09
On Tue, Jan 22, 2019 at 12:02:24PM -0500, Jerome Glisse wrote:
> On Tue, Jan 22, 2019 at 05:39:35PM +0800, Peter Xu wrote:
> > On Mon, Jan 21, 2019 at 09:05:35AM -0500, Jerome Glisse wrote:
> >
> > [...]
> >
> > > > + change_protection(dst_vma, start, start + len, newprot,
> > > > +
On Tue, 22 Jan 2019 16:21:46 +0100
Greg Kroah-Hartman wrote:
> When calling debugfs functions, there is no need to ever check the
> return value. The function can work or not, but the code logic should
> never do something different based on this.
>
> Cc: "Naveen N. Rao"
> Cc: Anil S
On Tue, Jan 22, 2019 at 11:53:10AM -0500, Jerome Glisse wrote:
> On Tue, Jan 22, 2019 at 04:22:38PM +0800, Peter Xu wrote:
> > On Mon, Jan 21, 2019 at 10:55:36AM -0500, Jerome Glisse wrote:
> > > On Mon, Jan 21, 2019 at 03:57:01PM +0800, Peter Xu wrote:
> > > > The idea comes from a discussion
Hi Amit,
On Mon, Jan 21, 2019 at 11:38:34PM +0530, Amit Kucheria wrote:
> Since all cpus in the big and little clusters, respectively, are in the
> same frequency domain, use all of them for mitigation in the
> cooling-map. We end up with two cooling devices - one each for the big
> and little
On Wed, Jan 23, 2019 at 09:44:12AM +0900, Tetsuo Handa wrote:
> Daniel Jordan wrote:
> > On Sat, Jan 19, 2019 at 11:41:22AM +0900, Tetsuo Handa wrote:
> > > On 2019/01/19 4:48, Daniel Jordan wrote:
> > > > On Sat, Jan 19, 2019 at 02:04:58AM +0900, Tetsuo Handa wrote:
> > > > __queue_work has a
Joel Fernandes wrote:
> > Why do we need to call fallocate() synchronously with ashmem_mutex held?
> > Why can't we call fallocate() asynchronously from WQ_MEM_RECLAIM workqueue
> > context so that we can call fallocate() with ashmem_mutex not held?
> >
> > I don't know how ashmem works, but as
On 1/22/19 7:36 PM, Curtis Malainey wrote:
Curtis Malainey | Software Engineer | cujomalai...@google.com | 650-898-3849
On Wed, Jan 23, 2019 at 4:11 AM Pierre-Louis Bossart
wrote:
The issue was that we were seeing a memory corruption bug on an AMD
chromebooks with that function already
On 1/22/19 12:17 PM, Jerome Glisse wrote:
> So lattely i have been looking at page flags and we are using 6 flags
> for memory reclaim and compaction:
>
> PG_referenced
> PG_lru
> PG_active
> PG_workingset
> PG_reclaim
> PG_unevictable
>
> On top of which you can add the
On a large system with many CPUs, using PMTMR as the clock source can
have a significant impact on the overall system performance because
of the following reasons:
1) There is a single PMTMR counter shared by all the CPUs.
2) PMTMR counter reading is a very slow operation.
Using PMTMR as the
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/perf/xgene_pmu.c: In function 'xgene_perf_stop':
drivers/perf/xgene_pmu.c:1055:6: warning:
variable 'config' set but not used [-Wunused-but-set-variable]
It never used since introduction.
Signed-off-by: YueHaibing
---
From: Artem Panfilov
Date: Sun, 20 Jan 2019 19:05:15 +0300
> This patch adds support for the SIOCGHWTSTAMP ioctl which enables user
> processes to read the current hwtstamp_config settings
> non-destructively.
>
> Signed-off-by: Artem Panfilov
Applied, thanks.
Curtis Malainey | Software Engineer | cujomalai...@google.com | 650-898-3849
On Wed, Jan 23, 2019 at 4:11 AM Pierre-Louis Bossart
wrote:
>
>
> > The issue was that we were seeing a memory corruption bug on an AMD
> > chromebooks with that function already (not observed on Intel). I was
> >
Hello,
Greg Kroah-Hartman wrote:
> When calling debugfs code, there is no need to ever check the return
> value of the call, as no logic should ever change if a call works
> properly or not. Fix up a bunch of x86-specific code to not care about
> the results of debugfs.
>
> Greg Kroah-Hartman
Hello,
Oleksij Rempel wrote:
> This patches are take from OpenWRT, rebased and tested with kernel
> v5.0-rt1 on DPTechnics DPT-Module (Atheros AR9331) by me.
>
> Since one dt-bindings header is touched, I added DT maintainers to the
> TO/CC.
>
> Felix Fietkau (6):
> MIPS: ath79: add helpers for
From: Linus Lüssing
Date: Mon, 21 Jan 2019 07:26:24 +0100
> This patchset adds initial Multicast Router Discovery support to
> the Linux bridge (RFC4286). With MRD it is possible to detect multicast
> routers and mark bridge ports and forward multicast packets to such routers
> accordingly.
>
>
On Tue 22 Jan 16:28 PST 2019, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 21, 2019 at 9:52 PM Bjorn Andersson
> wrote:
> >
> > From: Sibi Sankar
> >
> > This patch adds Q6V5 MSS remoteproc node for SDM845 SoCs.
> >
> > Signed-off-by: Sibi Sankar
> > Reviewed-by: Douglas Anderson
> >
On Tue, Jan 22, 2019 at 11:30:30AM -0500, Joe Lawrence wrote:
> On 12/18/18 10:18 AM, Joe Lawrence wrote:
> >On 12/18/2018 03:49 AM, Miroslav Benes wrote:
> >>On Mon, 17 Dec 2018, Joe Lawrence wrote:
> >>
> >>>I'm just being picky about its documentation and how we should note its
> >>>usage in
The pull request you sent on Tue, 22 Jan 2019 14:37:29 -0800:
> https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
> tags/clk-fixes-for-linus
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/0b0d4be6b4880c7199d41afe4d9a3f20f47fd9bb
Thank you!
--
On Tue 22 Jan 16:40 PST 2019, Doug Anderson wrote:
> Hi,
>
> On Tue, Jan 22, 2019 at 4:26 PM Bjorn Andersson
> wrote:
> > > > + clocks = <_board>;
> > > > + clock-names = "xo";
> > >
> > > I've found that nearly all the places that refer to xo_board are wrong
> > >
Fix inconsistent IS_ERR and PTR_ERR in i2c_imx_dma_request.
The proper pointer to be passed as argument is dma->chan_tx.
This bug was detected with the help of Coccinelle.
Fixes: 5b3a23a3cc94 ("i2c: imx: notify about real errors on dma
i2c_imx_dma_request")
Signed-off-by: Gustavo A. R. Silva
On 1/22/19 4:33 PM, Florian Fainelli wrote:
> On 32-bit architectures defining resource_size_t as 64-bit (because of
> PAE), we can run into a linker failure because of the modulo and the
> division against resource_size(), replace the two problematic operations
> with an alignment check on the
On Wed, 2019-01-23 at 02:00 +0200, Oded Gabbay wrote:
> This patch adds the habanalabs skeleton driver. The driver does nothing at
> this stage except very basic operations. It contains the minimal code to
> insmod and rmmod the driver and to create a /dev/hlX file per PCI device.
trivial notes:
On Tue, Jan 22, 2019 at 09:00:45AM -0800, Sean Christopherson wrote:
> On Tue, Jan 22, 2019 at 11:29:52PM +0800, Changbin Du wrote:
> > The commit c73da3f ("KVM: VMX: Properly handle dynamic VM Entry/Exit
> > controls") has a typo that cause invalid vmexit controls. The
> >
On Tue 22 Jan 15:26 PST 2019, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 21, 2019 at 9:51 PM Bjorn Andersson
> wrote:
> >
> > Define the rmtfs memory node, as described in version 10 of the memory
> > map.
> >
> > Signed-off-by: Bjorn Andersson
> > ---
> >
> > Changes since v2:
> > - New patch
Hello Rui,
On Tue, 4 Dec 2018 at 02:12, Zhang Rui wrote:
> On 三, 2018-10-10 at 01:30 -0700, Matthew Garrett wrote:
> > Platforms support more DPTF policies than the driver currently
> > exposes.
> > Add them. This effectively reverts
> > 31908f45a583e8f21db37f402b6e8d5739945afd which removed
Daniel Jordan wrote:
> On Sat, Jan 19, 2019 at 11:41:22AM +0900, Tetsuo Handa wrote:
> > On 2019/01/19 4:48, Daniel Jordan wrote:
> > > On Sat, Jan 19, 2019 at 02:04:58AM +0900, Tetsuo Handa wrote:
> > > __queue_work has a sanity check already for work, but using list_empty.
> > > Seems
> > >
On Tue 22 Jan 15:16 PST 2019, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 21, 2019 at 9:52 PM Bjorn Andersson
> wrote:
> >
> > Update existing and add all missing PIL regions to the reserved memory
> > map, as described in version 10.
> >
> > Signed-off-by: Bjorn Andersson
> > ---
> >
> >
Hi,
On Tue, Jan 22, 2019 at 4:26 PM Bjorn Andersson
wrote:
> > > + clocks = <_board>;
> > > + clock-names = "xo";
> >
> > I've found that nearly all the places that refer to xo_board are wrong
> > and should actually point to '< RPMH_CXO_CLK>'. Maybe yours
> > should
The driver can be built as a module just fine, so let's make it
selectable as such.
Reported-by: Paul Gortmaker
Signed-off-by: Florian Fainelli
---
drivers/reset/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index
On 32-bit architectures defining resource_size_t as 64-bit (because of
PAE), we can run into a linker failure because of the modulo and the
division against resource_size(), replace the two problematic operations
with an alignment check on the register resource (instead of modulo),
and the
Hi Philipp,
These two patches fix some recent issues brought up by Paul and Randy,
feel free to squash into c196cdc7659d ("reset: Add Broadcom STB SW_INIT
reset controller driver") since this is only in reset/next and
linux-next so far.
Thank you!
Florian Fainelli (2):
reset: brcmstb: Make it
On Tue, Jan 22, 2019 at 6:29 PM Omar Sandoval wrote:
...
> Now entry is uninitialized here when we assign it to d->debugfs.
Thanks for noticing that.
On Tue 22 Jan 15:10 PST 2019, Doug Anderson wrote:
> Hi,
>
> On Tue, Jan 22, 2019 at 11:24 AM Bjorn Andersson
> wrote:
> >
> > On Tue 22 Jan 10:58 PST 2019, Stephen Boyd wrote:
> >
> > > Quoting Bjorn Andersson (2019-01-21 21:51:03)
> > > > @@ -103,10 +138,30 @@
> > > >
Hi,
On Mon, Jan 21, 2019 at 9:52 PM Bjorn Andersson
wrote:
>
> From: Sibi Sankar
>
> This patch adds Q6V5 MSS remoteproc node for SDM845 SoCs.
>
> Signed-off-by: Sibi Sankar
> Reviewed-by: Douglas Anderson
> Signed-off-by: Bjorn Andersson
> ---
>
> Changes since v2:
> - Picked up Sibi's
PTR_RET is deprecated and will be removed soon.
Use PTR_ERR_OR_ZERO instead.
Notice that these are the last instances of PTR_RET in the
whole codebase.
Signed-off-by: Gustavo A. R. Silva
---
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
On Thu, Jan 17, 2019 at 9:14 AM Manivannan Sadhasivam
wrote:
>
> /* Skip the channels which are masked */
> if ((d->dma_channel_mask) & BIT(pch))
> continue;
Per the discussion w/ Vinod and Rob, I think I'll leave this bit be,
so we use the channels in the bitmask.
> PS: Use BIT() macro
usnic driver was tested with this change.
Acked-by: Parvi Kaustubhi
> On Jan 22, 2019, at 7:17 AM, Greg Kroah-Hartman
> wrote:
>
> When calling debugfs functions, there is no need to ever check the
> return value. The function can work or not, but the code logic should
> never do something
On Tue 22 Jan 15:46 PST 2019, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 21, 2019 at 9:52 PM Bjorn Andersson
> wrote:
> >
> > Add the ADSP and CDSP nodes for PAS-based remoteproc, supporting booting
> > these cores on e.g. the MTP, and enable the same for the MTP.
> >
> > Signed-off-by: Bjorn
On 1/22/19 11:51 AM, Tim Harvey wrote:
On Mon, Jan 21, 2019 at 12:24 PM Tim Harvey wrote:
On Tue, Jan 15, 2019 at 3:54 PM Steve Longerbeam wrote:
Hi Tim,
On 1/15/19 1:58 PM, Tim Harvey wrote:
On Wed, Jan 9, 2019 at 10:30 AM Steve Longerbeam wrote:
Also add an example pipeline for
On Tue, 22 Jan 2019 16:21:44 +0100
Greg Kroah-Hartman wrote:
> When calling debugfs functions, there is no need to ever check the
> return value. The function can work or not, but the code logic should
> never do something different based on this.
Ah, OK. It simplifies the code. But I have a
On 1/21/19 12:24 PM, Tim Harvey wrote:
On Tue, Jan 15, 2019 at 3:54 PM Steve Longerbeam wrote:
Hi Tim,
On 1/15/19 1:58 PM, Tim Harvey wrote:
On Wed, Jan 9, 2019 at 10:30 AM Steve Longerbeam wrote:
Also add an example pipeline for unconverted capture with interweave
on SabreAuto.
Dear Friend,
With due respect to your person and much sincerity of purpose, I make this
contact with you as I believe that you can be of great assistance to me. My
name is Mr. Abdul Samad, from Ouagadougou Republic of BURKINA FASO, West
Africa . Presently i work in the African development Bank as
Some works after roll-forward recovery can get an error which will release
all the data structures. Let's flush them in order to make it clean.
One possible corruption came from:
[ 90.400500] list_del corruption. prev->next should be ffed1f566208, but
was (null)
[ 90.675349] Call trace:
This patch adds support for doing various on-the-fly reset of Goya.
The driver supports two types of resets:
1. soft-reset
2. hard-reset
Soft-reset is done when the device detects a timeout of a command
submission that was given to the device. The soft-reset process only resets
the engines that
This patch adds the H/W queues module and the code to initialize Goya's
various compute and DMA engines and their queues.
Goya has 5 DMA channels, 8 TPC engines and a single MME engine. For each
channel/engine, there is a H/W queue logic which is used to pass commands
from the user to the H/W.
This patch adds two modules - ASID and context.
Each user process the opens a device's file must have at least one context
before it is able to "work" with the device. Each context has its own
device address-space and contains information about its runtime state (its
active command submissions).
When we umount f2fs, we need to avoid long delay due to discard commands, which
is actually taking tens of seconds, if storage is very slow on UNMAP. So, this
patch introduces timeout-based work on it.
By default, let me give 5 seconds for discard.
Signed-off-by: Jaegeuk Kim
---
Hi,
On Mon, Jan 21, 2019 at 9:52 PM Bjorn Andersson
wrote:
> @@ -1333,7 +1431,7 @@ static int q6v5_probe(struct platform_device *pdev)
> ret = qcom_q6v5_init(>q6v5, pdev, rproc,
> MPSS_CRASH_REASON_SMEM,
> qcom_msa_handover);
> if (ret)
> -
This patch adds debugfs support to the driver. It allows the user-space to
display information that is contained in the internal structures of the
driver, such as:
- active command submissions
- active user virtual memory mappings
- number of allocated command buffers
It also enables the user to
The habanalabs driver was written from scratch from the very first days
of Habana and is maintained by Oded Gabbay.
Signed-off-by: Oded Gabbay
---
CREDITS | 2 +-
MAINTAINERS | 9 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/CREDITS b/CREDITS
index
From: Omer Shpigelman
This patch adds the Virtual Memory and MMU modules.
Goya has an internal MMU which provides process isolation on the internal
DDR. The internal MMU also performs translations for transactions that go
from Goya to the Host.
The driver is responsible for allocating and
This patch adds support for receiving events from Goya's control CPU and
for receiving MSI-X interrupts from Goya's DMA engines and CPU.
Goya's PCI controller supports up to 8 MSI-X interrupts, which only 6 of
them are currently used. The first 5 interrupts are dedicated for Goya's
DMA engine
This patch add the sysfs and hwmon entries that are exposed by the driver.
Goya has several sensors, from various categories such as temperature,
voltage, current, etc. The driver exposes those sensors in the standard
hwmon mechanism.
In addition, the driver exposes a couple of interfaces in
This patch adds the main flow for the user to submit work to the device.
Each work is described by a command submission object (CS). The CS contains
3 arrays of command buffers: One for execution, and two for context-switch
(store and restore).
For each CB, the user specifies on which queue to
This patch implements the INFO IOCTL. That IOCTL is used by the user to
query information that is relevant/needed by the user in order to submit
deep learning jobs to Goya.
The information is divided into several categories, such as H/W IP, Events
that happened, DDR usage and more.
This patch adds the habanalabs skeleton driver. The driver does nothing at
this stage except very basic operations. It contains the minimal code to
insmod and rmmod the driver and to create a /dev/hlX file per PCI device.
Signed-off-by: Oded Gabbay
---
drivers/misc/Kconfig
This patch adds a basic support for the Goya device. The code initializes
the device's PCI controller and PCI bars. It also initializes various S/W
structures and adds some basic helper functions.
Signed-off-by: Oded Gabbay
---
drivers/misc/habanalabs/Makefile| 5 +-
Hello,
For those who don't know me, my name is Oded Gabbay (Kernel Maintainer
for AMD's amdkfd driver, worked at RedHat's Desktop group) and I work at
Habana Labs since its inception two and a half years ago.
Habana is a leading startup in the emerging AI processor space and we have
already
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