The GPIO-based bitbanging I2C driver is required to configure
CSI data, clock pins on CSI block in Allwinner A64 SoC.
Let build it as module.
Signed-off-by: Jagan Teki
---
Changes for v2:
- rebase on master
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
Enable Camera sensor interface for Allwinner SUN6I SoC's.
This support enable V4L2 platform drivers static and
VIDEO_SUN6I_CSI as module.
Signed-off-by: Jagan Teki
---
Changes for v2:
- rebase on master
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git
On 31/01/2019 14:53, Julien Thierry wrote:
> Hi,
>
> This patch series provides a way for irqchips to define some IRQs as NMIs.
>
> Updating this series as it is needed for the arm64 pseudo-NMI which we
> are considering to merge (I'll post a new version shortly).
>
Latest version of the
On Tue, Jan 29, 2019 at 07:20:28PM +, Dexuan Cui wrote:
From: Kimberly Brown
> ...
> But as you pointed, at least for sub-channels, channel->ringbuffer_page
> can indeed disappear in vmbus_close() -> ... -> vmbus_free_ring(), and
> the "attribute->show()" could crash when the race happens.
Thomas:
On Mon, Jan 28, 2019 at 11:39 PM Thomas Gleixner wrote:
[...]
> As an unintended side effect this distinction causes a major headache for
> license compliance, license scanners and the ongoing effort to clean up the
> license mess of the kernel.
Glad to be of service and sorry for having
Hi Johan,
>>> On Fri, Jan 25, 2019 at 04:29:05PM -0700, Shuah Khan wrote:
tty_set_termios() has the following WARMN_ON which can be triggered with a
syscall to invoke TIOCGETD __NR_ioctl.
>
> You meant TIOCSETD here, and in fact its the call which sets the uart
> protocol that triggers
Le jeudi 31 janvier 2019 à 22:34 +0900, Tomasz Figa a écrit :
> On Thu, Jan 31, 2019 at 9:42 PM Philipp Zabel wrote:
> > Hi Nicolas,
> >
> > On Wed, 2019-01-30 at 10:32 -0500, Nicolas Dufresne wrote:
> > > Le mercredi 30 janvier 2019 à 15:17 +0900, Tomasz Figa a écrit :
> > > > > I don't
On Tue, Jan 22, 2019 at 10:39:05AM -0800, Alexander Duyck wrote:
> This patch set provides functionality that will help to improve the
> locality of the async_schedule calls used to provide deferred
> initialization.
>
> This patch set originally started out focused on just the one call to
>
31.01.2019 9:16, Sowjanya Komatineni пишет:
> Bus clear feature of tegra i2c controller helps to recover from
> bus hang when i2c master loses the bus arbitration due to the
> slave device holding SDA LOW continuously for some unknown reasons.
>
> Per I2C specification, the device that held the
On 01/31/2019 05:49 AM, Kirill Tkhai wrote:
>
> 2)Not related to your patch -- it looks like we have problem in existing
> code with this netdev_refcnt_read(). It does not imply a memory ordering
> or some guarantees about reading percpu values. For example, in generic
> code struct percpu_ref
Hi Kirill, and thanks for your time,
On 31 Jan 19 14:49, Kirill Tkhai ktk...@virtuozzo.com wrote :
> Hi, Alexandre,
> On 31.01.2019 16:20, alexandre.besn...@softathome.com wrote:
> > From: Alexandre Besnard
> > Device remaining references counter is get as a signed integer.
> > When
31.01.2019 9:16, Sowjanya Komatineni пишет:
> This patch sorts all the include headers alphabetically for the
> I2C tegra driver
>
> Signed-off-by: Sowjanya Komatineni
> ---
> [V3/V4/V5/V7/V8] : Removed unsued headers in tegra I2C
> [V2] : Added this in V2 to sort the headers in tegra I2C
>
>
Hi Zeng,
On 31/01/2019 14:47, Zheng Xiang wrote:
> Hi Marc,
>
> On 2019/1/29 13:42, Zheng Xiang wrote:
>> On 2019/1/28 21:51, Marc Zyngier wrote:
>>> On 28/01/2019 07:13, Zheng Xiang wrote:
Hi Marc,
Thanks for your review.
On 2019/1/26 19:38, Marc Zyngier wrote:
> Hi
31.01.2019 9:16, Sowjanya Komatineni пишет:
> This patch adds DMA support for Tegra I2C.
>
> Tegra I2C TX and RX FIFO depth is 8 words. PIO mode is used for
> transfer size of the max FIFO depth and DMA mode is used for
> transfer size higher than max FIFO depth to save CPU overhead.
>
> PIO
On Thu, Jan 31, 2019 at 09:05:01AM +0100, Christoph Hellwig wrote:
> On Wed, Jan 30, 2019 at 08:44:20PM +, Jason Gunthorpe wrote:
> > Not really, for MRs most drivers care about DMA addresses only. The
> > only reason struct page ever gets involved is because it is part of
> > the GUP, SGL and
On 1/30/19 2:57 PM, Singh, Brijesh wrote:
> A kexec reboot may leave the firmware in INIT or WORKING state.
> Currently, we issue PLATFORM_INIT command during the probe without
> checking the current state. The PLATFORM_INIT command fails if the
> FW is already in INIT state. Lets check the
On Thu, Jan 31, 2019 at 09:02:03AM +0100, Christoph Hellwig wrote:
> On Wed, Jan 30, 2019 at 01:50:27PM -0500, Jerome Glisse wrote:
> > I do not see how VMA changes are any different than using struct page
> > in respect to userspace exposure. Those vma callback do not need to be
> > set by
31.01.2019 17:43, Thierry Reding пишет:
> On Thu, Jan 31, 2019 at 05:06:18PM +0300, Dmitry Osipenko wrote:
>> 31.01.2019 15:06, Thierry Reding пишет:
>>> On Thu, Jan 31, 2019 at 03:05:48AM +0300, Dmitry Osipenko wrote:
30.01.2019 19:01, Sowjanya Komatineni пишет:
>>> [...]
> diff --git
Add RTC support for i.MX8MQ.
Signed-off-by: Abel Vesa
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 892063a..49b14af 100644
---
Add a cpufeature indicating whether a cpu supports masking interrupts
by priority.
The feature will be properly enabled in a later patch.
Signed-off-by: Julien Thierry
Reviewed-by: Suzuki K Poulose
Reviewed-by: Mark Rutland
Acked-by: Catalin Marinas
Acked-by: Marc Zyngier
Cc: Catalin
The addition of PMR should not bypass the semantics of daifflags.
When DA_F are set, I bit is also set as no interrupts (even of higher
priority) is allowed.
When DA_F are cleared, I bit is cleared and interrupt enabling/disabling
goes through ICC_PMR_EL1.
Signed-off-by: Julien Thierry
Sent from my iPad
> On Jan 31, 2019, at 10:03 PM, Ezequiel Garcia wrote:
>
> Hey Ayaka!
>
>> On Thu, 2019-01-31 at 11:13 +0800, ayaka wrote:
>> From: Randy 'ayaka' Li
>>
>> Hello
>> Those patches are based on the previous vendor driver I post before,
>> but it can apply without the
The values non secure EL1 needs to use for PMR and RPR registers depends on
the value of SCR_EL3.FIQ.
The values non secure EL1 sees from the distributor and redistributor
depend on whether security is enabled for the GIC or not.
To avoid having to deal with two sets of values for PMR
Provide a higher priority to be used for pseudo-NMIs. When such an
interrupt is received, keep interrupts fully disabled at CPU level to
prevent receiving other pseudo-NMIs while handling the current one.
Signed-off-by: Julien Thierry
Acked-by: Marc Zyngier
Cc: Thomas Gleixner
Cc: Jason Cooper
Instead disabling interrupts by setting the PSR.I bit, use a priority
higher than the one used for interrupts to mask them via PMR.
When using PMR to disable interrupts, the value of PMR will be used
instead of PSR.[DAIF] for the irqflags.
Signed-off-by: Julien Thierry
Suggested-by: Daniel
Implement architecture specific primitive allowing the GICv3 driver to
use priorities to mask interrupts.
Signed-off-by: Julien Thierry
Suggested-by: Daniel Thompson
Acked-by: Marc Zyngier
Cc: Marc Zyngier
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/arch_gicv3.h | 8
Currently, irqflags are saved before calling runtime services and
checked for mismatch on return.
Provide a pair of overridable macros to save and restore (if needed) the
state that need to be preserved on return from a runtime service.
This allows to check for flags that are not necesarly
Introduce fixed values for PMR that are going to be used to mask and
unmask interrupts by priority.
The current priority given to GIC interrupts is 0xa0, so clearing PMR's
most significant bit is enough to mask interrupts.
Signed-off-by: Julien Thierry
Suggested-by: Daniel Thompson
Acked-by:
In order to replace PSR.I interrupt disabling/enabling with ICC_PMR_EL1
interrupt masking, ICC_PMR_EL1 needs to be saved/restored when
taking/returning from an exception. This mimics the way hardware saves
and restores PSR.I bit in spsr_el1 for exceptions and ERET.
Add PMR to the registers to
i.MX8MQ needs it for RTC support.
Signed-off-by: Abel Vesa
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6e5af25..5ac64c5 100644
--- a/arch/arm64/configs/defconfig
+++
CPU does not received signals for interrupts with a priority masked by
ICC_PMR_EL1. This means the CPU might not come back from a WFI
instruction.
Make sure ICC_PMR_EL1 does not mask interrupts when doing a WFI.
Since the logic of cpu_do_idle is becoming a bit more complex than just
two
Per definition of the daifflags, Serrors can occur during any interrupt
context, that includes NMI contexts. Trying to nmi_enter in an nmi context
will crash.
Skip nmi_enter/nmi_exit when serror occurred during an NMI.
Suggested-by: James Morse
Signed-off-by: Julien Thierry
Acked-by: Marc
Handling of an NMI should not set any TIF flags. For NMIs received from
EL0 the current exit path is safe to use.
However, an NMI received at EL1 could have interrupted some task context
that has set the TIF_NEED_RESCHED flag. Preempting a task should not
happen as a result of an NMI.
Skip
Implement NMI callbacks for GICv3 irqchip. Install NMI safe handlers
when setting up interrupt line as NMI.
Only SPIs and PPIs are allowed to be set up as NMI.
Signed-off-by: Julien Thierry
Reviewed-by: Marc Zyngier
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
---
Add a build option and a command line parameter to build and enable the
support of pseudo-NMIs.
Signed-off-by: Julien Thierry
Suggested-by: Daniel Thompson
Cc: Catalin Marinas
Cc: Will Deacon
---
Documentation/admin-guide/kernel-parameters.txt | 5 +
arch/arm64/Kconfig
When an NMI is raised while interrupts where disabled, the IRQ tracing
already is in the correct state (i.e. hardirqs_off) and should be left
as such when returning to the interrupted context.
Check whether PMR was masking interrupts when the NMI was raised and
skip IRQ tracing if necessary.
Once the boot CPU has been prepared or a new secondary CPU has been
brought up, use ICC_PMR_EL1 to mask interrupts on that CPU and clear
PSR.I bit.
Since ICC_PMR_EL1 is initialized at CPU bringup, avoid overwriting
it in the GICv3 driver.
Signed-off-by: Julien Thierry
Suggested-by: Daniel
In preparation for the application of alternatives at different points
during the boot process, provide the possibility to check whether
alternatives for a feature of interest was already applied instead of
having a global boolean for all alternatives.
Make VHE enablement code check for the VHE
Interrupts masked by ICC_PMR_EL1 will not be signaled to the CPU. This
means that hypervisor will not receive masked interrupts while running a
guest.
We need to make sure that all maskable interrupts are masked from the
time we call local_irq_disable() in the main run loop, and remain so
until
From: Daniel Thompson
Currently alternatives are applied very late in the boot process (and
a long time after we enable scheduling). Some alternative sequences,
such as those that alter the way CPU context is stored, must be applied
much earlier in the boot sequence.
Introduce
The code to detect whether Linux has access to group0 interrupts can
prove useful in other parts of the driver.
Provide a separate function to do this.
Signed-off-by: Julien Thierry
Acked-by: Marc Zyngier
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
---
Add helper functions to access system registers related to interrupt
priorities: PMR and RPR.
Signed-off-by: Julien Thierry
Reviewed-by: Mark Rutland
Acked-by: Catalin Marinas
Reviewed-by: Marc Zyngier
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Marc Zyngier
---
It is not supported to have some CPUs using GICv3 sysreg CPU interface
while some others do not.
Once ICC_SRE_EL1.SRE is set on a CPU, the bit cannot be cleared. Since
matching this feature require setting ICC_SRE_EL1.SRE, it cannot be
turned off if found on a CPU.
Set the feature as
Mask the IRQ priority through PMR and re-enable IRQs at CPU level,
allowing only higher priority interrupts to be received during interrupt
handling.
Signed-off-by: Julien Thierry
Acked-by: Catalin Marinas
Acked-by: Marc Zyngier
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Thomas Gleixner
Cc:
There are some helpers to modify PSR.[DAIF] bits that are not referenced
anywhere. The less these bits are available outside of local_irq_*
functions the better.
Get rid of those unused helpers.
Signed-off-by: Julien Thierry
Reviewed-by: Mark Rutland
Acked-by: Catalin Marinas
Acked-by: Marc
Hi,
This series is a continuation of the work started by Daniel [1]. The goal
is to use GICv3 interrupt priorities to simulate an NMI.
The patches depend on the core API for NMIs patches [2]. Both series can
be found on this branch:
git clone http://linux-arm.org/linux-jt.git -b v5.0-pseudo-nmi
When using VHE, the host needs to clear HCR_EL2.TGE bit in order
to interact with guest TLBs, switching from EL2&0 translation regime
to EL1&0.
However, some non-maskable asynchronous event could happen while TGE is
cleared like SDEI. Because of this address translation operations
relying on
On Thu, Jan 31, 2019 at 03:22:19PM +0100, Andrea Parri wrote:
> Fix wildcard patterns and add cgroup-v2 documentation.
>
> Signed-off-by: Andrea Parri
Applied to cgroup/for-5.0.
Thanks.
--
tejun
On 1/31/2019 7:37 AM, Peter Zijlstra wrote:
On Wed, Jan 30, 2019 at 06:23:42AM -0800, kan.li...@linux.intel.com wrote:
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 374a197..03bf45d 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2578,3 +2578,45 @@
On Mon, Jan 28, 2019 at 05:00:13PM +0100, Oleg Nesterov wrote:
> The only user of cgroup_subsys->free() callback is pids_cgrp_subsys which
> needs pids_free() to uncharge the pid.
>
> However, ->free() is called from __put_task_struct()->cgroup_free() and this
> is too late. Even the trivial
Hi,
On 31/01/2019 13:52, Zhen Lei wrote:
> Currently, many peripherals are faster than before. For example, the top
> speed of the older netcard is 10Gb/s, and now it's more than 25Gb/s. But
> when iommu page-table mapping enabled, it's hard to reach the top speed
> in strict mode, because of
NMI handling code should be executed between calls to nmi_enter and
nmi_exit.
Add a separate domain handler to properly setup NMI context when handling
an interrupt requested as NMI.
Signed-off-by: Julien Thierry
Acked-by: Marc Zyngier
Cc: Thomas Gleixner
Cc: Marc Zyngier
Cc: Will Deacon
Provide flow handlers that are NMI safe for interrupts and percpu_devid
interrupts.
Signed-off-by: Julien Thierry
Acked-by: Marc Zyngier
Cc: Thomas Gleixner
Cc: Marc Zyngier
Cc: Peter Zijlstra
---
include/linux/irq.h | 3 +++
kernel/irq/chip.c | 54
Hi,
This patch series provides a way for irqchips to define some IRQs as NMIs.
Updating this series as it is needed for the arm64 pseudo-NMI which we
are considering to merge (I'll post a new version shortly).
Changes since v5[1]:
- Added Marc's Acked-by, Reviewed-by tags
- Fixed locking bug in
Add support for percpu_devid interrupts treated as NMIs.
Percpu_devid NMIs need to be setup/torn down on each CPU they target.
The same restrictions as for global NMIs still apply for percpu_devid NMIs.
Signed-off-by: Julien Thierry
Cc: Thomas Gleixner
Cc: Peter Zijlstra
Cc: Ingo Molnar
Cc:
Add functionality to allocate interrupt lines that will deliver IRQs
as Non-Maskable Interrupts. These allocations are only successful if
the irqchip provides the necessary support and allows NMI delivery for the
interrupt line.
Interrupt lines allocated for NMI delivery must be enabled/disabled
On 1/18/19 6:51 PM, Mel Gorman wrote:
> Similar to the migration scanner, this patch uses the free lists to quickly
> locate a migration target. The search is different in that lower orders
> will be searched for a suitable high PFN if necessary but the search
> is still bound. This is justified
Hi Marc,
On 2019/1/29 13:42, Zheng Xiang wrote:
> On 2019/1/28 21:51, Marc Zyngier wrote:
>> On 28/01/2019 07:13, Zheng Xiang wrote:
>>> Hi Marc,
>>>
>>> Thanks for your review.
>>>
>>> On 2019/1/26 19:38, Marc Zyngier wrote:
Hi Zheng,
On Sat, 26 Jan 2019 06:16:24 +,
Zheng
Someone owes me a beer ...
While typing these I think doing an s/component_master/aggregate/
would be useful:
- it's shorter :-)
- I think component/aggregate is much more meaningful naming than
component/puppetmaster or something like that. At least to my
English ear "aggregate" emphasizes
Component framework is extended to support multiple components for
a struct device. These will be matched with different masters based on
its sub component value.
We are introducing this, as I915 needs two different components
with different subcomponent value, which will be matched to two
On Thu, Jan 31, 2019 at 05:06:18PM +0300, Dmitry Osipenko wrote:
> 31.01.2019 15:06, Thierry Reding пишет:
> > On Thu, Jan 31, 2019 at 03:05:48AM +0300, Dmitry Osipenko wrote:
> >> 30.01.2019 19:01, Sowjanya Komatineni пишет:
> > [...]
> >>> diff --git a/drivers/i2c/busses/i2c-tegra.c
> >>>
On Thu, Jan 31, 2019 at 03:37:23PM +0100, Christoph Hellwig wrote:
> On Thu, Jan 31, 2019 at 02:01:27PM +0100, Joerg Roedel wrote:
> > On Thu, Jan 31, 2019 at 11:41:29AM +0100, Christoph Hellwig wrote:
> > > Sorry for not noticing last time, but since 5.0 we keep all non-fast
> > > path DMA
On Thu, Jan 31, 2019 at 08:15:50AM -0600, Bjorn Helgaas wrote:
> On Wed, Jan 30, 2019 at 8:40 PM Stephen Rothwell
> wrote:
> >
> > Hi all,
> >
> > Today's linux-next merge of the vhost tree got a conflict in:
> >
> > drivers/pci/setup-bus.c
> >
> > between commit:
> >
> > 51c48b310183 ("PCI:
On Thu, 31 Jan 2019 09:52:43 +0100
Michael Mueller wrote:
> Function kvm_s390_gisa_clear() now clears the Interruption
> Pending Mask of the GISA asap. If the GISA is in the alert
> list at this time it stays in the list but is removed by
> process_gib_alert_list().
>
> Signed-off-by: Michael
On Thu, Jan 31, 2019 at 02:01:27PM +0100, Joerg Roedel wrote:
> On Thu, Jan 31, 2019 at 11:41:29AM +0100, Christoph Hellwig wrote:
> > Sorry for not noticing last time, but since 5.0 we keep all non-fast
> > path DMA mapping interfaces out of line, so this should move to
> > kernel/dma/mapping.c.
Kishon,
On 31/01/19 13:04, Kishon Vijay Abraham I wrote:
> Hi,
>
> On 31/01/19 4:11 PM, Roger Quadros wrote:
>>
>>
>> On 31/01/19 08:02, Kishon Vijay Abraham I wrote:
>>> Roger,
>>>
>>> On 30/01/19 8:28 PM, Roger Quadros wrote:
Kishon,
On 24/01/19 12:48, Kishon Vijay Abraham I
Hi Rob
Thanks for your comments!
On Wed, Jan 30, 2019 at 6:07 PM Rob Herring wrote:
>
> On Mon, Jan 28, 2019 at 10:49:31AM +0100, Ricardo Ribalda Delgado wrote:
> > Bindings for dac7612.
> >
> > Cc: devicet...@vger.kernel.org
> > Signed-off-by: Ricardo Ribalda Delgado
> > ---
> >
The load_microcode_amd() function searches for microcode patches and
attempts to apply a microcode patch if is a different level than the
currently installed level. While the processor won't actually load a
level that is less than what is installed, the logic is followed as if
the patch should be
On Thu, Jan 31, 2019 at 01:10:01PM +0100, Rafael J. Wysocki wrote:
> On Thu, Jan 31, 2019 at 12:59 PM Takashi Iwai wrote:
> >
> > On Thu, 31 Jan 2019 12:46:54 +0100,
> > Rafael J. Wysocki wrote:
> > >
> > > On Thu, Jan 31, 2019 at 12:21 PM Takashi Iwai wrote:
> > > >
> > > > On Thu, 31 Jan 2019
On Thu, 31 Jan 2019, Zhenzhong Duan wrote:
> On 2019/1/30 16:06, Thomas Gleixner wrote:
> > On Tue, 22 Jan 2019, Zhenzhong Duan wrote:
> >
> > > On a large system with many CPUs, using PMTMR as the clock source can
> > > have a significant impact on the overall system performance because
> > >
Instead of overriding the peripheral id(PID) check in AMBA
by hardcoding them in DT, add the PIDs to the ETM4x driver.
Here we use Unique Component Identifier(UCI) for MSM8996
since the ETM and CPU debug module shares the same PIDs.
SDM845 does not support CPU debug module.
Signed-off-by: Sai
Add UCI table for coresight CPU debug module. This patch adds
the UCI entries for Kryo CPUs found on MSM8996 which shares
the same PIDs as ETMs.
Without this, below error is observed on MSM8996:
[5.429867] OF: graph: no port node found in /soc/debug@381
[5.429938] coresight-etm4x:
SDM845 has ETMv4.2 and can use the existing etm4x driver.
But the current etm driver checks only for ETMv4.0 and
errors out for other etm4x versions. This patch adds this
missing support to enable SoC's with ETMv4x to use same
driver by checking only the ETM architecture major version
number.
From: Vivek Gautam
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
Signed-off-by: Vivek Gautam
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 434
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on MSM8998.
Signed-off-by: Sai Prakash Ranjan
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
This depends on MSM8998
Fix wildcard patterns and add cgroup-v2 documentation.
Signed-off-by: Andrea Parri
---
MAINTAINERS | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9f64f8d3740ed..a96054c1d870a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3906,9 +3906,10
On 1/31/2019 5:40 PM, Rafael J. Wysocki wrote:
On Thu, Jan 31, 2019 at 12:59 PM Takashi Iwai wrote:
On Thu, 31 Jan 2019 12:46:54 +0100,
Rafael J. Wysocki wrote:
On Thu, Jan 31, 2019 at 12:21 PM Takashi Iwai wrote:
On Thu, 31 Jan 2019 12:05:30 +0100,
Thierry Reding wrote:
On Wed, Jan 30,
I found same issue while debugging, I will submit patch to fix this shortly.
Philip
On 2019-01-30 10:35 p.m., Mikhail Gavrilov wrote:
> Hi folks.
> Yet another kernel panic happens while GPU again is hang:
>
> [ 1469.906798]
> [ 1469.906799] WARNING:
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
- Depends on AOSS QMP side channel patches by Bjorn Andersson [1] - [4].
- AMBA
This patch series adds support for coresight on SDM845, MSM8998, and MSM8996.
* Patch 1 adds device tree nodes for SDM845 coresight components.
* Patch 2 adds device tree nodes for MSM8998 coresight components.
* Patch 3 adds device tree nodes for MSM8996 coresight components.
* Patch 4
+++ Miguel Ojeda [23/01/19 18:37 +0100]:
The upcoming GCC 9 release adds the -Wmissing-attributes warnings
(enabled by -Wall), which trigger for all the init/cleanup_module
aliases in the kernel (defined by the module_init/exit macros),
ending up being very noisy.
These aliases point to the
On Wed, Jan 30, 2019 at 8:40 PM Stephen Rothwell wrote:
>
> Hi all,
>
> Today's linux-next merge of the vhost tree got a conflict in:
>
> drivers/pci/setup-bus.c
>
> between commit:
>
> 51c48b310183 ("PCI: Probe bridge window attributes once at
> enumeration-time")
>
> from the pci tree and
On 31.01.2019 14:25, Neil Armstrong wrote:
> Hi Andrzej, Laurent,
>
> On 15/01/2019 13:33, Neil Armstrong wrote:
>> This patchset aims to add support for the following HDMI2.0 4k60 modes:
>> - 594Mhz TMDS frequency needing TMDS Scramling and 1/40 rate for RGB/YUV4:4:4
>> - 297MHz TMDS frequency
On 1/31/19 2:55 PM, Vlastimil Babka wrote:
> On 1/18/19 6:51 PM, Mel Gorman wrote:
> ...
>
>> +for (order = cc->order - 1;
>> + order >= PAGE_ALLOC_COSTLY_ORDER && pfn == cc->migrate_pfn &&
>> nr_scanned < limit;
>> + order--) {
>> +struct free_area *area =
> On Jan 30, 2019, at 7:46 PM, Gustavo A. R. Silva
> wrote:
>
> One of the more common cases of allocation size calculations is finding
> the size of a structure that has a zero-sized array at the end, along
> with memory for some number of elements for that array. For example:
>
> struct
From: Colin Ian King
An unsigned long long is being formatted with %lld instead of the unsigned
version %llu. Fix this.
Clean up cppcheck warning:
%lld in format string (no. 1) requires 'long long' but the argument type
is 'unsigned long long'.
Fixes: a62c24d75529 ("mtd: part: Add sysfs
31.01.2019 15:06, Thierry Reding пишет:
> On Thu, Jan 31, 2019 at 03:05:48AM +0300, Dmitry Osipenko wrote:
>> 30.01.2019 19:01, Sowjanya Komatineni пишет:
> [...]
>>> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> [...]
>>> + return -EIO;
>>> + }
>>> +
On Wed, Jan 30, 2019 at 12:40:59PM -0500, Dennis Zhou wrote:
> Hi David,
>
> On Tue, Jan 29, 2019 at 06:18:30PM +0100, David Sterba wrote:
> > On Mon, Jan 28, 2019 at 04:24:26PM -0500, Dennis Zhou wrote:
> > > As mentioned above, a requirement that differs zstd from zlib is that
> > > higher
lantianyu1...@gmail.com writes:
> From: Lan Tianyu
>
> On the bare metal, enabling X2APIC mode requires interrupt remapping
> function which helps to deliver irq to cpu with 32-bit APIC ID.
> Hyper-V doesn't provide interrupt remapping function so far and Hyper-V
> MSI protocol already supports
Hey Ayaka!
On Thu, 2019-01-31 at 11:13 +0800, ayaka wrote:
> From: Randy 'ayaka' Li
>
> Hello
> Those patches are based on the previous vendor driver I post before,
> but it can apply without the previous one.
> I really want to make it work before FOSDEM and I didn't. And upcoming
> the
Hello,
I am working on porting an out-of-tree kernel driver to the kernel
5.0 and that driver uses functionality provided by
drivers/xen/mem-reservation.c
module. Since commit [1] it is not possible to build a kernel module
which uses mem-reservation API as xen_scrub_pages variable, which is
Pop-culture updates for this OS.
It seems many three letter gods will more easily approve of a three-letter
concept, so popculture updates for this OS initiative will be an update of name
to PFY O-S "Pay Fair Operating System".
And we ourselves use a zën-concept of the deity, since
On Wed, Jan 30, 2019 at 08:33:48PM +0100, Greg Kroah-Hartman wrote:
> On Wed, Jan 30, 2019 at 06:21:02PM +, Will Deacon wrote:
> > Hi Greg,
> >
> > On Tue, Jan 22, 2019 at 03:41:11PM +0100, Greg Kroah-Hartman wrote:
> > > When calling debugfs functions, there is no need to ever check the
> >
On 1/18/19 6:51 PM, Mel Gorman wrote:
...
> + for (order = cc->order - 1;
> + order >= PAGE_ALLOC_COSTLY_ORDER && pfn == cc->migrate_pfn &&
> nr_scanned < limit;
> + order--) {
> + struct free_area *area = >zone->free_area[order];
> + struct
Currently, many peripherals are faster than before. For example, the top
speed of the older netcard is 10Gb/s, and now it's more than 25Gb/s. But
when iommu page-table mapping enabled, it's hard to reach the top speed
in strict mode, because of frequently map and unmap operations. In order
to keep
On Thu, Jan 31, 2019 at 8:40 AM Mike Rapoport wrote:
>
> (added Andrey Konovalov)
>
> On Thu, Jan 31, 2019 at 07:15:26AM +0100, Christophe Leroy wrote:
> >
> > Le 31/01/2019 à 07:06, Stephen Rothwell a écrit :
> > >Hi all,
> > >
> > >On Thu, 31 Jan 2019 16:38:54 +1100 Stephen Rothwell
> > >
Hi, Alexandre,
On 31.01.2019 16:20, alexandre.besn...@softathome.com wrote:
> From: Alexandre Besnard
>
> Device remaining references counter is get as a signed integer.
>
> When unregistering network devices, the loop waiting for this counter
> to decrement tests the 0 strict equality. Thus
Jacek
On 1/30/19 4:14 PM, Jacek Anaszewski wrote:
> Dan,
>
> On 1/30/19 10:07 PM, Dan Murphy wrote:
>> Jacek
>>
>> On 1/30/19 2:20 PM, Jacek Anaszewski wrote:
>>> Dan,
>>>
>>> On 1/30/19 8:59 PM, Dan Murphy wrote:
Jacek
On 1/30/19 1:37 PM, Jacek Anaszewski wrote:
> Hi Dan,
On Mon, 28 Jan 2019 10:49:30 +0100
Ricardo Ribalda Delgado wrote:
> It is a driver for Texas Instruments Dual, 12-Bit Serial Input
> Digital-to-Analog Converter.
>
> Datasheet of this chip:
> http://www.ti.com/lit/ds/sbas106/sbas106.pdf
>
> Signed-off-by: Ricardo Ribalda Delgado
Hi Ricardo,
Luca Coelho writes:
> On Thu, 2019-01-31 at 10:46 +1100, Stephen Rothwell wrote:
>> Hi all,
>>
>> After merging the wireless-drivers-next tree, today's linux-next
>> build
>> (x86_64 allmodconfig) produced this warning:
>>
>> drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c:195:13: warning:
>>
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