On Wed, Jan 30, 2019 at 09:14:00PM +0100, Peter Zijlstra wrote:
> On Tue, Jan 29, 2019 at 10:12:45AM -0500, Masayoshi Mizuma wrote:
> > From: Hidetoshi Seto
> >
> > register_sched_domain_sysctl() copies the cpu_possible_mask into
> > sd_sysctl_cpus, but only if sd_sysctl_cpus hasn't already been
On Mon, 28 Jan 2019 14:02:41 +0100
Artur Rojek wrote:
> Add an IIO driver for the ADC hardware present on Ingenic JZ47xx SoCs.
>
> Signed-off-by: Artur Rojek
Looks pretty good to me. A few minor things inline.
Thanks,
Jonathan
> ---
> drivers/iio/adc/Kconfig | 9 +
>
From: Bartosz Golaszewski
This series ports the davinci platform to using SPARSE_IRQ, cleans up
the irqchip drivers and moves them over to drivers/irqchip.
The series can be logically split into four parts. The first (1-8) aims
at introducing support for SPARSE_IRQ. It contains a couple changes
From: Bartosz Golaszewski
We need to create an irq domain if we want to select SPARSE_IRQ. The
cp-intc driver already supports it, but aintc doesn't. Use the helpers
provided by the generic irq chip abstraction.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/irq.c | 38
From: Bartosz Golaszewski
This variable is defined globally in common.c. Define separate local
variables for the aintc and cp-intc drivers and remove the global one.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/common.c | 2 --
arch/arm/mach-davinci/cp_intc.c
From: Bartosz Golaszewski
Everything is in place now for SPARSE_IRQ. Select it and set
DAVINCI_INTC_START to NR_IRQS.
We now need to include mach/irqs.h in a couple places as it is no
longer indirectly included after selecting SPARSE_IRQ.
Signed-off-by: Bartosz Golaszewski
---
From: Bartosz Golaszewski
We're going to extend the davinci_irq_init() function with a config
structure so we can drop the intc-related fields from davinci_soc_info.
Once we do it, we won't be able to use this routine directly as the
init_irq callback. Wrap the calls in additional helpers that
From: Bartosz Golaszewski
This is done in preparation for selecting CONFIG_SPARSE_IRQ. The
interrupt numbers will then start at the predefined NR_IRQS offset.
For now wrap all interrupt numbers with a macro and define
DAVINCI_INTC_START to 0. Logically nothing changes for now.
Signed-off-by:
From: Bartosz Golaszewski
We now use the generic ARM irq handler on davinci. There are no more
users that check davinci_intc_type. Remove the variable and all its
references.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/common.c | 1 -
From: Bartosz Golaszewski
The aintc driver has now been cleaned up. Move it to drivers/irqchip
where it belongs. There's no device-tree support for any dm* board so
there's no IRQCHIP_OF_DECLARE() - there's only the exported init
function called from machine code.
Signed-off-by: Bartosz
From: Bartosz Golaszewski
Add the new-style config structures for dm* SoCs. They will be used
once we make the aintc driver stop using davinci_soc_info.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/dm355.c | 11 +++
arch/arm/mach-davinci/dm365.c | 11 +++
From: Bartosz Golaszewski
Modify the aintc driver to take all its configuration from the new
config structure. Stop referencing davinci_soc_info in any way.
Move the declaration for davinci_aintc_init() to irq-davinci-aintc.h
and make it take the new config structure as parameter. Convert all
From: Bartosz Golaszewski
Add a config structure that will be used by aintc-based platforms.
It contains the register range resource, number of interrupts and
a list of priorities.
Signed-off-by: Bartosz Golaszewski
---
include/linux/irqchip/irq-davinci-aintc.h | 17 +
1 file
From: Bartosz Golaszewski
In preparation for moving the driver to drivers/irqchip do some
cleanup: use a common prefix for all symbols.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/cp_intc.c | 143 ++--
arch/arm/mach-davinci/da830.c |
From: Bartosz Golaszewski
I've been unable to figure out exactly why, but it seems that the
IRQ_TINT1_TINT34 interrupt for timer 1 needs to be handled as a
level irq, not edge like all others.
This timer is used by the dsp on dm64* boards only.
Let's move the handler setup out of the aintc
From: Bartosz Golaszewski
There's no need to have a local header for cp-intc. Move the only
declaration for a public function to common.h. Move all register
offsets into the driver source file and drop all unused defines.
Make cp_intc_of_init() static.
Signed-off-by: Bartosz Golaszewski
---
From: Bartosz Golaszewski
Add a config structure that will be used by cp-intc-based platforms.
It contains the register range resource and the number of interrupts.
Signed-off-by: Bartosz Golaszewski
---
include/linux/irqchip/irq-davinci-cp-intc.h | 16
1 file changed, 16
From: Bartosz Golaszewski
Modify the cp-intc driver to take all its configuration from the new
config structure. Stop referencing davinci_soc_info in any way.
Move the declaration for davinci_cp_intc_init() to
irq-davinci-cp-intc.h and make it take the new config structure as
parameter. Convert
From: Bartosz Golaszewski
Add the new-style config structures for dm* SoCs. They will be used
once we make the cp-intc driver stop using davinci_soc_info.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/da830.c | 10 ++
arch/arm/mach-davinci/da850.c | 10 ++
2
From: Alexandre Besnard
Device remaining references counter is get as a signed integer.
When unregistering network devices, the loop waiting for this counter
to decrement tests the 0 strict equality. Thus if an error occurs and
two references are given back by a protocol, we are stuck in the
From: Bartosz Golaszewski
Use WARN_ON() on eny error in cp-intc initialization and drop all
custom error messages.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/cp_intc.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git
From: Bartosz Golaszewski
This header is no longer needed. Remove it.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/cp_intc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 8d751318682d..812e49fcaa8b
From: Bartosz Golaszewski
As the second step in preparation for mach/irqs.h removal - replace
all constants defined there with the DAVINCI_INTC_IRQ() macro which
takes the NR_IRQS offset into account.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/asp.h | 8 +-
From: Bartosz Golaszewski
We can now remove mach/irqs.h as there are no more users.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/board-da830-evm.c | 1 -
arch/arm/mach-davinci/board-da850-evm.c | 1 -
arch/arm/mach-davinci/board-dm644x-evm.c | 1 -
From: Bartosz Golaszewski
We don't need comments explaining what functions with obvious names do.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/cp_intc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
From: Bartosz Golaszewski
These are no longer used. Remove them.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/da830.c | 19 ---
arch/arm/mach-davinci/da850.c | 20
arch/arm/mach-davinci/dm355.c | 3
From: Bartosz Golaszewski
The cp-intc driver has now been cleaned up. Move it to drivers/irqchip
where it belongs.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/Kconfig | 8 ++--
arch/arm/mach-davinci/Makefile| 2 --
From: Bartosz Golaszewski
Use lowercase letters in hexadecimal numbers as is done in most of the
kernel code base.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/cp_intc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-davinci/cp_intc.c
From: Bartosz Golaszewski
Replace the GPLv2 license boilerplate with an SPDX identifier.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/cp_intc.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-davinci/cp_intc.c
From: Bartosz Golaszewski
This field is not used by any board. Remove it as part of the interrupt
support cleanup.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/cp_intc.c | 5 -
arch/arm/mach-davinci/include/mach/common.h | 1 -
2 files changed, 6 deletions(-)
From: Bartosz Golaszewski
Since we now select SPARSE_IRQ in davinci, the mach/irqs.h header is
no longer included from asm/irq.h. All interrupt numbers for devices
should be defined as platform device resources. Let's prepare for the
removal of mach/irqs.h by moving all defines that we want to
From: Bartosz Golaszewski
Drop tabs from variable initialization. Arrange variables in reverse
christmas-tree order. Add a newline before a return.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/cp_intc.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff
From: Bartosz Golaszewski
We're going to extend the cp_intc_init() function with a config
structure so we can drop the intc-related fields from davinci_soc_info.
Once we do it, we won't be able to use this routine directly as the
init_irq callback. Wrap the calls in additional helpers that
From: Bartosz Golaszewski
Replace the GPLv2 or later license boilerplate with an SPDX identifier.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/irq.c | 26 ++
1 file changed, 6 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-davinci/irq.c
From: Bartosz Golaszewski
These includes are no longer required. Remove them.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/irq.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 2e114ad83adc..ce4625d9cad7
From: Bartosz Golaszewski
In order to select SPARSE_IRQ we need to make the interrupt numbers
dynamic (at least at build-time for the top-level controller). The
interrupt numbers are used as array indexes for irq priorities.
Drop the defines and just initialize the arrays in a linear manner.
From: Bartosz Golaszewski
In preparation for moving the driver to drivers/irqchip do some
cleanup: use a common prefix for all symbols.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/dm355.c | 2 +-
arch/arm/mach-davinci/dm365.c | 2 +-
From: Bartosz Golaszewski
Since no offset goes past 0xff - let's drop the 00 prefix for better
readability. While we're at it: convert all hex numbers to lower-case.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/irq.c | 22 +++---
1 file changed, 11
From: Bartosz Golaszewski
In order to support SPARSE_IRQ we first need to make davinci use the
generic irq handler for ARM. Translate the legacy assembly to C and
put the irq handlers into their respective drivers (aintc and cp-intc).
Signed-off-by: Bartosz Golaszewski
---
arch/arm/Kconfig
On Thu, Jan 31, 2019 at 11:06:29AM +0100, Hans de Goede wrote:
> Hi,
>
> On 30-01-19 17:02, Heikki Krogerus wrote:
> > Hi,
> >
> > This is the second version of this series. On top the two code style
> > improvements requested by Andy, I also renamed the connection
> > identifiers used with the
On Wed, Jan 30, 2019 at 06:51:56PM +0200, Andy Shevchenko wrote:
> On Wed, Jan 30, 2019 at 6:03 PM Heikki Krogerus
> wrote:
> >
> > When the connections are defined in firmware, struct
> > device_connection will have the fwnode member pointing to
> > the device node (struct fwnode_handle) of the
On Thu, Jan 31, 2019 at 9:42 PM Philipp Zabel wrote:
>
> Hi Nicolas,
>
> On Wed, 2019-01-30 at 10:32 -0500, Nicolas Dufresne wrote:
> > Le mercredi 30 janvier 2019 à 15:17 +0900, Tomasz Figa a écrit :
> > > > I don't remember saying that, maybe I meant to say there might be a
> > > > workaround ?
On Thu, Jan 31, 2019 at 12:06:09AM +0200, Oded Gabbay wrote:
> This patch adds the H/W queues module and the code to initialize Goya's
> various compute and DMA engines and their queues.
>
> Goya has 5 DMA channels, 8 TPC engines and a single MME engine. For each
> channel/engine, there is a H/W
In function do_write_buffer(), in the for loop, there is a case
chip_ready() returns 1 while chip_good() returns 0, so it never
break the loop.
To fix this, chip_good() is enough and it should timeout if it stay
bad for a while.
Fixes: dfeae1073583(mtd: cfi_cmdset_0002: Change write buffer to
Add the bindings for the Bifrost family of ARM Mali GPUs.
The Bifrost GPU architecture is similar to the Midgard family,
but with a different Shader Core & Execution Engine structures.
Bindings are based on the Midgard family bindings, but the inner
architectural changes makes it a separate
When initializing clocks, a reference to the TCON channel 0 clock is
obtained. However, the clock is never prepared and enabled later.
Switching from simplefb to DRM actually disables the clock (that was
usually configured by U-Boot) because of that.
On the V3s, this results in a hang when
Hi Andrzej, Laurent,
On 15/01/2019 13:33, Neil Armstrong wrote:
> This patchset aims to add support for the following HDMI2.0 4k60 modes:
> - 594Mhz TMDS frequency needing TMDS Scramling and 1/40 rate for RGB/YUV4:4:4
> - 297MHz TMDS frequency with YUV4:2:0 encoding
>
> The first mode uses the
On 2019/1/31 20:48, Marc Zyngier wrote:
On 31/01/2019 11:19, Zenghui Yu wrote:
According to ARM IHI 0069C (ID070116), we should use GITS_TYPER's
bits [7:4] as ITT_entry_size.
Signed-off-by: Zenghui Yu
---
include/linux/irqchip/arm-gic-v3.h | 2 +-
1 file changed, 1 insertion(+), 1
Hello All,
On Fri, Dec 07, 2018 at 01:09:00PM +0200, Matti Vaittinen wrote:
> Series adds managed clkdev lookup interfaces and cleans few drivers
>
> Few clk drivers appear to be leaking clkdev lookup registrations at
> driver remove. The patch series adds devm versions of lookup
> registrations
On Thu, Jan 31, 2019 at 02:22:47PM +0100, Greg Kroah-Hartman wrote:
> On Thu, Jan 31, 2019 at 11:09:51AM +0100, Rafael J. Wysocki wrote:
> > On Thu, Jan 24, 2019 at 12:25 PM Rafael J. Wysocki
> > wrote:
> > >
> > > Hi Greg at al,
> > >
> > > Recently I have been looking at the device links code
On Thu, Jan 31, 2019 at 11:09:51AM +0100, Rafael J. Wysocki wrote:
> On Thu, Jan 24, 2019 at 12:25 PM Rafael J. Wysocki wrote:
> >
> > Hi Greg at al,
> >
> > Recently I have been looking at the device links code because of the
> > recent discussion on possibly using them in the DRM subsystem (see
On Thu, 31 Jan 2019 13:13:22 +
Peter Rosin wrote:
> On 2019-01-27 09:27, Boris Brezillon wrote:
> > On Thu, 10 Jan 2019 15:10:28 +
> > Peter Rosin wrote:
> >
> >> Hi!
> >>
> >> I found an unfortunate issue while recoding plane handling to use
> >>
On 1/31/19 1:44 PM, Philipp Zabel wrote:
> On Thu, 2019-01-31 at 13:30 +0100, Hans Verkuil wrote:
>> On 1/31/19 11:45 AM, Hans Verkuil wrote:
>>> On 1/24/19 11:04 AM, Tomasz Figa wrote:
Due to complexity of the video decoding process, the V4L2 drivers of
stateful decoder hardware require
On 1/31/2019 12:07 AM, Mathieu Poirier wrote:
On Tue, Jan 29, 2019 at 12:43:58AM +0530, Sai Prakash Ranjan wrote:
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
---
Depends on AOSS QMP side channel patches and AMBA bus pclk change
by Bjorn Andersson
On 31.01.19 14:09, Robin van der Gracht wrote:
On Thu, 31 Jan 2019 13:17:23 +0100
Ulf Hansson wrote:
On Thu, 31 Jan 2019 at 09:20, Robin van der Gracht wrote:
On Mon, 28 Jan 2019 22:15:23 +0100
Ulf Hansson wrote:
...
BTW, you didn't really answer my earlier question about the TI WiFi
On 2019-01-27 09:27, Boris Brezillon wrote:
> On Thu, 10 Jan 2019 15:10:28 +
> Peter Rosin wrote:
>
>> Hi!
>>
>> I found an unfortunate issue while recoding plane handling to use
>> drm_atomic_helper_check_plane_state(). The driver rotates clockwise,
>> which is not correct. I simply fixed
On Thu, 31 Jan 2019 12:40:04 +
wrote:
> On 01/31/2019 01:55 PM, Boris Brezillon wrote:
> > On Wed, 30 Jan 2019 15:08:47 +
> > wrote:
> >
> >> +
> >> +static int atmel_sam9x60_qspi_set_cfg(struct atmel_qspi *aq,
> >> +const struct spi_mem_op *op,
> >> +
>
> Aside from all the missin {}, I'm fairly sure this is broken since this
> happens from NMI context. This can interrupt switch_mm() and things like
> use_temporary_mm().
So the concern is that the sample is from before the switch, and then
looks it up in the wrong page tables if the PMI
On 31/01/19 14:03, Raslan, KarimAllah wrote:
>
> One option here would be to add 'e820__mapped_raw_any' (or whatever
> other name) and make it identical to the current implementation of
> e820__mapped_any at. Would that be slightly more acceptable? :)
Yes, of course it would (for me at least
On Thu, 31 Jan 2019 13:17:23 +0100
Ulf Hansson wrote:
> On Thu, 31 Jan 2019 at 09:20, Robin van der Gracht wrote:
> >
> > On Mon, 28 Jan 2019 22:15:23 +0100
> > Ulf Hansson wrote:
> >
> > > On Mon, 28 Jan 2019 at 15:41, Martin Kepplinger
> > > wrote:
> > > >
> > > > From: Martin
On Wed, 2019-01-30 at 18:14 +0100, Paolo Bonzini wrote:
> On 25/01/19 19:28, Raslan, KarimAllah wrote:
> >
> > So the simple way to do it is:
> >
> > 1- Pass 'mem=' in the kernel command-line to limit the amount of memory
> > managed
> > by the kernel.
> > 2- Map this physical memory you
On Thu, Jan 31, 2019 at 01:28:34PM +0530, Ravi Bangoria wrote:
> Hi Andi,
>
> On 1/25/19 9:30 PM, Andi Kleen wrote:
> >> [Fri Jan 25 10:28:53 2019] perf: interrupt took too long (2501 > 2500),
> >> lowering kernel.perf_event_max_sample_rate to 79750
> >> [Fri Jan 25 10:29:08 2019] perf:
On Thu, Jan 31, 2019 at 11:41:29AM +0100, Christoph Hellwig wrote:
> Sorry for not noticing last time, but since 5.0 we keep all non-fast
> path DMA mapping interfaces out of line, so this should move to
> kernel/dma/mapping.c.
Okay, attached patch does that. It applies on-top of this patch-set.
+ the platform maintainers.
On Thu, Jan 31, 2019 at 01:26:16PM +0100, Lubomir Rintel wrote:
> Hi,
>
> On Wed, 2019-01-23 at 21:56 +0100, Sebastian Reichel wrote:
> > Hi,
> >
> > On Thu, Jan 10, 2019 at 06:40:00PM +0100, Lubomir Rintel wrote:
> > > The XO-1 and XO-1.5 batteries apparently differ
Hi Souptick,
On 1/31/19 5:54 AM, Souptick Joarder wrote:
> On Thu, Jan 17, 2019 at 4:58 PM Mike Rapoport wrote:
>>
>> On Thu, Jan 17, 2019 at 04:53:44PM +0530, Souptick Joarder wrote:
>>> On Mon, Jan 7, 2019 at 10:54 PM Souptick Joarder
>>> wrote:
Remove duplicate headers which are
On Thu, Jan 31, 2019 at 01:37:25PM +0100, Peter Zijlstra wrote:
> On Wed, Jan 30, 2019 at 06:23:42AM -0800, kan.li...@linux.intel.com wrote:
> > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
> > index 374a197..03bf45d 100644
> > --- a/arch/x86/events/core.c
> > +++
On 1/31/19 1:08 PM, Jiri Kosina wrote:
> On Thu, 31 Jan 2019, Daniel Gruss wrote:
>
>> If I understood it correctly, this patch just removes the advantages of
>> preadv2 over mmmap+access for the attacker.
>
> Which is the desired effect. We are not trying to solve the timing aspect,
> as I
A virtio transport is free to implement some of the callbacks in
virtio_config_ops in a matter that they cannot be called from
atomic context (e.g. virtio-ccw, which maps a lot of the callbacks
to channel I/O, which is an inherently asynchronous mechanism).
This can be very surprising for
On Wed, Jan 30, 2019 at 10:16:27PM -0800, Sowjanya Komatineni wrote:
> This patch adds I2C interface timing registers support for
> proper bus rate configuration along with meeting the i2c spec
> setup and hold times based on the tuning performed on Tegra210,
> Tegra186 and Tegra194 platforms.
>
On Thu, 2019-01-31 at 09:44 +, Marc Zyngier wrote:
> On 31/01/2019 09:19, Honghui Zhang wrote:
> > On Tue, 2019-01-22 at 17:37 +0800, Jianjun Wang wrote:
> >> There is no need to create the inner domain as a parent for MSI domian,
> >> some feature has been implemented by MSI framework.
> >>
>
On 31/01/2019 11:19, Zenghui Yu wrote:
> According to ARM IHI 0069C (ID070116), we should use GITS_TYPER's
> bits [7:4] as ITT_entry_size.
>
> Signed-off-by: Zenghui Yu
> ---
> include/linux/irqchip/arm-gic-v3.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On Wed, Jan 30, 2019 at 10:16:26PM -0800, Sowjanya Komatineni wrote:
> Tegra194 allows max of 64K bytes and Tegra186 and prior allows
> max of 4K bytes of transfer per packet.
>
> one sec timeout is not enough for transfers more than 10K bytes
> at STD bus rate.
>
> This patch updates I2C
Hi Christoph,
I compiled kernels for the X5000 and X1000 from your branch
'powerpc-dma.6' today.
Gitweb:
http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/powerpc-dma.6
git clone git://git.infradead.org/users/hch/misc.git -b powerpc-dma.6 a
The X1000 and X5000 boot but
The following properties:
- regulator-state-enabled
- regulator-state-disabled
- regulator-state-uv
are not valid ones as per
Documentation/devicetree/bindings/regulator/regulator.txt
Fix it by using the correct properties as per the dt bindings.
Signed-off-by: Otavio Salvador
---
Changes in
The following properties:
- regulator-state-enabled
- regulator-state-disabled
- regulator-state-uv
are not valid ones as per
Documentation/devicetree/bindings/regulator/regulator.txt
Fix it by using the correct properties as per the dt bindings.
Signed-off-by: Otavio Salvador
---
Changes in
On rv1108-elgin-r1 board the RK805 VCC5 and VCC6 supplies come from
the BUCK2 regulator at 2.2V, so fix the representation in the
device tree.
While at it, rename it from vdd_cam to vdd_buck2, which is a better
name for the regulator label.
Signed-off-by: Otavio Salvador
---
Changes in v2:
I'm announcing the release of the 4.20.6 kernel.
All users of the 4.20 kernel series must upgrade.
The updated 4.20.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
linux-4.20.y
and can be browsed at the normal kernel.org git web browser:
On Wed, Jan 30, 2019 at 09:15:09AM +0100, Geert Uytterhoeven wrote:
> On Wed, Jan 30, 2019 at 9:10 AM Jonas Bonn wrote:
> > And with that said, if you insist having a u16 for this, I'll change it.
> > Just let me know.
> I'll defer that to the maintainer (Mark).
It's an internal kernel
RK805 has the following voltage range for the BUCK1 and BUCK2 regulators:
>From 0.7125V to 1.45V in 12.5mV steps, 1.8V, 2V, 2.2V and 2.3V
, which corresponds to the following values as per the RK805
datasheet:
000 000: 0.7125V
000 001: 0.725V
……
111 011: 1.45V
111 100: 1.8V
111 101: 2.0V
111
I'm announcing the release of the 4.19.19 kernel.
All users of the 4.19 kernel series must upgrade.
The updated 4.19.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
linux-4.19.y
and can be browsed at the normal kernel.org git web
diff --git a/Makefile b/Makefile
index 9f37a8a9feb9..39c4e7c3c13c 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 4
PATCHLEVEL = 19
-SUBLEVEL = 18
+SUBLEVEL = 19
EXTRAVERSION =
NAME = "People's Front"
diff --git
I'm announcing the release of the 4.14.97 kernel.
All users of the 4.14 kernel series must upgrade.
The updated 4.14.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
linux-4.14.y
and can be browsed at the normal kernel.org git web
On Wed, Jan 30, 2019 at 10:16:23PM -0800, Sowjanya Komatineni wrote:
> This patch sorts all the include headers alphabetically for the
> I2C tegra driver
>
> Signed-off-by: Sowjanya Komatineni
> ---
> [V3/V4/V5/V7/V8] : Removed unsued headers in tegra I2C
> [V2] : Added this in V2 to sort the
On Wed, Jan 30, 2019 at 10:16:24PM -0800, Sowjanya Komatineni wrote:
> Bus clear feature of tegra i2c controller helps to recover from
> bus hang when i2c master loses the bus arbitration due to the
> slave device holding SDA LOW continuously for some unknown reasons.
>
> Per I2C specification,
diff --git a/Makefile b/Makefile
index 57b45169ed85..485afde0f1f1 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 4
PATCHLEVEL = 14
-SUBLEVEL = 96
+SUBLEVEL = 97
EXTRAVERSION =
NAME = Petit Gorille
diff --git
diff --git a/Makefile b/Makefile
index 44a487ee24d2..9964792e200f 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
VERSION = 4
PATCHLEVEL = 9
-SUBLEVEL = 153
+SUBLEVEL = 154
EXTRAVERSION =
NAME = Roaring Lionus
diff --git a/arch/arc/include/asm/perf_event.h
Hello Mark,
On Wed, Jan 30, 2019 at 1:40 PM Mark Brown wrote:
> On Tue, Jan 29, 2019 at 05:54:21PM -0200, Otavio Salvador wrote:
> > RK805 has the following voltage range for the BUCK1 and BUCK2 regulators:
>
> I'm missing the other patches in this series and don't see a cover
> letter - what's
On Thu, 2019-01-31 at 13:30 +0100, Hans Verkuil wrote:
> On 1/31/19 11:45 AM, Hans Verkuil wrote:
> > On 1/24/19 11:04 AM, Tomasz Figa wrote:
> > > Due to complexity of the video decoding process, the V4L2 drivers of
> > > stateful decoder hardware require specific sequences of V4L2 API calls
> >
I'm announcing the release of the 4.9.154 kernel.
All users of the 4.9 kernel series must upgrade.
The updated 4.9.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
linux-4.9.y
and can be browsed at the normal kernel.org git web browser:
On Wed, Jan 30, 2019 at 10:16:25PM -0800, Sowjanya Komatineni wrote:
> This patch adds DMA support for Tegra I2C.
>
> Tegra I2C TX and RX FIFO depth is 8 words. PIO mode is used for
> transfer size of the max FIFO depth and DMA mode is used for
> transfer size higher than max FIFO depth to save
I'm announcing the release of the 4.9.154 kernel.
All users of the 4.9 kernel series must upgrade.
The updated 4.9.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
linux-4.9.y
and can be browsed at the normal kernel.org git web browser:
Hi Nicolas,
On Wed, 2019-01-30 at 10:32 -0500, Nicolas Dufresne wrote:
> Le mercredi 30 janvier 2019 à 15:17 +0900, Tomasz Figa a écrit :
> > > I don't remember saying that, maybe I meant to say there might be a
> > > workaround ?
> > >
> > > For the fact, here we queue the headers (or first
On 1/31/19 2:30 AM, Linus Torvalds wrote:
> See
>
>
>
> https://lore.kernel.org/lkml/CAHk-=wihe4dnhkpe4oghwwmy23jntuufqagwtgcjjxyovyj...@mail.gmail.com/
>
> for an explanation of the SH bug.
>
> But Guenter Roeck confirmed that my patch fixed it on SH for him. Is there
> something else
Hi,
Okay my bad, proper __initconst declarations would do the trick, cool stuff.
--
Janne
On Thu, Jan 31, 2019 at 1:09 PM Janne Karhunen wrote:
>
> Hi,
>
> Never mind, not enough coffee for the morning. Looks good addressing
> wise, but something goes haywire with the copy. Some size
On 01/31/2019 01:55 PM, Boris Brezillon wrote:
> On Wed, 30 Jan 2019 15:08:47 +
> wrote:
>
>> +
>> +static int atmel_sam9x60_qspi_set_cfg(struct atmel_qspi *aq,
>> + const struct spi_mem_op *op,
>> + struct atmel_qspi_cfg
On 1/31/19 1:30 PM, Hans Verkuil wrote:
> On 1/31/19 11:45 AM, Hans Verkuil wrote:
>> On 1/24/19 11:04 AM, Tomasz Figa wrote:
>>> Due to complexity of the video decoding process, the V4L2 drivers of
>>> stateful decoder hardware require specific sequences of V4L2 API calls
>>> to be followed.
On Wed, Jan 30, 2019 at 06:23:42AM -0800, kan.li...@linux.intel.com wrote:
> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
> index 374a197..03bf45d 100644
> --- a/arch/x86/events/core.c
> +++ b/arch/x86/events/core.c
> @@ -2578,3 +2578,45 @@ void perf_get_x86_pmu_capability(struct
On Thu, Jan 31, 2019 at 01:29:40PM +0100, Claudiu Beznea - M18063 wrote:
> From: Claudiu Beznea
>
> Add device tree binding for SAM9X60 pin controller.
>
> Signed-off-by: Claudiu Beznea
> ---
> Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 5 +++--
> 1 file changed, 3
Am Donnerstag, 31. Januar 2019, 13:31:52 CET schrieb Souptick Joarder:
> On Thu, Jan 31, 2019 at 5:37 PM Heiko Stuebner wrote:
> >
> > Am Donnerstag, 31. Januar 2019, 04:08:12 CET schrieb Souptick Joarder:
> > > Previouly drivers have their own way of mapping range of
> > > kernel pages/memory
On 31. 01. 19, 13:32, David Sterba wrote:
> This should be mentioned in the changelog though, it's not obvious at
> all why just returning after a failure is ok and that the packet will be
> resent.
Agreed.
thanks,
--
js
suse labs
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