From: Andi Kleen
The TopDown events can be collected per thread/process on Icelake. To
use TopDown through RDPMC in applications, the metrics and slots MSR
values have to be saved/restored during context switching.
It is useful to have a remove transaction when the counter is
unscheduled, so
From: Andi Kleen
The internal counters used for the metrics can overflow. If this happens
an overflow is triggered on the SLOTS fixed counter. Add special code
that resets all the slave metric counters in this case.
Signed-off-by: Andi Kleen
Signed-off-by: Kan Liang
---
No changes since V3.
From: Andi Kleen
The top down sub event counters are mapped to a fixed counter,
but should have the normal weight for the scheduler.
So special case this.
Signed-off-by: Andi Kleen
Signed-off-by: Kan Liang
---
No changes since V3.
arch/x86/events/intel/core.c | 9 +
1 file changed,
From: Kan Liang
To get correct PERF_METRICS value, the fixed counter 3 must start from
0. It would bring problems when sampling read slots and topdown events.
For example,
perf record -e '{slots, topdown-retiring}:S'
The slots would not overflow if it starts from 0.
Add specific
From: Kan Liang
Add Intel Icelake uncore support,
- The init code is based on Skylake
- Add new pci id for IMC
- New MSR address for CBOX
- Get CBOX# from CNL_UNC_CBO_CONFIG MSR directly
- Create a new PMU for fixed clocktick counter
Signed-off-by: Kan Liang
---
No changes since V3.
From: Andi Kleen
Icelake supports a new CPUID 10.ECX cpu leaf to indicate some fixed
counters are not supported. This extends the previous count to a bitmap
which allows to disable even lower counters.
It's a nop on Icelake (all fixed counters are supported), but let's
implement it here. This
From: Andi Kleen
Newer kernel code can collect XMM registers in some cases.
Add support for perf script to dump them, and support
for the register parser in perf record -I ... to configure them.
For now they are just printed in hex, could potentially add
other formats too.
Signed-off-by: Andi
From: Andi Kleen
Export new top down events for perf that map to the sub metrics
in the metrics register, and another for the new slots fixed counter.
This makes the new fixed counters in Icelake visible to the perf
user tools.
Signed-off-by: Andi Kleen
Signed-off-by: Kan Liang
---
No
From: Andi Kleen
Icelake has support for reporting per thread TopDown metrics.
These are reported differently than the previous TopDown support,
each metric is standalone, but scaled to pipeline "slots".
We don't need to do anything special for HyperThreading anymore.
Teach perf stat --topdown
From: Andi Kleen
Metrics counters (hardware counters containing multiple metrics)
are modelled as separate registers for each sub-event, with an
extra reg being used for coordinating access to the underlying
register in the scheduler.
This patch adds the basic infrastructure to separate the
From: Kan Liang
Icelake support the same RAPL counters as Skylake.
Signed-off-by: Kan Liang
---
No changes since V3.
arch/x86/events/intel/rapl.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
index
From: Kan Liang
Add V1 event list for Icelake.
Signed-off-by: Kan Liang
---
No changes since V3.
.../pmu-events/arch/x86/icelake/cache.json| 552 +++
.../arch/x86/icelake/floating-point.json | 90 ++
.../pmu-events/arch/x86/icelake/frontend.json | 424 +
From: Kan Liang
Icelake uses the same C-state residency events as Sandy Bridge.
Signed-off-by: Kan Liang
---
No changes since V3.
arch/x86/events/intel/cstate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index
From: Kan Liang
Starting from Icelake, XMM registers can be collected in PEBS record.
But current code only output the pt_regs.
Add a new struct x86_perf_regs for both pt_regs and xmm_regs.
XMM registers are 128 bit. To simplify the code, they are handled like
two different registers, which
From: Kan Liang
The patch series intends to add Icelake support for Linux perf.
PATCH 1-18: Kernel patches to support Icelake.
- 1-5: Support adaptive PEBS feature
- 6-7: Enable core support with some new features, e.g. 8 generic
counters, new event constraints, a new fixed counter.
-
From: Andi Kleen
With adaptive PEBS the CPU can directly supply the LBR information,
so we don't need to read it again. But the LBRs still need to be
enabled. Add a special count to the cpuc that distinguishes these
two cases, and avoid reading the LBRs unnecessarily when PEBS is
active.
Commit-ID: 766460852cfaeca4042e5f3aeb9616b3689147bc
Gitweb: https://git.kernel.org/tip/766460852cfaeca4042e5f3aeb9616b3689147bc
Author: Kangjie Lu
AuthorDate: Mon, 25 Mar 2019 15:29:22 -0500
Committer: Borislav Petkov
CommitDate: Tue, 26 Mar 2019 17:01:30 +0100
x86/platform/uv: Fix
On 26/03/2019 14:24, Marc Gonzalez wrote:
> +static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8998_pcie_serdes_tbl,
> + .serdes_tbl_num =
On Tue, 26 Mar 2019, Oleg Nesterov wrote:
> On 03/23, Thomas Gleixner wrote:
> >
> > On Thu, 28 Feb 2019, Gustavo A. R. Silva wrote:
> >
> > > arch/x86/include/asm/syscall.h | 28
> > > 1 file changed, 28 insertions(+)
> >
> > Second thoughts. So this adds 28 /*
On Mon, Mar 25, 2019 at 07:18:42PM +0100, Jann Horn wrote:
> On Mon, Mar 25, 2019 at 5:21 PM Christian Brauner
> wrote:
> > The pidctl() syscalls builds on, extends, and improves translate_pid() [4].
> > I quote Konstantins original patchset first that has already been acked and
> > picked up by
On Tue, 26 Mar 2019 17:04:30 +0100,
Ard Biesheuvel wrote:
>
> On Tue, 26 Mar 2019 at 16:25, Takashi Iwai wrote:
> >
> > On Fri, 01 Mar 2019 16:27:24 +0100,
> > Takashi Iwai wrote:
> > >
> > > On Fri, 01 Mar 2019 15:57:03 +0100,
> > > Ard Biesheuvel wrote:
> > > >
> > > > On Fri, 1 Mar 2019 at
On Tue, Mar 26, 2019 at 11:43:38AM -0400, Qian Cai wrote:
> Kmemleak could quickly fail to allocate an object structure and then
> disable itself in a low-memory situation. For example, running a mmap()
> workload triggering swapping and OOM. This is especially problematic for
> running things
On Tue, Mar 26, 2019 at 11:43:38AM -0400, Qian Cai wrote:
> Unless there is a brave soul to reimplement the kmemleak to embed it's
> metadata into the tracked memory itself in a foreseeable future, this
> provides a good balance between enabling kmemleak in a low-memory
> situation and not
Daniel,
On Tue, 26 Mar 2019, Daniel Lezcano wrote:
> >> +/*
> >> + * Exponential moving average computation
> >> + */
> >> +static int irq_timings_ema_new(s64 value, s64 ema_old)
> >
> > There is a mixed bag of s64/u64 all over this code. Please stay
> > consistent. We had enough sign confusion
Hi Julien,
On 2019-03-26, Julien Grall wrote:
>>> [...]
>>> [1.169151] 002: Serial: AMBA PL011 UART driver
>>> [1.254891] 002: 7ff8.uart: ttyAMA0 at MMIO 0x7ff8 (irq = 32,
>>> base_baud = 0) is a PL011 rev3
>>> [1.255007] 002: printk: console [ttyAMA0] enabled
>>
>> The
On Mon, Mar 25, 2019 at 06:40:17PM -0400, Joel Fernandes wrote:
> On Mon, Mar 25, 2019 at 12:42 PM Paul E. McKenney
> wrote:
> >
> > On Mon, Mar 25, 2019 at 12:33:37PM -0400, Joel Fernandes wrote:
> > > On Mon, Mar 25, 2019 at 11:02 AM Paul E. McKenney
> > > wrote:
> > > >
> > > > On Fri, Mar
On Tue, Mar 26, 2019 at 01:24:41PM +, David Woodhouse wrote:
> On Tue, 2019-03-26 at 12:17 +, Lorenzo Pieralisi wrote:
> > [+Zhou, Gustavo]
> >
> > On Tue, Mar 26, 2019 at 12:00:55PM +0200, Jonathan Chocron wrote:
> > > Adding support for Amazon's Annapurna Labs PCIe driver.
> > > The HW
On Tue, 26 Mar 2019, Qian Cai wrote:
> + if (!object) {
> + /*
> + * The tracked memory was allocated successful, if the kmemleak
> + * object failed to allocate for some reasons, it ends up with
> + * the whole kmemleak disabled, so let it
On Tue, 26 Mar 2019 16:16:54 +0100,
Timo Wischer wrote:
>
> On 3/26/19 15:23, Takashi Iwai wrote:
> > On Tue, 26 Mar 2019 12:25:37 +0100,
> > Timo Wischer wrote:
> >> On 3/26/19 09:35, Takashi Iwai wrote:
> >>
> >> On Tue, 26 Mar 2019 08:49:33 +0100,
> >> wrote:
> >>
Hi Jarkko,
On 3/25/19 7:09 AM, Jarkko Sakkinen wrote:
> It is still missing the comment I asked to add. Otherwise, it is good.
>
Sorry, I didn't see your email with the suggestion earlier.
To be honest I'm not sure if this comment adds much value, or if it is
even correct. The poll doesn't
This adds test cases for all three subcommands and verifies that they
succeed and fail as expected.
Additionally, the tests verify that pidctl() pidfds are correctly useable
with pidfd_send_signal().
Signed-off-by: Christian Brauner
Cc: Arnd Bergmann
Cc: "Eric W. Biederman"
Cc: Kees Cook
Cc:
Let pidfd_send_signal() use pidfds retrieved via pidctl(). With this patch
pidfd_send_signal() becomes independent of procfs. This fullfils the
request made when we merged the pidfd_send_signal() patchset. The
pidfd_send_signal() syscall is now always available allowing for it to be
used by users
From: David Howells
Make the anon_inodes facility unconditional so that it can be used by core
VFS code and the pidctl() syscall.
Signed-off-by: David Howells
Signed-off-by: Al Viro
[christ...@brauner.io: adapt commit message to mention pidctl()]
Signed-off-by: Christian Brauner
---
On Tue, Mar 26, 2019 at 08:43:45AM +, He, Bo wrote:
> Hi, Paul:
> I have tried on my PC and not hit any hang issue with RCU torture test
> for one hour, the configurations are like:
> OS: ubuntu 16.04
> kenrel: 3.18.136 + 3.18 rcu patch
> CPU: Intel(R) Xeon(R) CPU E3-1225 V2 @ 3.20GHz
The pidctl() syscalls builds on, extends, and improves translate_pid() [4].
I quote Konstantins original patchset first that has already been acked and
picked up by Eric before and whose functionality is preserved in this
syscall:
"Each process have different pids, one for each pid namespace it
On Mon, Mar 25, 2019 at 08:33:30PM +, Ghannam, Yazen wrote:
> From: Yazen Ghannam
>
> The AMD64 EDAC module current hardcodes the EDAC channel layer size
> (count) to two. Future AMD systems may have more channels than this.
>
> Set the EDAC channel layer size equal to the maximum number of
This is v1 of this patchset with various minor fixes which are listed in
the individual commits. Notably, pidfds are now O_CLOEXEC by default.
The pidctl() syscalls builds on, extends, and improves translate_pid()
[4] and serves as the natural connection between the pid-based and the
pidfd-based
On Wed, Mar 06, 2019 at 11:08:45PM +0100, Enrico Weigelt, metux IT consult
wrote:
> Formatting of Kconfig files doesn't look so pretty, so just
> take damp cloth and clean it up.
>
> Signed-off-by: Enrico Weigelt, metux IT consult
> ---
> drivers/infiniband/hw/bnxt_re/Kconfig | 10 +-
>
On Tue 2019-03-26 16:30:21, Andy Shevchenko wrote:
> On Tue, Mar 26, 2019 at 04:12:43PM +0200, Sakari Ailus wrote:
> > On Tue, Mar 26, 2019 at 04:06:33PM +0200, Heikki Krogerus wrote:
> > > On Tue, Mar 26, 2019 at 03:13:53PM +0200, Andy Shevchenko wrote:
>
> > > > > > Do we support swnode here?
>
On Tue, Mar 26, 2019 at 11:41:05AM +, Ghannam, Yazen wrote:
> They don't apply cleanly to v4.14 anymore because of the recent header change.
>
> I figured they would need to be fixed up and submitted separately to older
> stable
> versions. Is that okay?
Ah yes, right.
Thx.
--
Rename some traceevent APIs for consistency:
tep_pid_is_registered() to tep_is_pid_registered()
tep_file_bigendian() to tep_is_file_bigendian()
to make the names and return values consistent with other tep_is_... APIs
tep_data_lat_fmt() to tep_data_latency_format()
to make the name more
This patch renames "pevent" member of the struct tep_event_filter to "tep".
This makes the struct consistent with the chosen naming convention:
tep (trace event parser), instead of the old pevent.
Signed-off-by: Tzvetomir Stoyanov
---
tools/lib/traceevent/event-parse.h | 2 +-
This patch removes call to exit() from tep_filter_add_filter_str(). A library
function should not force the application to exit. In the current implementation
tep_filter_add_filter_str() calls exit() when a special "test_filters" mode is
set, used only for debugging purposes. When this mode is set
This patch renames "pevent" member of the struct tep_event to "tep". This makes
the struct consistent with the chosen naming convention:
tep (trace event parser), instead of the old pevent.
Signed-off-by: Tzvetomir Stoyanov
---
tools/lib/traceevent/event-parse.c| 32
This patch removes trivial filter tep APIs:
enum tep_filter_trivial_type
tep_filter_event_has_trivial()
tep_update_trivial()
tep_filter_clear_trivial()
Trivial filters is an optimization, used only in the first
version of KernelShark. The API is deprecated, the next KernelShark
release does
This patch renames "struct tep_handle *pevent" input arguments of libtraceevent
APIs to "struct tep_handle *tep". This makes the API consistent with the chosen
naming convention: tep (trace event parser), instead of the old pevent.
Signed-off-by: Tzvetomir Stoyanov
---
Kmemleak could quickly fail to allocate an object structure and then
disable itself in a low-memory situation. For example, running a mmap()
workload triggering swapping and OOM. This is especially problematic for
running things like LTP testsuite where one OOM test case would disable
the whole
This patch renames from "pevent" to "tep":
- all "pevent" input arguments of libtraceevent internal functions.
- all local "pevent" variables of libtraceevent.
This makes the implementation consistent with the chosen naming convention,
tep (trace event parser), and will avoid any confusion with
This patch series does a cleanup of traceevent implementation and APIs:
- All "pevent" function parameters and local variables are renamed to "tep".
This makes the implementation consistent with the chosen naming convention,
tep (trace event parser), and avoids any confusion with the old
This patch adds a parsing failures counter to struct tep_handle. The counter can
be used to track failures on parsing event format files. It is updated
automatically by tep_parse_event(), when failure is detected. The patch also
adds two new APIs for accessing the counter:
Commit-ID: db779ef67ffeadbb44e9e818eb64dbe528e2f48f
Gitweb: https://git.kernel.org/tip/db779ef67ffeadbb44e9e818eb64dbe528e2f48f
Author: Bhupesh Sharma
AuthorDate: Tue, 26 Mar 2019 12:20:28 +0530
Committer: Borislav Petkov
CommitDate: Tue, 26 Mar 2019 16:36:03 +0100
proc/kcore: Remove
On Tue, 26 Mar 2019 12:37:37 +
"Liu, Yi L" wrote:
> > From: Alex Williamson [mailto:alex.william...@redhat.com]
> > Sent: Tuesday, March 26, 2019 2:17 AM
> > To: Liu, Yi L
> > Subject: Re: [RFC v2 1/2] vfio/pci: export common symbols in vfio-pci
> >
> > On Sat, 23 Mar 2019 11:06:44 +
>
On Mon, 2019-03-25 at 15:09 -0700, Matthew Garrett wrote:
> Systems in lockdown mode should block the kexec of untrusted kernels.
> For x86 and ARM we can ensure that a kernel is trustworthy by validating
> a PE signature, but this isn't possible on other architectures. On those
> platforms we can
On Tue, Mar 26, 2019 at 04:12:27PM +0100, Rafael J. Wysocki wrote:
> On Tue, Mar 26, 2019 at 3:41 PM Leon Romanovsky wrote:
> >
> > On Tue, Mar 26, 2019 at 01:29:54PM +0100, Rafael J. Wysocki wrote:
> > > On Tue, Mar 26, 2019 at 1:02 PM Leon Romanovsky wrote:
> > > >
> > > > From: Leon
> -Original Message-
> From: Kirti Wankhede
> Sent: Tuesday, March 26, 2019 2:06 AM
> To: Parav Pandit ; k...@vger.kernel.org; linux-
> ker...@vger.kernel.org; alex.william...@redhat.com
> Cc: Neo Jia
> Subject: Re: [PATCH 8/8] vfio/mdev: Improve the create/remove sequence
>
>
>
>
On Tue, 26 Mar 2019 08:18:15 -0700
"Paul E. McKenney" wrote:
> On Tue, Mar 26, 2019 at 08:13:11PM +0800, Yafang Shao wrote:
> > When CONFIG_RCU_TRACE is not set, all these tracepoints are defined as
> > do-nothing macro.
> > We'd better make those inline functions that take proper arguments.
> >
On Tue, 26 Mar 2019 12:36:22 +0530
Kirti Wankhede wrote:
> On 3/23/2019 4:50 AM, Parav Pandit wrote:
> > There are five problems with current code structure.
> > 1. mdev device is placed on the mdev bus before it is created in the
> > vendor driver. Once a device is placed on the mdev bus
Hi Thomas,
thanks for reviewing this patch.
[ ... ]
>> +
>> +/*
>> + * Exponential moving average computation
>> + */
>> +static int irq_timings_ema_new(s64 value, s64 ema_old)
>
> There is a mixed bag of s64/u64 all over this code. Please stay
> consistent. We had enough sign confusion bugs
These values are not referred to anywhere else in the kernel. Card
detect is controlled by the device tree property "mediatek,cd-poll",
and there is no driver support for eMMC whatsoever.
Signed-off-by: George Hilliard
---
v2: Rewrite of v1
v3: [Not present]
v4: Resubmit of v2
On Tue, 26 Mar 2019 05:53:22 +
Parav Pandit wrote:
> > -Original Message-
> > From: linux-kernel-ow...@vger.kernel.org > ow...@vger.kernel.org> On Behalf Of Parav Pandit
> > Sent: Monday, March 25, 2019 10:19 PM
> > To: Alex Williamson
> > Cc: k...@vger.kernel.org;
The module was initializing completions whenever it was going to wait on
them, and not when the completion was allocated. This is incorrect
according to the completion docs:
Calling init_completion() on the same completion object twice is
most likely a bug [...]
Re-initialization is
On Tue 2019-03-26 15:55:57, Andy Shevchenko wrote:
> On Tue, Mar 26, 2019 at 03:39:47PM +0200, Sakari Ailus wrote:
> > On Tue, Mar 26, 2019 at 03:13:53PM +0200, Andy Shevchenko wrote:
> > > On Sun, Mar 24, 2019 at 08:17:46PM +0200, Sakari Ailus wrote:
>
> > > The patch series by Petr I mentioned
Coding style fixup and rebase of v3, and resubmit of the Kconfig patch
that got dropped from v2. No other changes.
Thanks for your continued attention and reviews!
George
Hi, Vignesh
At 2019-03-19 13:22:15, "Vignesh Raghavendra" wrote:
>Hi,
>
>On 13/03/19 7:15 PM, Liu Xiang wrote:
>> In some is25lp256, the DWORD1 of JEDEC Basic Flash Parameter Header
>> is 0xfff920e5. So the DWORD1[18:17] Address Bytes bits are 0b00,
>> means that 3-Byte only addressing.
HiSilicon erratum 162001800 describes the limitation of
SMMUv3 PMCG implementation on HiSilicon Hip08 platforms.
On these platforms, the PMCG event counter registers
(SMMU_PMCG_EVCNTRn) are read only and as a result it
is not possible to set the initial counter period value
on event monitor
On 26/03/2019 06:29, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.0.5 release.
> There are 52 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
This adds support for MSI-based counter overflow interrupt.
Signed-off-by: Shameer Kolothum
Reviewed-by: Robin Murphy
---
drivers/perf/arm_smmuv3_pmu.c | 58 +++
1 file changed, 58 insertions(+)
diff --git a/drivers/perf/arm_smmuv3_pmu.c
From: Neil Leeder
Adds a new driver to support the SMMUv3 PMU and add it into the
perf events framework.
Each SMMU node may have multiple PMUs associated with it, each of
which may support different events.
SMMUv3 PMCG devices are named as smmuv3_pmcg_ where
is the physical page address of
From: Neil Leeder
Add support for the SMMU Performance Monitor Counter Group
information from ACPI. This is in preparation for its use
in the SMMUv3 PMU driver.
Signed-off-by: Neil Leeder
Signed-off-by: Hanjun Guo
Signed-off-by: Shameer Kolothum
Reviewed-by: Robin Murphy
Acked-by: Lorenzo
On 26/03/2019 06:29, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.19.32 release.
> There are 45 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
This adds a driver for the SMMUv3 PMU into the perf framework.
It includes an IORT update to support PM Counter Groups.
This is based on the initial work done by Neil Leeder[1]
SMMUv3 PMCG devices are named as smmuv3_pmcg_
where is the physical page address of the SMMU PMCG.
For example, the
On 26/03/2019 06:29, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.14.109 release.
> There are 41 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On 26/03/2019 06:29, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.9.166 release.
> There are 30 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On Tue, Mar 26, 2019 at 08:13:11PM +0800, Yafang Shao wrote:
> When CONFIG_RCU_TRACE is not set, all these tracepoints are defined as
> do-nothing macro.
> We'd better make those inline functions that take proper arguments.
>
> As RCU_TRACE() is defined as do-nothing marco as well when
>
On Tue, Mar 26, 2019 at 11:50:52PM +0900, Masami Hiramatsu wrote:
> On Mon, 25 Mar 2019 17:23:34 -0400
> Steven Rostedt wrote:
>
> > On Wed, 13 Feb 2019 01:12:44 +0900
> > Masami Hiramatsu wrote:
> >
> > > Prohibit probing on IRQ handlers in irqentry_text because
> > > if it interrupts user
On 3/26/19 15:23, Takashi Iwai wrote:
On Tue, 26 Mar 2019 12:25:37 +0100,
Timo Wischer wrote:
On 3/26/19 09:35, Takashi Iwai wrote:
On Tue, 26 Mar 2019 08:49:33 +0100,
wrote:
From: Timo Wischer
snd_pcm_link() can be called by the user as long as
Add support for Synopsys DesignWare core IP based PCIe host controller
present in Tegra194 SoC.
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc/Kconfig | 10 +
drivers/pci/controller/dwc/Makefile|1 +
drivers/pci/controller/dwc/pcie-tegra194.c | 1862
Add PCIe host controller driver for DesignWare core based
PCIe controller IP present in Tegra194.
Signed-off-by: Vidya Sagar
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index
Enable PCIe controller nodes to enable respective PCIe slots on
P2972- board. Following is the ownership of slots by different
PCIe controllers.
Controller-0 : M.2 Key-M slot
Controller-1 : On-board Marvell eSATA controller
Controller-3 : M.2 Key-E slot
Signed-off-by: Vidya Sagar
---
Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
For each PCIe lane of a controller, there is a P2U unit instantiated at
hardware level. This driver provides support for the programming required
for each
Add support for Tegra194 PCIe controllers. These controllers are based
on Synopsys DesignWare core IP.
Signed-off-by: Vidya Sagar
---
.../bindings/pci/nvidia,tegra194-pcie.txt | 209 +
.../devicetree/bindings/phy/phy-tegra194-p2u.txt | 34
2 files changed,
Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra194 SoC contains six PCIe controllers and twenty P2U instances
grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us)
and NVIDIA High Speed (NVHS-8 P2Us) respectively.
Signed-off-by: Vidya Sagar
---
Add #defines for the Data Link Feature and Physical Layer 16.0 GT/s
features.
Signed-off-by: Vidya Sagar
---
include/uapi/linux/pci_regs.h | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
move PCIe config space capability search API to common designware file
as this can be used by both host and ep mode codes.
It also adds extended capability search APIs.
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 37 +
save pci_bus pointer created by PCIe sub-system's
pci_scan_root_bus_bridge() to be used by host controller drivers for post
processing. Tegra host controller driver needs it for the following
reasons
- to derive pci_host_bridge structure from pci_bus which is used to
configure iATU's outbound
Remove multiple write enable and disable sequences of dbi registers as
Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by
DBI write-lock enable bit thereby not allowing any further writes to BAR-0
register in config space to take place. Hence disabling write permission
only
Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
UPHY lanes from
On Fri 2019-03-22 17:29:30, Sakari Ailus wrote:
> Add support for %pfw conversion specifier (with "f" and "P" modifiers) to
> support printing full path of the node, including its name ("f") and only
> the node's name ("P") in the printk family of functions. The two flags
> have equivalent
On 03/23, Thomas Gleixner wrote:
>
> On Thu, 28 Feb 2019, Gustavo A. R. Silva wrote:
>
> > arch/x86/include/asm/syscall.h | 28
> > 1 file changed, 28 insertions(+)
>
> Second thoughts. So this adds 28 /* fall through */ comments. Now I
> appreciate the effort, but
Le 19/03/2019 à 14:20, Razvan Stefanescu a écrit :
> In half-duplex operation, RX should be started after TX completes.
>
> If DMA is used, there is a case when the DMA transfer completes but the
> TX FIFO is not emptied, so the RX cannot be restarted just yet.
>
> Use a boolean variable to
On Wed, 2019-03-20 at 20:50 -0400, Richard Guy Briggs wrote:
> On 2019-03-20 19:48, Paul Moore wrote:
> > On Sat, Mar 16, 2019 at 8:10 AM Richard Guy Briggs wrote:
> > > In commit fa516b66a1bf ("EVM: Allow runtime modification of the set of
> > > verified xattrs"), the call to audit_log_start()
On Thu, 28 Feb 2019 12:31:53 +0530, Naga Sureshkumar Relli wrote:
> This patch adds the dts binding document for Zynq SOC QSPI
> controller.
>
> Signed-off-by: Naga Sureshkumar Relli
> ---
> .../devicetree/bindings/spi/spi-zynq-qspi.txt | 25
> ++
> 1 file changed, 25
On Tue, Mar 26, 2019 at 3:41 PM Leon Romanovsky wrote:
>
> On Tue, Mar 26, 2019 at 01:29:54PM +0100, Rafael J. Wysocki wrote:
> > On Tue, Mar 26, 2019 at 1:02 PM Leon Romanovsky wrote:
> > >
> > > From: Leon Romanovsky
> > >
> > > Kernel is booted with less possible CPUs (possible_cpus kernel
On 3/26/19 4:45 AM, Adrian Hunter wrote:
Hi
Doing:
make -C tools clean
Results in:
git diff --stat
tools/pci/pcitest.sh | 72
tools/testing/selftests/livepatch/test-callbacks.sh | 587
On Sat, Mar 02, 2019 at 11:06:36PM +, Colin King wrote:
> From: Colin Ian King
>
> The non-null check on udata is redundant as this check was performed
> just a few statements earlier and the check is always true as udata
> must be non-null at this point. Remove redundant the check on udata
Le 19/03/2019 à 14:20, Razvan Stefanescu a écrit :
> Use a helper function to check that a port needs to use half duplex
> communication, replacing several occurrences of multi-line bit checking.
>
> Fixes: b389f173aaa1 ("tty/serial: atmel: RS485 half duplex w/DMA: enable
> RX after TX is done")
Add an mfd driver for Intel Merrifield Basin Cove PMIC.
Signed-off-by: Andy Shevchenko
---
- corrected name of Power Source detection driver
drivers/mfd/Kconfig | 11 ++
drivers/mfd/Makefile | 1 +
drivers/mfd/intel_soc_pmic_mrfld.c | 157
> On 26 Mar 2019, at 15:48, Vitaly Kuznetsov wrote:
>
> Liran Alon writes:
>
>>> On 26 Mar 2019, at 15:07, Vitaly Kuznetsov wrote:
>>> - Instread of putting the temporary HF_SMM_MASK drop to
>>> rsm_enter_protected_mode() (as was suggested by Liran), move it to
>>> emulator_set_cr()
Andi,
On Mon, 25 Mar 2019, Andi Kleen wrote:
> >So on user space to kernel space transitions swapping in kernel GS should
> >simply do:
> > userGS = RDGSBASE()
> > WRGSBASE(kernelGS)
>
> This would also need to find kernelGS first, by doing RDPID and then
> reading it from
On Mon, Feb 25, 2019 at 10:59:19PM -0800, Bjorn Andersson wrote:
> qcom_qmp_phy_init() is extended to support the additional register
> writes needed in PCS MISC and the appropriate sequences and resources
> are defined for SDM845.
>
> Signed-off-by: Bjorn Andersson
> ---
>
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