Once boosting value is 0, then further consecutive-down events won't do
anything useful since the only purpose of those consecutive events to
boost the freq and de-boosting is over in the case of 0. Note that upper
watermark is infinitely high in a case of frequency max out and thus the
upper
Extend event signature matching to catch more input devices emulated by
BMC firmwares, QEMU and VMware.
Signed-off-by: Alexander Tsoy
---
drivers/input/joydev.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/input/joydev.c
Hi all,
Today's linux-next merge of the netfilter-next tree got conflicts in:
include/linux/netfilter/ipset/ip_set.h
include/linux/netfilter/ipset/ip_set_counter.h
include/linux/netfilter/ipset/ip_set_skbinfo.h
include/linux/netfilter/ipset/ip_set_timeout.h
This patch adds system suspend and resume support for Tegra210
clocks.
All the CAR controller settings are lost on suspend when core power
goes off.
This patch has implementation for saving and restoring all the PLLs
and clocks context during system suspend and resume to have the
clocks back to
This patch updates device tree for RTC and PMC to allow system wake
from deep sleep on RTC alarm.
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
This patch adds support for storing OSC clock frequency and the
drive-strength during OSC clock init and creates an API to restore
OSC control register value from the saved context.
This API is invoked by Tegra210 clock driver during system resume
to restore the OSC clock settings.
Acked-by:
This patch implements save and restore context for peripheral fixed
clock ops, peripheral gate clock ops, sdmmc mux clock ops, and
peripheral clock ops.
During system suspend, core power goes off and looses the settings
of the Tegra CAR controller registers.
So during suspend entry clock and
This patch implements save and restore of pllout context.
During system suspend, core power goes off and looses the settings
of the Tegra CAR controller registers.
So during suspend entry the state of pllout is saved and on resume
it is restored back to have pllout in same state as before
This patch uses fence_udelay rather than udelay during PLLU
initialization to ensure writes to clock registers happens before
waiting for specified delay.
Signed-off-by: Sowjanya Komatineni
---
drivers/clk/tegra/clk-tegra210.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
This patch has Jetson TX1 platform specific SC7 timing configuration
in device tree.
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
This patch allows to create separate irq_set_wake and irq_set_type
implementations for different tegra designs PMC that has different
wake models which require difference wake registers and different
programming sequence.
AOWAKE model support is available for Tegra186 and Tegra194 only
and it
This patch configures polarity of the core power request signal
in PMC control register based on the device tree property.
PMC asserts and de-asserts power request signal based on it polarity
when it need to power-up and power-down the core rail during SC7.
Signed-off-by: Sowjanya Komatineni
Tegra210 and prior Tegra chips have deep sleep entry and wakeup related
timings which are platform specific that should be configured before
entering into deep sleep.
Below are the timing specific configurations for deep sleep entry and
wakeup.
- Core rail power-on stabilization timer
- OSC clock
This patch implements PMC wakeup sequence for Tegra210 and defines
common used RTC alarm wake event.
Signed-off-by: Sowjanya Komatineni
---
drivers/soc/tegra/pmc.c | 111
1 file changed, 111 insertions(+)
diff --git a/drivers/soc/tegra/pmc.c
During system suspend state, core power goes off and looses all the
CAR controller register settings.
This patch creates APIs for saving and restoring the context of Tegra
CPUG, CPULP and SCLK.
CPU and System clock context includes
- CPUG, CPULP, and SCLK burst policy settings for clock sourcea
Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry
sequence and sc7 entry firmware is run from COP/BPMP-Lite.
So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence
for Tegra210.
This patch has fix for leaving the COP IRQ enabled for Tegra210 during
During SC7 resume, PARKED bit clear from the pinmux registers may
cause a glitch on the GPIO lines.
So, Tegra GPIOs restore should happen prior to restoring Tegra pinmux
to keep the GPIO lines in a known good state prior to clearing PARKED
bit.
This patch has fix for this by moving Tegra GPIOs
This patch adds support for Tegra pinctrl driver suspend and resume.
During suspend, context of all pinctrl registers are stored and
on resume they are all restored to have all the pinmux and pad
configuration for normal operation.
Signed-off-by: Sowjanya Komatineni
---
This patch series includes Tegra210 deepsleep support with RTC alarm
wake event.
This series also includes save and restore of PLLs, clocks, OSC contexts
for deepsleep exit to normal operation.
This patch series doesn't support 100% suspend/resume to allow fully
functional state upon resume and
This patch creates APIs for supporting Tegra210 clock driver to
perform DFLL suspend and resume operation.
During suspend, DFLL mode is saved and on resume Tegra210 clock driver
invokes DFLL resume API to re-initialize DFLL to enable target device
clock in open loop mode or closed loop mode.
This patch implements context save and restore for clock divider.
During system suspend, core power goes off and looses the settings
of the Tegra CAR controller registers.
So during suspend entry the context of clock divider is saved and
on resume context is restored back for normal operation.
This patch implements save and restore of PLL context.
During system suspend, core power goes off and looses the settings
of the Tegra CAR controller registers.
So during suspend entry pll rate is stored and on resume it is
restored back along with its state.
Acked-by: Thierry Reding
On Wed, 19 Jun 2019, Fenghua Yu wrote:
> C0.2 state in umwait and tpause instructions can be enabled or disabled
> on a processor through IA32_UMWAIT_CONTROL MSR register.
through the IA32CONTROL MSR.
MSR register, IOW: Machine Specific Register register.
>
> Andy Lutomirski suggests to
Sasha,
On Sun, 23 Jun 2019, Sasha Levin wrote:
> On Sat, Jun 22, 2019 at 04:46:28PM +0200, Thomas Gleixner wrote:
> > Folks, please stop chosing Cc lists as you like. We have well established
> > rules for that. And please stop queueing random unreviewed patches in
> > next. Next is not a
On Sun, 23 Jun 2019, Andy Lutomirski wrote:
>
> > On Jun 23, 2019, at 6:10 AM, Thomas Gleixner wrote:
> >
> >> On Sun, 23 Jun 2019, Linus Torvalds wrote:
> >>
> >> Andy added comments and changed the patch in other ways too, so I think
> >> it's fine to have him as author, and my sign-off is
On Wed, 19 Jun 2019, Fenghua Yu wrote:
>
> +#define MSR_IA32_UMWAIT_CONTROL 0xe1
> +#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLED BIT(0)
> +#define MSR_IA32_UMWAIT_CONTROL_MAX_TIME 0xfffc
Errm, no! That's not maxtime, that's the time field mask in the
MSR. Throughout
On Wed, 19 Jun 2019, Fenghua Yu wrote:
> +Description: Umwait control
> +
> + enable_c02: Read/write interface to control umwait C0.2 state
> + Read returns C0.2 state status:
> + 0: C0.2 is disabled
> + 1:
Vincenzo,
On Fri, 21 Jun 2019, Vincenzo Frascino wrote:
> vDSO (virtual dynamic shared object) is a mechanism that the Linux
> kernel provides as an alternative to system calls to reduce where
> possible the costs in terms of cycles.
> This is possible because certain syscalls like gettimeofday()
On Wed, 19 Jun 2019, Fenghua Yu wrote:
> Users can write an unsigned 32-bit number to
> /sys/devices/system/cpu/umwait_control/max_time to change the default
Users? Administrators can. Users NOT.
> value. Note that a value of zero means there is no limit. Low order
> two bits must be zero.
...
On Mon, 24 Jun 2019, Thomas Gleixner wrote:
> On Wed, 19 Jun 2019, Fenghua Yu wrote:
> > +Description: Umwait control
> > +
> > + enable_c02: Read/write interface to control umwait C0.2 state
> > + Read returns C0.2 state status:
> > + 0:
On Mon, 24 Jun 2019, Michael Kelley wrote:
> From: Thomas Gleixner Sent: Sunday, June 23, 2019 3:13 PM
> >
> > I have no objections if you collect hyper-v stuff, quite the contrary, but
> > changes which touch other subsystems need to be coordinated upfront. That's
> > all I'm asking for.
> >
>
The autonuma scan period should be increased (scanning is slowed down)
if the majority of the page accesses are shared with other processes.
But in current code, the scan period will be decreased (scanning is
speeded up) in that situation.
This patch fixes the code. And this has been tested via
Hi Frank,
Thank you for your comment!
On Sun, 23 Jun 2019 12:58:45 -0700
Frank Rowand wrote:
> Hi Masami,
>
> On 6/21/19 9:18 AM, Masami Hiramatsu wrote:
> > Hi,
> >
> > Here is an RFC series of patches to add boot-time tracing using
> > devicetree.
> >
> > Currently, kernel support
Hi Sasha,
On Sun, 23 Jun 2019 15:09:29 -0400 Sasha Levin wrote:
>
> Appologies about this. I ended up with way more travel than I would have
> liked (writing this from an airport). I've reset our hyperv-next branch
> to remove these 3 commits until we figure this out.
But not pushed out, yet?
On Sun, 2019-06-23 at 23:15 +0200, Fabian Schindlatz wrote:
> Fix some warnings and one error reported by checkpatch.pl:
[]
> diff --git a/drivers/bluetooth/hci_ll.c b/drivers/bluetooth/hci_ll.c
[]
> @@ -351,7 +356,8 @@ static int ll_enqueue(struct hci_uart *hu, struct sk_buff
> *skb)
>
On Fri, Jun 21, 2019 at 08:42:48AM +, Robin Gong wrote:
> Hello Shawn/Will,
> Do you have comments for this V5 patch set? I got tags from Mark,
> Vinod and Rob.
I'm fine with the DTS change, but not sure how the series should be
merged.
Shawn
>
> On 2019-06-10 at 08:17 +,
Hi all,
In commit
d0bb82fd6018 ("net: stmmac: set IC bit when transmitting frames with HW
timestamp")
Fixes tag
Fixes: f748be531d70 ("net: stmmac: Rework coalesce timer and fix multi-queue
races")
has these problem(s):
- Subject does not match target commit subject
Just use
On 19. 6. 8. 오전 6:24, Linus Walleij wrote:
> On Tue, Jun 4, 2019 at 3:30 AM Chanwoo Choi wrote:
>> On 19. 5. 31. 오전 3:39, Linus Walleij wrote:
>
>>> + /*
>>> + * It is unlikely that this is an acknowledged interrupt that goes
>>> + * away after handling, what we are looking for are
Hi, Shawn
> -Original Message-
> From: Shawn Guo
> Sent: Monday, June 24, 2019 10:27 AM
> To: Anson Huang
> Cc: mark.rutl...@arm.com; Aisheng Dong ; Peng
> Fan ; feste...@gmail.com; Jacky Bai
> ; devicet...@vger.kernel.org; sb...@kernel.org;
> catalin.mari...@arm.com;
The driver expects certain debug features to be disabled in order to
work properly. Let's disable them explicitly for consistency and to not
rely on a boot state.
Acked-by: Peter De Schrijver
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 17 -
1 file
Hi all,
Today's linux-next merge of the arm-soc tree got a conflict in:
arch/arm/include/debug/netx.S
between commit:
d2912cb15bdd ("treewide: Replace GPLv2 boilerplate/reference with SPDX - rule
500")
from Linus' tree and commit:
ceb02dcf676f ("ARM: delete netx machine")
from the
Since commit 4bfc0bb2c60e ("bpf: decouple the lifetime of cgroup_bpf
from cgroup itself"), cgroup_bpf release occurs asynchronously
(from a worker context), and before the release of the cgroup itself.
This introduced a previously non-existing race between the release
and update paths. E.g. if a
Add device-tree binding for NVIDIA Tegra30 External Memory Controller.
The binding is based on the Tegra124 EMC binding since hardware is
similar, although there are couple significant differences.
Note that the memory timing description is given in a platform-specific
form because there is no
Hello,
This series introduces driver for the External Memory Controller (EMC)
found on Tegra30 chips, it controls the external DRAM on the board. The
purpose of this driver is to program memory timing for external memory on
the EMC clock rate change. The driver was tested using the ACTMON devfreq
On Mon, Jun 24, 2019 at 10:22:01AM +0800, Shawn Guo wrote:
> On Fri, Jun 21, 2019 at 03:07:17PM +0800, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > ARCH_MXC platforms needs system counter as broadcast timer
> > to support cpuidle, enable it by default.
> >
> > Signed-off-by: Anson
A proper External Memory Controller clock rounding and parent selection
functionality is required by the EMC drivers, it is not available using
the generic clock implementation because only the Memory Controller driver
is aware of what clock rates are actually available for a particular
device.
Hi, Shawn
> -Original Message-
> From: Shawn Guo
> Sent: Monday, June 24, 2019 10:22 AM
> To: Anson Huang
> Cc: catalin.mari...@arm.com; w...@kernel.org; robh...@kernel.org;
> mark.rutl...@arm.com; s.ha...@pengutronix.de; ker...@pengutronix.de;
> feste...@gmail.com;
From: Huang Ying
0-Day test system reported some OOM regressions for several
THP (Transparent Huge Page) swap test cases. These regressions are
bisected to 6861428921b5 ("block: always define BIO_MAX_PAGES as
256"). In the commit, BIO_MAX_PAGES is set to 256 even when THP swap
is enabled. So
Introduce driver for the External Memory Controller (EMC) found on Tegra30
chips, it controls the external DRAM on the board. The purpose of this
driver is to program memory timing for external memory on the EMC clock
rate change.
Acked-by: Peter De Schrijver
Signed-off-by: Dmitry Osipenko
---
24.06.2019 2:50, Chanwoo Choi пишет:
> Hi Dmitry,
>
> On 19. 6. 24. 오전 2:17, Dmitry Osipenko wrote:
>> 05.06.2019 2:09, Dmitry Osipenko пишет:
>>> 04.06.2019 3:49, Chanwoo Choi пишет:
On 19. 6. 4. 오전 1:52, Dmitry Osipenko wrote:
> 03.05.2019 3:52, Dmitry Osipenko пишет:
>> 03.05.2019
Timing control debug features should be disabled at a boot time, but you
never now and hence it's better to disable them explicitly because some of
those features are crucial for the driver to do a proper thing.
Acked-by: Peter De Schrijver
Signed-off-by: Dmitry Osipenko
---
On 19. 6. 21. 오후 8:13, Paweł Chmiel wrote:
> This small patchset adds support for Fairchild Semiconductor FSA9480
> microUSB switch.
>
> It has been tested on Samsung Galaxy S and Samsung Fascinate 4G,
> but it can be found also on other Samsung Aries (s5pv210) based devices.
>
> Tomasz Figa
On Fri, Jun 21, 2019 at 03:07:17PM +0800, anson.hu...@nxp.com wrote:
> From: Anson Huang
>
> ARCH_MXC platforms needs system counter as broadcast timer
> to support cpuidle, enable it by default.
>
> Signed-off-by: Anson Huang
> ---
> arch/arm64/Kconfig.platforms | 1 +
> 1 file changed, 1
The memory frequency scaling will be managed by tegra20-devfreq driver
and PM QoS once all the prerequisite patches will get upstreamed.
The parent clock is now managed by the clock driver and we also should
assume that PLLM rate can't be changed on some devices (Galaxy Tab 10.1
for example).
On Fri, Jun 21, 2019 at 01:06:03PM +0800, anson.hu...@nxp.com wrote:
> From: Anson Huang
>
> Enable CONFIG_KEYBOARD_SNVS_PWRKEY as module to support i.MX8M
> series SoCs' power key.
>
> Signed-off-by: Anson Huang
Applied, thanks.
On Wed, Jun 19, 2019 at 12:05:16AM +0300, Daniel Baluta wrote:
> lsio_mu13 node is used to communicate with DSP.
>
> Signed-off-by: Daniel Baluta
Applied, thanks.
On Fri, Jun 21, 2019 at 10:48:25AM -0700, Andi Kleen wrote:
> On Fri, Jun 14, 2019 at 01:28:53PM +0200, Jiri Olsa wrote:
> > hi,
> > the HPE server can do POST tracing and have enabled LBR
> > tracing during the boot, which makes check_msr fail falsly.
> >
> > It looks like check_msr code was
Hi Dmitry,
On 19. 6. 24. 오전 2:17, Dmitry Osipenko wrote:
> 05.06.2019 2:09, Dmitry Osipenko пишет:
>> 04.06.2019 3:49, Chanwoo Choi пишет:
>>> On 19. 6. 4. 오전 1:52, Dmitry Osipenko wrote:
03.05.2019 3:52, Dmitry Osipenko пишет:
> 03.05.2019 3:31, Chanwoo Choi пишет:
>> Hi Dmitry,
On Sat, Jun 22, 2019 at 04:01:40PM +0530, Keerthy wrote:
Hi Keerty,
Commit bfe59032bd6127ee190edb30be9381a01765b958 ("net: ethernet:
ti: cpsw: use cpsw as drv data")changes
the driver data to struct cpsw_common *cpsw. This is done
only in probe/remove but the suspend/resume functions are
still
>IRQ numbers are always positive, hence the corresponding variable should
>be unsigned to keep types consistent. This is a minor change that cleans
>up code a tad more.
>
>Suggested-by: Thierry Reding
>Signed-off-by: Dmitry Osipenko
Acked-by: MyungJoo Ham
Cheers,
MyungJoo
Now Terga20 and Tegra30 EMC drivers should provide clock-rounding
functionality using the new Tegra-CLK driver API.
Acked-by: Peter De Schrijver
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 50 --
1 file changed, 48 insertions(+), 2
On 6/23/19 6:40 PM, Jiri Olsa wrote:
> On Fri, Jun 21, 2019 at 10:48:25AM -0700, Andi Kleen wrote:
>> On Fri, Jun 14, 2019 at 01:28:53PM +0200, Jiri Olsa wrote:
>>> hi,
>>> the HPE server can do POST tracing and have enabled LBR
>>> tracing during the boot, which makes check_msr fail falsly.
>>>
Hello
Does anyone have any comments on this ?
> Add the device-tree binding documentation for Milbeaut SDHCI driver.
>
> Signed-off-by: Takao Orito
> ---
> .../devicetree/bindings/mmc/sdhci-milbeaut.txt | 32
> ++
> 1 file changed, 32 insertions(+)
> create mode
On Thu, Jun 20, 2019 at 11:05:32AM -0600, Angus Ainslie (Purism) wrote:
> Enable the snvs power key.
>
> Signed-off-by: Angus Ainslie (Purism)
Applied, thanks.
On Thu, Jun 20, 2019 at 11:04:39AM -0600, Angus Ainslie (Purism) wrote:
> The charge controller can handle 14V but the PTC on the devkit can only
> handle 6V so limit the negotiated voltage to 5V.
>
> Signed-off-by: Angus Ainslie (Purism)
Prefix 'arm64: dts: librem5: ...' should be fine, so I
The consecutive-down event tells that we should perform frequency
de-boosting, but boosting is in a reset state on start and hence the
event won't do anything useful for us and it will be just a dummy
interrupt request.
Signed-off-by: Dmitry Osipenko
---
drivers/devfreq/tegra30-devfreq.c | 1 -
On 19. 6. 24. 오전 4:16, Krzysztof Kozlowski wrote:
> On Sun, 23 Jun 2019 at 06:31, Chanwoo Choi wrote:
>>
>> Hi Krzysztof,
>>
>> 2019년 6월 23일 (일) 오전 4:20, Krzysztof Kozlowski 님이 작성:
>>>
>>> Enable support for Mali GPU with Panfrost and Lima drivers for:
>>> 1. Samsung Exynos5433 and Exynos7
The current implementation is inaccurate and results in very intensive
interrupt activity, which neglects the whole idea of polling offload to
hardware. The reason of the shortcoming is that watermarks are not set
up correctly and this results in ACTMON constantly asking to change freq
and then
The register polling code was gone, but the included header change was
missed. Fix it up for consistency.
Acked-by: Peter De Schrijver
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 6/22/19 6:27 AM, Stanislav Fomichev wrote:
On 06/21, Andrii Nakryiko wrote:
)
On Fri, Jun 21, 2019 at 9:11 AM Stanislav Fomichev wrote:
On 06/21, kernel test robot wrote:
FYI, we noticed the following commit (built with gcc-7):
commit: 69d96519dbf0bfa1868dc8597d4b9b2cdeb009d7
Add External Memory Controller node to the device-tree.
Acked-by: Peter De Schrijver
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index
There is no real need to keep interrupt always-enabled, will be nicer
to keep it disabled where appropriate.
Suggested-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
drivers/devfreq/tegra30-devfreq.c | 43 ---
1 file changed, 22 insertions(+), 21 deletions(-)
Governor could be stopped while boosting is active. We have assumption
that everything is reset on governor's restart, including the boosting
value, which was missed.
Signed-off-by: Dmitry Osipenko
---
drivers/devfreq/tegra30-devfreq.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
Hi all,
Today's linux-next merge of the hwmon-staging tree got a conflict in:
drivers/hwmon/iio_hwmon.c
between commit:
d2912cb15bdd ("treewide: Replace GPLv2 boilerplate/reference with SPDX - rule
500")
from Linus' tree and commit:
2119f92b6b66 ("hwmon: Convert remaining drivers to
Hi Sasha,
On Sun, 23 Jun 2019 20:24:30 -0400 Sasha Levin wrote:
>
> Pushed now. For some reason the airport wifi was blocking ssh :/
Thanks.
--
Cheers,
Stephen Rothwell
pgpTHy1b84gSj.pgp
Description: OpenPGP digital signature
The EMC clock rate rounding technically could fail, hence let's handle
the error cases properly.
Signed-off-by: Dmitry Osipenko
---
drivers/devfreq/tegra30-devfreq.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/devfreq/tegra30-devfreq.c
On Fri, Jun 21, 2019 at 11:01:25AM +0200, Daniel Vetter wrote:
> On Thu, Jun 20, 2019 at 04:40:12PM +0200, Neil Armstrong wrote:
> > Hi Andrzej,
> >
> > Gentle ping, could you review the dw-hdmi changes here ?
>
> btw not sure you absolutely need review from Andrzej, we're currently a
> bit
There is no need in a write-barrier now, given that interrupt masking is
handled by CPU's GIC now. Hence we know exactly that interrupt won't fire
after stopping the devfreq's governor. In other cases we don't care about
potential buffering of the writes to hardware and thus there is no need to
On 06/24/19 at 09:35am, Dave Young wrote:
> On 06/23/19 at 06:24am, Tiezhu Yang wrote:
> > Fix the following sparse warning:
> >
> > arch/x86/kernel/crash.c:59:15:
> > warning: symbol 'crash_zero_bytes' was not declared. Should it be static?
> >
> > First, make crash_zero_bytes static. In
On Sun, Jun 23, 2019 at 5:34 PM Thomas Gleixner wrote:
> +GENERIC VDSO LIBRARY:
> +M: Andy Lutomirksy
Lutomirski, perhaps? Although I do appreciate the opportunity to say
"not me!" :)
> Hi all,
>
> In commit
>
> d0bb82fd6018 ("net: stmmac: set IC bit when transmitting frames with
> HW timestamp")
>
> Fixes tag
>
> Fixes: f748be531d70 ("net: stmmac: Rework coalesce timer and fix
> multi-queue races")
>
> has these problem(s):
>
> - Subject does not match target
On Sat, Jun 22, 2019 at 2:13 AM Ira Weiny wrote:
>
> On Fri, Jun 21, 2019 at 06:15:16PM +0800, Pingfan Liu wrote:
> > Both hugetlb and thp locate on the same migration type of pageblock, since
> > they are allocated from a free_list[]. Based on this fact, it is enough to
> > check on a single
Add debug messages to know about what's happening in hardware and how
driver reacts.
Signed-off-by: Dmitry Osipenko
---
drivers/devfreq/tegra30-devfreq.c | 33 +++
1 file changed, 33 insertions(+)
diff --git a/drivers/devfreq/tegra30-devfreq.c
IRQ numbers are always positive, hence the corresponding variable should
be unsigned to keep types consistent. This is a minor change that cleans
up code a tad more.
Suggested-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
drivers/devfreq/tegra30-devfreq.c | 8
1 file changed,
On Wed, Jun 19, 2019 at 1:35 AM Rafael J. Wysocki wrote:
>
> On Wed, Jun 19, 2019 at 1:52 AM Joel Fernandes wrote:
> >
> > On Tue, Jun 18, 2019 at 7:15 PM Tri Vo wrote:
> > [snip]
> > > > > > >
> > > > > > > Android userspace reading wakeup_sources is not ideal because:
> > > > > > > - Debugfs
From: Thomas Gleixner Sent: Sunday, June 23, 2019 3:13 PM
>
> I have no objections if you collect hyper-v stuff, quite the contrary, but
> changes which touch other subsystems need to be coordinated upfront. That's
> all I'm asking for.
>
> Btw, that clocksource stuff looks good code wise, just
On Mon, Jun 17, 2019 at 08:30:24AM -0700, Andrey Smirnov wrote:
> Add support for ZII's i.MX7 based Remote Modem Unit 2 (RMU2) board.
>
> Signed-off-by: Andrey Smirnov
> Cc: Shawn Guo
> Cc: Rob Herring
> Cc: Chris Healy
> Cc: Lucas Stach
> Cc: Fabio Estevam
> Cc: Bob Langer
> Cc: Liang Pan
On Wed, Jun 19, 2019 at 09:07:08AM +0800, anson.hu...@nxp.com wrote:
> From: Anson Huang
>
> This patch adds i.MX8MN SoC driver support:
>
> root@imx8mnevk:~# cat /sys/devices/soc0/family
> Freescale i.MX
>
> root@imx8mnevk:~# cat /sys/devices/soc0/machine
> NXP i.MX8MNano DDR4 EVK board
>
>
Hi all,
On Thu, 20 Jun 2019 11:41:26 +1000 Stephen Rothwell
wrote:
>
> After merging the fbdev tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> x86_64-linux-gnu-ld: drivers/gpu/vga/vga_switcheroo.o: in function
> `vga_switchto_stage2':
>
Hi Felipe,
On Monday, June 17, 2019 20:53, Felipe Balbi wrote:
> Hi,
>
> Ran Wang writes:
> > Hi Felipe,
> >
> > On Thursday, May 30, 2019 17:09, Ran Wang wrote:
> >>
> >>
> >> > >> >> > /* Global Debug Queue/FIFO Space Available Register */
> >> > >> >> > #define DWC3_GDBGFIFOSPACE_NUM(n)
On Wed, Jun 19, 2019 at 03:12:39PM +0800, anson.hu...@nxp.com wrote:
> From: Anson Huang
>
> Some of i.MX SoCs' clock driver use platform driver model,
> and they need to call imx_register_uart_clocks() API, so
> imx_register_uart_clocks() API should NOT be in .init section.
>
> Signed-off-by:
Commit-ID: bd9a0c97e53c3d7a56b2751179903ddc5da42683
Gitweb: https://git.kernel.org/tip/bd9a0c97e53c3d7a56b2751179903ddc5da42683
Author: Fenghua Yu
AuthorDate: Wed, 19 Jun 2019 18:33:57 -0700
Committer: Thomas Gleixner
CommitDate: Mon, 24 Jun 2019 01:44:20 +0200
x86/umwait: Add sysfs
Commit-ID: ecf9db3d1f1a8fd2c335148891c3b044e9ce0628
Gitweb: https://git.kernel.org/tip/ecf9db3d1f1a8fd2c335148891c3b044e9ce0628
Author: Andy Lutomirski
AuthorDate: Sat, 22 Jun 2019 15:08:18 -0700
Committer: Thomas Gleixner
CommitDate: Mon, 24 Jun 2019 01:21:31 +0200
x86/vdso: Give the
Commit-ID: 6dbbf5ec9e1e9f607a4c51266d0f9a63ba754b63
Gitweb: https://git.kernel.org/tip/6dbbf5ec9e1e9f607a4c51266d0f9a63ba754b63
Author: Fenghua Yu
AuthorDate: Wed, 19 Jun 2019 18:33:54 -0700
Committer: Thomas Gleixner
CommitDate: Mon, 24 Jun 2019 01:44:19 +0200
x86/cpufeatures:
I was contributing to the NVIDIA Tegra30+ devfreq driver recently and want
to help keep it working and evolving in the future.
Signed-off-by: Dmitry Osipenko
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6c203278700f..ac347278f1fc
Commit-ID: f14d8025d263f3c8236775df724a7c1f14e0dc94
Gitweb: https://git.kernel.org/tip/f14d8025d263f3c8236775df724a7c1f14e0dc94
Author: Vincenzo Frascino
AuthorDate: Fri, 21 Jun 2019 10:52:35 +0100
Committer: Thomas Gleixner
CommitDate: Sat, 22 Jun 2019 21:21:07 +0200
arm64: compat:
Commit-ID: ff4b353f2ef9dc8e396d7cb9572801e34a8c7374
Gitweb: https://git.kernel.org/tip/ff4b353f2ef9dc8e396d7cb9572801e34a8c7374
Author: Fenghua Yu
AuthorDate: Wed, 19 Jun 2019 18:33:56 -0700
Committer: Thomas Gleixner
CommitDate: Mon, 24 Jun 2019 01:44:20 +0200
x86/umwait: Add sysfs
Commit-ID: bfe801ebe84f42b4666d3f0adde90f504d56e35b
Gitweb: https://git.kernel.org/tip/bfe801ebe84f42b4666d3f0adde90f504d56e35b
Author: Vincenzo Frascino
AuthorDate: Fri, 21 Jun 2019 10:52:42 +0100
Committer: Thomas Gleixner
CommitDate: Sat, 22 Jun 2019 21:21:09 +0200
arm64: vdso:
On 06/23/19 at 06:24am, Tiezhu Yang wrote:
> Fix the following sparse warning:
>
> arch/x86/kernel/crash.c:59:15:
> warning: symbol 'crash_zero_bytes' was not declared. Should it be static?
>
> First, make crash_zero_bytes static. In addition, crash_zero_bytes
> is used when CONFIG_KEXEC_FILE is
Hello,
This series is a followup to [1] which addresses some additional review
comments that were made by Thierry Reding to [1] and makes several
important changes to the driver, fixing excessive interrupts activity.
In the end I'm proposing myself as a maintainer for the driver.
[1]
101 - 200 of 407 matches
Mail list logo
