Add the SDHI devices nodes to the R8A7742 device tree.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian Rotariu
---
arch/arm/boot/dts/r8a7742.dtsi | 60 ++
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi
Document RZ/G1H (R8A7742) SoC bindings.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian Rotariu
---
Documentation/devicetree/bindings/net/renesas,ether.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/renesas,ether.yaml
Add the sata devices nodes to the R8A7742 device tree.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian Rotariu
---
arch/arm/boot/dts/r8a7742.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi
Add Ethernet AVB support for R8A7742 SoC.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian Rotariu
---
arch/arm/boot/dts/r8a7742.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index
RZ/G1H (R8A7742) watchdog implementation is compatible with R-Car Gen2,
therefore add relevant documentation.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian Rotariu
---
Documentation/devicetree/bindings/watchdog/renesas,wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
On Thu, May 14, 2020 at 09:54:15AM +0300, Heikki Krogerus wrote:
> On Wed, May 13, 2020 at 04:14:51PM -0700, Randy Dunlap wrote:
> > On 5/13/20 2:30 PM, Brendan Higgins wrote:
> > > On Wed, May 13, 2020 at 8:18 AM Heikki Krogerus
> > > wrote:
> > >>
> > >> In the function kobject_cleanup(),
Document APMU and SMP enable method for RZ/G1H (also known as r8a7742)
SoC.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian Rotariu
---
Documentation/devicetree/bindings/power/renesas,apmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
Define the generic R8A7742 part of the Ether device node.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian Rotariu
---
arch/arm/boot/dts/r8a7742.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
Document SDHI controller for RZ/G1H (R8A7742) SoC, which is compatible
with R-Car Gen2 SoC family.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian Rotariu
---
Documentation/devicetree/bindings/mmc/renesas,sdhi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Add support for r8a7742 SoC. Renesas RZ/G1H (R8A7742) SDHI is identical to
the R-Car Gen2 family.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian Rotariu
---
drivers/mmc/host/renesas_sdhi_sys_dmac.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Add the I2C[0-3] and IIC[0-3] devices nodes to the R8A7742 device tree.
Automatic transmission for PMIC control is not available on IIC3 hence
compatible string "renesas,rcar-gen2-iic" and "renesas,rmobile-iic" is
not added to iic3 node.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian
Document i2c controller for RZ/G1H (R8A7742) SoC, which is compatible
with R-Car Gen2 SoC family.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian Rotariu
---
Documentation/devicetree/bindings/i2c/renesas,i2c.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Steven Rostedt writes:
> On Tue, 12 May 2020 23:01:03 +0200
> Thomas Gleixner wrote:
>
>> --- a/arch/x86/kernel/cpu/mce/core.c
>> +++ b/arch/x86/kernel/cpu/mce/core.c
>> @@ -1916,7 +1916,7 @@ static __always_inline void exc_machine_
>> mce_check_crashing_cpu())
>> return;
On 15/05/2020 16:43, Srinivas Pandruvada wrote:
> On Fri, 2020-05-15 at 16:10 +0200, Daniel Lezcano wrote:
>> Initially the thermal framework had a very simple notification
>> mechanism to send generic netlink messages to the userspace.
>>
>> The notification function was never called from
Document IIC controller for RZ/G1H (R8A7742) SoC, which is compatible
with R-Car Gen2 SoC family.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian Rotariu
---
Documentation/devicetree/bindings/i2c/renesas,iic.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
…
> new_blkg = blkg_alloc(pos, q, GFP_KERNEL);
…
I suggest to omit the source code quotation from the change description.
> if calling blkg_lookup_check() failed, at the IS_ERR block,
> the new_blkg should be free before goto lable fail_unlock
> in blkg_conf_prep() function.
How do you think
Hi All,
This patch series describes i2c, iic, mmc0, sdhi, sata, AVB, apmu and
RWDT on R8A7742 SoC.
Cheers,
Prabhakar
Lad Prabhakar (17):
dt-bindings: i2c: renesas,i2c: Document r8a7742 support
dt-bindings: i2c: renesas,iic: Document r8a7742 support
ARM: dts: r8a7742: Add I2C and IIC
On Fri, May 15, 2020 at 01:47:56PM +0300, Serge Semin wrote:
> Since the common code in the spi-dw-dma.c driver is ready to be used
> by the MMIO driver and now provides a method to generically (on any
> DT or ACPI-based platforms) retrieve the Tx/Rx DMA channel handlers,
> we can use it and a set
Hi Mathieu,
On 2020-05-15 20:22, Mathieu Poirier wrote:
On Thu, 14 May 2020 at 12:39, Sai Prakash Ranjan
wrote:
Hi Mathieu,
On 2020-05-14 23:30, Mathieu Poirier wrote:
> Good morning Sai,
>
> On Thu, May 14, 2020 at 04:29:15PM +0530, Sai Prakash Ranjan wrote:
>> From: Tingwei Zhang
>>
>>
On Thu, May 14, 2020 at 12:59 PM David Howells wrote:
>
> How about this then?
>
> David
> ---
> commit fa37b6c7e2f86d16ede1e0e3cb73857152d51825
> Author: David Howells
> Date: Thu May 14 17:48:55 2020 +0100
>
> keys: Move permissions checking decisions into the checking code
>
>
On Sat, May 16, 2020 at 12:01:41AM +0900, Akira Yokosawa wrote:
> On Thu, 14 May 2020 15:45:58 -0700, Paul E. McKenney wrote:
> > On Fri, May 15, 2020 at 07:03:33AM +0900, Akira Yokosawa wrote:
> >> On Thu, 14 May 2020 10:16:56 -0700, Paul E. McKenney wrote:
> >>> On Thu, May 14, 2020 at
On Fri, May 15, 2020 at 05:50:07PM +0300, Serge Semin wrote:
> On Fri, May 15, 2020 at 05:05:47PM +0300, Andy Shevchenko wrote:
> > On Thu, May 07, 2020 at 02:31:34AM +0300, Serge Semin wrote:
> > > Really instead of twice checking the clk_round_rate() return value
> > > we could do it once, and
; ^~
>
> i.e., CONFIG_MOUNT_NOTIFICATIONS is not set/enabled.
>
> Full randconfig file is attached.
>
This build error is still present in linux-next 20200515.
--
~Randy
Reported-by: Randy Dunlap
On Fri, May 15, 2020 at 01:47:54PM +0300, Serge Semin wrote:
> Seeing all of the DW SPI driver components like DW SPI DMA/PCI/MMIO
> depend on the DW SPI core code it's better to use the if-endif
> conditional kernel config statement to signify that common dependency.
Makes sense!
Reviewed-by:
On Friday 15 May 2020 15:53:59 CEST Greg Kroah-Hartman wrote:
> On Fri, May 15, 2020 at 10:33:11AM +0200, Jerome Pouiller wrote:
> > From: Jérôme Pouiller
> >
> > The function hif_scan() return the timeout for the completion of the
> > scan request. It is the only function from hif_tx.c that
In the kernel, volatile is used in various concurrent context, whether
in low-level synchronization primitives or for legacy reasons. If
supported by the compiler, we will assume that aligned volatile accesses
up to sizeof(long long) (matching compiletime_assert_rwonce_type()) are
atomic.
Recent
The first version of Clang that supports -tsan-distinguish-volatile will
be able to support KCSAN. The first Clang release to do so, will be
Clang 11. This is due to satisfying all the following requirements:
1. Never emit calls to __tsan_func_{entry,exit}.
2. __no_kcsan functions should not
To avoid inserting __tsan_func_{entry,exit}, add option if supported by
compiler. Currently only Clang can be told to not emit calls to these
functions. It is safe to not emit these, since KCSAN does not rely on
them.
Note that, if we disable __tsan_func_{entry,exit}(), we need to disable
Some compilers incorrectly inline small __no_kcsan functions, which then
results in instrumenting the accesses. For this reason, the 'noinline'
attribute was added to __no_kcsan_or_inline. All known versions of GCC
are affected by this. Supported version of Clang are unaffected, and
never inlines
This patch series is the conclusion to [1], where we determined that due
to various interactions with no_sanitize attributes and the new
{READ,WRITE}_ONCE(), KCSAN will require Clang 11 or later. Other
sanitizers are largely untouched, and only KCSAN now has a hard
dependency on Clang 11. To test,
Clang (unlike GCC) removes reads before writes with matching addresses
in the same basic block. This is an optimization for TSAN, since writes
will always cause conflict if the preceding read would have.
However, for KCSAN we cannot rely on this option, because we apply
several special rules to
The volatile access no longer needs to be wrapped in data_race(),
because we require compilers that emit instrumentation distinguishing
volatile accesses.
Signed-off-by: Marco Elver
---
include/linux/compiler.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Arnd Bergmann
Clang does not allow -fsanitize-coverage=trace-{pc,cmp} together
with -fsanitize=bounds or with ubsan:
clang: error: argument unused during compilation:
'-fsanitize-coverage=trace-pc' [-Werror,-Wunused-command-line-argument]
clang: error: argument unused during compilation:
Cleanup and move the KASAN and KCSAN related function attributes to
compiler_types.h, where the rest of the same kind live.
No functional change intended.
Signed-off-by: Marco Elver
---
include/linux/compiler.h | 29 -
include/linux/compiler_types.h | 29
Signed-off-by: Marco Elver
---
Documentation/dev-tools/kcsan.rst | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/Documentation/dev-tools/kcsan.rst
b/Documentation/dev-tools/kcsan.rst
index f4b5766f12cc..ce4bbd918648 100644
--- a/Documentation/dev-tools/kcsan.rst
+++
Like is done for KCSAN, for KASAN we should also use __always_inline in
compilation units that have instrumentation disabled
(KASAN_SANITIZE_foo.o := n). Adds common documentation for KASAN and
KCSAN explaining the attribute.
Signed-off-by: Marco Elver
---
include/linux/compiler_types.h | 13
On Fri, May 15, 2020 at 01:47:53PM +0300, Serge Semin wrote:
> Since there is a generic method available to initialize the DW SPI DMA
> interface on any DT and ACPI-based platforms, which in general can be
> designed with not only DW DMAC but with any DMA engine on board, we can
> freely remove
Hi,
On 15/05/2020 14:16:24+0300, cristian.bir...@microchip.com wrote:
> From: Cristian Birsan
>
> This patch set adds usb device support for SAM9x60 SoC.
> The DPRAM memory for the USB High Speed Device Port (UDPHS) hardware
> block was increased and the allocation method is changed. This patch
On Thu, 14 May 2020 15:45:58 -0700, Paul E. McKenney wrote:
> On Fri, May 15, 2020 at 07:03:33AM +0900, Akira Yokosawa wrote:
>> On Thu, 14 May 2020 10:16:56 -0700, Paul E. McKenney wrote:
>>> On Thu, May 14, 2020 at 08:46:18AM +0800, Boqun Feng wrote:
On Wed, May 13, 2020 at 06:39:03AM
On Fri, May 15, 2020 at 10:39:25PM +0800, Lai Jiangshan wrote:
> On Fri, May 15, 2020 at 9:04 PM Peter Zijlstra wrote:
> > On Fri, May 15, 2020 at 12:47:06PM +, Lai Jiangshan wrote:
> > > lib/rbtree.c has ensured that there is not possible to
> > > inadvertently cause (temporary) loops in the
Andy Lutomirski writes:
> On Tue, May 5, 2020 at 7:16 AM Thomas Gleixner wrote:
>>
>> Provide a separate macro for #DF as this needs to emit paranoid only code
>> and has also a special ASM stub in 32bit.
>
> Acked-by: Andy Lutomirski
>
> but... maybe it would be cleaner just to open-code all
On Fri, May 15, 2020 at 06:44:44AM -0700, Shakeel Butt wrote:
> On Fri, May 15, 2020 at 6:24 AM Johannes Weiner wrote:
> >
> > On Fri, May 15, 2020 at 10:29:55AM +0200, Michal Hocko wrote:
> > > On Sat 09-05-20 07:06:38, Shakeel Butt wrote:
> > > > On Fri, May 8, 2020 at 2:44 PM Johannes Weiner
On Fri, May 15, 2020 at 05:16:27PM +0300, Serge Semin wrote:
> On Fri, May 15, 2020 at 04:49:56PM +0300, Andy Shevchenko wrote:
> > On Fri, May 15, 2020 at 04:05:59PM +0300, Serge Semin wrote:
> > > On Fri, May 15, 2020 at 04:03:05PM +0300, Andy Shevchenko wrote:
> > > > On Fri, May 15, 2020 at
On 2020/05/13, Sebastian Reichel wrote:
> From: Jean-Francois Dagenais
>
> In certain designs, it is possible to add a battery on a populated i2c
> bus without an sbs compliant charger. In that case, the battery will
> un-necessarily and sometimes un-desirably master the bus trying to write
>
On 15/05/2020 17:00:01+0300, Codrin Ciubotariu wrote:
> The SCL gpio pin used by I2C bus for recovery needs to be configured as
> open drain.
>
> Fixes: 455fec938bbb ("ARM: dts: at91: sama5d2: add i2c gpio pinctrl")
> Fixes: a4bd8da893a3 ("ARM: dts: at91: sama5d3: add i2c gpio pinctrl")
> Fixes:
On Fri, May 15, 2020 at 03:48:59PM +0200, Greg Kroah-Hartman wrote:
I still fail to understand the need for this patch at all. It doesn't
clean anything up, nor change anything. There is no rule that this has
to be in one order or the other, and in fact, I like the order that the
files
On Fri, May 15, 2020 at 7:29 AM Arnaldo Carvalho de Melo
wrote:
>
> Em Fri, May 15, 2020 at 11:17:07AM +0200, Jiri Olsa escreveu:
> > On Thu, May 14, 2020 at 11:56:20PM -0700, Ian Rogers wrote:
> > > Localize the hashmap__* symbols in libbpf.a. To allow for a version in
> > > libapi.
> > >
> > >
On 06/05/2020 19:24, Enric Balletbo i Serra wrote:
> Hi Wei,
>
> Thank you for your patch.
>
> On 6/5/20 16:13, Wei Yongjun wrote:
>> Add the missing platform_device_unregister() before return
>> from mtk_mmsys_probe() in the error handling case.
>>
>> Fixes: 667c769246b0 ("soc / drm:
On Thu, 14 May 2020 at 12:39, Sai Prakash Ranjan
wrote:
>
> Hi Mathieu,
>
> On 2020-05-14 23:30, Mathieu Poirier wrote:
> > Good morning Sai,
> >
> > On Thu, May 14, 2020 at 04:29:15PM +0530, Sai Prakash Ranjan wrote:
> >> From: Tingwei Zhang
> >>
> >> On some Qualcomm Technologies Inc. SoCs
On Fri, May 15, 2020 at 01:47:52PM +0300, Serge Semin wrote:
> This is a preparation patch before adding the DW DMA support into the
> DW SPI MMIO driver. We need to unpin the Non-DMA-specific code from the
> intended to be generic DW APB SSI DMA code. This isn't that hard,
> since the most part
On 14/05/2020 05:03:06+, tudor.amba...@microchip.com wrote:
> From: Tudor Ambarus
>
> Rework the sama5d2 SoC flexcom definitions. The Flexcom IPs are
> in the SoC. Move all the flexcom nodes together with their function
> definitions in the SoC dtsi. Boards will just fill the pins and enable
On Fri, May 15, 2020 at 05:05:47PM +0300, Andy Shevchenko wrote:
> On Thu, May 07, 2020 at 02:31:34AM +0300, Serge Semin wrote:
> > Really instead of twice checking the clk_round_rate() return value
> > we could do it once, and if it isn't error the clock rate can be changed.
> > By doing so we
Hi Sebastian,
On 2020/05/13, Sebastian Reichel wrote:
> Some smart batteries store their manufacture date, which is
> useful to identify the battery and/or to know about the cell
> quality.
>
Have you considered exposing this as a single file? Say following the ISO8601
format - -MM-DD.
Hi Wolfram,
On 26/02/2020 23:23, Rob Herring wrote:
> On Sat, 22 Feb 2020 21:54:41 +0530, Manivannan Sadhasivam wrote:
>> I2C controller driver for MT6577 SoC is reused for MT6797 SoC. Hence,
>> document that in DT binding.
>>
>> Signed-off-by: Manivannan Sadhasivam
>> ---
>>
On Fri, 2020-05-15 at 16:10 +0200, Daniel Lezcano wrote:
> Initially the thermal framework had a very simple notification
> mechanism to send generic netlink messages to the userspace.
>
> The notification function was never called from anywhere and the
> corresponding dead code was removed. It
On 2020/05/13, Sebastian Reichel wrote:
> SBS battery driver exposes 32 power supply properties now,
> which will result in uevent failure on (un)plugging the
> battery. Other drivers (e.g. bq27xxx) are also coming close
> to this limit, so increase it.
>
> Signed-off-by: Sebastian Reichel
> ---
Hello,
syzbot found the following crash on:
HEAD commit:bdecf38f Add linux-next specific files for 20200515
git tree: linux-next
console output: https://syzkaller.appspot.com/x/log.txt?x=155a43b210
kernel config: https://syzkaller.appspot.com/x/.config?x=27a5e30c87a59937
dashboard
On 05/15, Chao Yu wrote:
> On 2020/5/15 10:15, Jaegeuk Kim wrote:
> > Let's guarantee flusing dirty meta pages to avoid infinite loop.
>
> What's the root cause? Race case or meta page flush failure?
Investigating, but at least, this can avoid the inifinite loop there.
V2:
>From
> Complete shot in the dark but restore adjust_numa_imbalance() and try
> this
> diff --git a/kernel/sched/core.c b/kernel/sched/core.c
> index 1a9983da4408..0b31f4468d5b 100644
> --- a/kernel/sched/core.c
> +++ b/kernel/sched/core.c
> @@ -2393,7 +2393,7 @@ static void ttwu_queue(struct
be downloaded at:
https://github.com/linux-test-project/ltp/releases/tag/20200515
The project pages as well as GIT repository are hosted on GitHub:
https://github.com/linux-test-project/ltp
http://linux-test-project.github.io/
If you ever wondered how to write a LTP testcase, don't miss our de
* Kees Cook:
> On Fri, May 15, 2020 at 10:43:34AM +0200, Florian Weimer wrote:
>> * Kees Cook:
>>
>> > Maybe I've missed some earlier discussion that ruled this out, but I
>> > couldn't find it: let's just add O_EXEC and be done with it. It actually
>> > makes the execve() path more like
On Fri, 2020-05-15 at 16:10 +0200, Daniel Lezcano wrote:
> Initially the thermal framework had a very simple notification
> mechanism to send generic netlink messages to the userspace.
>
> The notification function was never called from anywhere and the
> corresponding dead code was removed. It
Hi Mathieu
On 5/14/20 10:40 PM, Mathieu Poirier wrote:
> After adding support for rpmsg device name extension, this patch
> provides a function that returns the extension portion of an rpmsg
> device name. That way users of the name extension functionality don't
> have to write the same boiler
Hi Bernard,
On Fri, May 08, 2020 at 04:47:17PM +0800, Bernard wrote:
> From: "赵军奎"
> Date: 2020-04-24 19:37:36
> To: Liviu Dudau
> Cc: Brian Starkey ,David Airlie
> ,Daniel Vetter
> ,dri-de...@lists.freedesktop.org,linux-kernel@vger.kernel.org,opensource.ker...@vivo.com
> Subject: Re:Re:
On Fri, May 15, 2020 at 01:47:51PM +0300, Serge Semin wrote:
> Tx-only DMA transfers are working perfectly fine since in this case
> the code just ignores the Rx FIFO overflow interrupts. But it turns
> out the SPI Rx-only transfers are broken since nothing pushing any
> data to the shift
C6x needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/c6x/include/asm/cacheflush.h | 19 +--
1 file changed, 1 insertion(+), 18 deletions(-)
diff --git
ARM64 needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/arm64/include/asm/cacheflush.h | 46 -
1 file changed, 5 insertions(+), 41 deletions(-)
diff --git
On Fri, May 15, 2020 at 01:47:50PM +0300, Serge Semin wrote:
> This field is used only for the DW SPI DMA code initialization, that's
> why there were no problems with it being uninitialized in Dw SPI MMIO
> driver. Since in a further patch we are going to introduce the DW SPI DMA
> support in the
OpenRISC needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/openrisc/include/asm/cacheflush.h | 31 +-
1 file changed, 6 insertions(+), 25 deletions(-)
diff --git
On Fri, May 15, 2020 at 9:04 PM Peter Zijlstra wrote:
>
> On Fri, May 15, 2020 at 12:47:06PM +, Lai Jiangshan wrote:
> > lib/rbtree.c has ensured that there is not possible to
> > inadvertently cause (temporary) loops in the tree structure
> > as seen in program order of the modifier. But
IA64 needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/ia64/include/asm/cacheflush.h | 28 +++-
1 file changed, 3 insertions(+), 25 deletions(-)
diff --git
Only build read_code when binary formats that use it are built into the
kernel.
Signed-off-by: Christoph Hellwig
---
fs/exec.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/fs/exec.c b/fs/exec.c
index 06b4c550af5d9..a4f766f296f8f 100644
--- a/fs/exec.c
+++ b/fs/exec.c
@@ -1027,6
m68knommu needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
Acked-by: Greg Ungerer
---
arch/m68k/include/asm/cacheflush_no.h | 19 ++-
1 file changed, 2 insertions(+), 17 deletions(-)
diff
Rename the current flush_icache_range to flush_icache_user_range as
per commit ae92ef8a4424 ("PATCH] flush icache in correct context") there
seems to be an assumption that it operates on user addresses. Add a
flush_icache_range around it that for now is a no-op.
Signed-off-by: Christoph Hellwig
Hexagon needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/hexagon/include/asm/cacheflush.h | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git
On Fri, May 15, 2020 at 01:47:49PM +0300, Serge Semin wrote:
> Each channel of DMA controller may have a limited length of burst
> transaction (number of IO operations performed at ones in a single
> DMA client request). This parameter can be used to setup the most
> optimal DMA Tx/Rx data level
load_flat_file works on user addresses.
Signed-off-by: Christoph Hellwig
Acked-by: Greg Ungerer
---
fs/binfmt_flat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/binfmt_flat.c b/fs/binfmt_flat.c
index 831a2b25ba79f..6f0aca5379da2 100644
--- a/fs/binfmt_flat.c
+++
The Xtensa implementation of flush_icache_range seems to be able to
cope with user addresses. Just define flush_icache_user_range to
flush_icache_range.
Signed-off-by: Christoph Hellwig
---
arch/xtensa/include/asm/cacheflush.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
The function currently known as flush_icache_user_range only operates
on a single page. Rename it to flush_icache_user_page as we'll need
the name flush_icache_user_range for something else soon.
Signed-off-by: Christoph Hellwig
Acked-by: Geert Uytterhoeven
---
flush_icache_range generally operates on kernel addresses, but for some
reason m68k needed a set_fs override. Move that into the m68k code
insted of keeping it in the module loader.
Signed-off-by: Christoph Hellwig
Reviewed-by: Geert Uytterhoeven
Acked-by: Geert Uytterhoeven
---
read_code operates on user addresses.
Signed-off-by: Christoph Hellwig
---
fs/exec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/exec.c b/fs/exec.c
index a4f766f296f8f..c541867316a63 100644
--- a/fs/exec.c
+++ b/fs/exec.c
@@ -1033,7 +1033,7 @@ ssize_t read_code(struct
flush_icache_user_range will be the name for a generic primitive.
Move the arm name so that arm already has an implementation.
Signed-off-by: Christoph Hellwig
---
arch/arm/include/asm/cacheflush.h | 4 ++--
arch/arm/kernel/traps.c | 2 +-
2 files changed, 3 insertions(+), 3
These obviously operate on user addresses.
Signed-off-by: Christoph Hellwig
---
mm/nommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/mm/nommu.c b/mm/nommu.c
index 318df4e236c99..aed7acaed2383 100644
--- a/mm/nommu.c
+++ b/mm/nommu.c
@@ -443,7 +443,7 @@
flush_icache_user_range is only used by , so
remove it from the architectures that implement it, but don't use
.
Signed-off-by: Christoph Hellwig
---
arch/arm/include/asm/cacheflush.h | 3 ---
arch/sparc/include/asm/cacheflush_32.h | 2 --
arch/sparc/include/asm/cacheflush_64.h | 1 -
cacheflush.h uses a somewhat to generic include guard name that clashes
with various arch files. Use a more specific one.
Signed-off-by: Christoph Hellwig
---
include/asm-generic/cacheflush.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
On 15/05/2020 12:48, Jiri Olsa wrote:
On Fri, May 15, 2020 at 10:09:10AM +0100, John Garry wrote:
On 15/05/2020 00:02, Ian Rogers wrote:
On Thu, May 14, 2020 at 2:00 AM John Garry wrote:
On 13/05/2020 17:10, Ian Rogers wrote:
Out of interest, if we could move the validation of metrics to
There is a magic ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE cpp symbol that
guards non-stub availability of flush_dcache_pagge. Use that to
check if flush_dcache_pagg is implemented.
Signed-off-by: Christoph Hellwig
---
include/asm-generic/cacheflush.h | 6 +++---
1 file changed, 3 insertions(+), 3
The SuperH implementation of flush_icache_range seems to be able to
cope with user addresses. Just define flush_icache_user_range to
flush_icache_range.
Signed-off-by: Christoph Hellwig
---
arch/sh/include/asm/cacheflush.h | 1 +
1 file changed, 1 insertion(+)
diff --git
Power needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Also remove the pointless __KERNEL__ ifdef while we're at it.
Signed-off-by: Christoph Hellwig
---
arch/powerpc/include/asm/cacheflush.h | 42 +++
1 file
Define flush_icache_user_range to flush_icache_range unless the
architecture provides its own implementation.
Signed-off-by: Christoph Hellwig
---
include/asm-generic/cacheflush.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/asm-generic/cacheflush.h
RISC-V needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Also remove the pointless __KERNEL__ ifdef while we're at it.
Signed-off-by: Christoph Hellwig
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
---
Alpha needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/alpha/include/asm/cacheflush.h | 28 ++--
1 file changed, 6 insertions(+), 22 deletions(-)
diff --git
Microblaze needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/microblaze/include/asm/cacheflush.h | 29 ++--
1 file changed, 2 insertions(+), 27 deletions(-)
diff --git
On Fri, May 15, 2020 at 10:43:34AM +0200, Florian Weimer wrote:
> * Kees Cook:
>
> > Maybe I've missed some earlier discussion that ruled this out, but I
> > couldn't find it: let's just add O_EXEC and be done with it. It actually
> > makes the execve() path more like openat2() and is much
This seems to lead to some crazy include loops when using
asm-generic/cacheflush.h on more architectures, so leave it
to the arch header for now.
Signed-off-by: Christoph Hellwig
---
arch/um/include/asm/tlb.h | 2 ++
arch/x86/include/asm/cacheflush.h | 2 ++
drivers/nvdimm/pmem.c
flush_icache_page is only used by mm/memory.c.
Signed-off-by: Christoph Hellwig
---
arch/nds32/mm/cacheflush.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c
index 254703653b6f5..8f168b33065fa 100644
--- a/arch/nds32/mm/cacheflush.c
Hi all,
flush_icache_range is mostly used for kernel address, except for the following
cases:
- the nommu brk and mmap implementations,
- the read_code helper that is only used for binfmt_flat, binfmt_elf_fdpic,
and binfmt_aout including the broken ia32 compat version
- binfmt_flat itself,
The arguments passed look bogus, try to fix them to something that seems
to make sense.
Signed-off-by: Christoph Hellwig
---
arch/arm/kernel/fiq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index
flush_icache_user_range is only used by copy_to_user_page, which is
only used by core VM code.
Signed-off-by: Christoph Hellwig
---
arch/powerpc/mm/mem.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 041ed7cfd341a..f0d1bf0a8e14f 100644
flush_cache_user_range is an ARMism not used by any generic or unicore32
specific code.
Signed-off-by: Christoph Hellwig
---
arch/unicore32/include/asm/cacheflush.h | 8
1 file changed, 8 deletions(-)
diff --git a/arch/unicore32/include/asm/cacheflush.h
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