Re: [PATCH v4 2/4] dt-bindings: nvmem: Add properties needed for blowing fuses

On Mon, 22 Jun 2020 07:49:27 -0700, Douglas Anderson wrote: > From: Ravi Kumar Bokka > > On some systems it's possible to actually blow the fuses in the qfprom > from the kernel. Add properties to support that. > > NOTE: Whether this is possible depends on the BIOS settings and > whether the

Re: [PATCH v4 1/4] dt-bindings: nvmem: qfprom: Convert to yaml

On Mon, 22 Jun 2020 07:49:26 -0700, Douglas Anderson wrote: > From: Ravi Kumar Bokka > > This switches the bindings over from txt to yaml. > > Signed-off-by: Ravi Kumar Bokka > Signed-off-by: Douglas Anderson > --- > > Changes in v4: > - Maintainer now listed as Srinivas. > - Example under

Re: [PATCH V2 0/3] riscv: Enable LOCKDEP

Thank you, Palmer On Fri, Jul 10, 2020 at 6:06 AM Palmer Dabbelt wrote: > > On Sat, 27 Jun 2020 06:57:05 PDT (-0700), guo...@kernel.org wrote: > > From: Guo Ren > > > > Lockdep is needed by proving the spinlocks and rwlocks. To support it, > > we need to add TRACE_IRQFLAGS codes in

Re: [PATCH v4 2/3] dt-bindings: arm: realtek: Document RTD1319 and Realtek Pym Particles EVB

On Mon, 22 Jun 2020 14:55:25 +0200, Andreas Färber wrote: > From: James Tai > > Define compatible strings for Realtek RTD1319 SoC and Realtek Pym Particles > EVB. > > Signed-off-by: James Tai > Signed-off-by: Andreas Färber > --- > v3 -> v4: > * Renamed compatible from pymparticle to

Re: [PATCH v4 1/3] dt-bindings: arm: realtek: Convert comments to descriptions

On Mon, 22 Jun 2020 14:55:24 +0200, Andreas Färber wrote: > Turn the SoC-level comments into description properties. > > Signed-off-by: Andreas Färber > --- > v4: New > > .../devicetree/bindings/arm/realtek.yaml | 24 +-- > 1 file changed, 12 insertions(+), 12

Re: [PATCH v2 1/2] riscv: Add STACKPROTECTOR supported

Yes, I didn't test riscv32-gcc and it needs to be 16UL. On Fri, Jul 10, 2020 at 2:37 AM kernel test robot wrote: > > Hi, > > I love your patch! Perhaps something to improve: > > [auto build test WARNING on linus/master] > [also build test WARNING on v5.8-rc4 next-20200

Re: [PATCH v4 1/3] dt-bindings: hwmon: Add Sparx5 temperature sensor

On Thu, 18 Jun 2020 15:59:49 +0200, Lars Povlsen wrote: > This add the DT binding specification for the Sparx5 temperature > sensor. > > Signed-off-by: Lars Povlsen > --- > .../bindings/hwmon/microchip,sparx5-temp.yaml | 44 +++ > 1 file changed, 44 insertions(+) > create mode

[PATCH v6 1/2] dt-bindings: mfd: Add ENE KB3930 Embedded Controller binding

Add binding document for the ENE KB3930 Embedded Controller. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring --- Changes since v5: - s/a I2C bus/an I2C bus/ Changes since v4: - Collected Rob's Reviewed-by Changes since v1: - Addressed binding validation failure ---

[PATCH v6 2/2] mfd: ene-kb3930: Add driver for ENE KB3930 Embedded Controller

This driver provides access to the EC RAM of said embedded controller attached to the I2C bus as well as optionally supporting its slightly weird power-off/restart protocol. A particular implementation of the EC firmware can be identified by a model byte. If this driver identifies the Dell Ariel

[PATCH v6 0/2] mfd: Add ENE KB3930 Embedded Controller driver

Hi, please consider applying the patches chained to this message. It's the sixth version of the driver for the ENE KB3930 Embedded Controller. This addresses responses to the fifth version of the set. Detailed change logs are in the individual patch descriptions. One thing that I was asked to

[SchedulerWakeupLatency] Skipping Idle Cores and CPU Search

> A) Name: Skipping Idle Cores and CPU Search > B) Target behavior: Finding idle CPUs in the CFS scheduler for scheduling awakened tasks increases system throughput at the expense of additional wake-up latency. For the majority of processes this is a reasonable trade-off. Some communication

Re: [PATCH v4 1/2] dt-bindings: usb: Add USB PHY support for Intel LGM SoC

On Wed, 17 Jun 2020 11:58:17 +0800, Ramuthevar,Vadivel MuruganX wrote: > From: Ramuthevar Vadivel Murugan > > Add the dt-schema to support USB PHY on Intel LGM SoC > > Signed-off-by: Ramuthevar Vadivel Murugan > > --- > .../devicetree/bindings/usb/intel,lgm-usb-phy.yaml | 53 >

Re: [PATCH v4 07/12] ARM: mstar: Add binding details for mstar,l3bridge

On Tue, 16 Jun 2020 21:15:20 +0900, Daniel Palmer wrote: > This adds a YAML description of the l3bridge node needed by the > platform code for the MStar/SigmaStar Armv7 SoCs. > > Signed-off-by: Daniel Palmer > --- > .../bindings/misc/mstar,l3bridge.yaml | 44 +++ > 1

Re: [PATCH v6 1/4] ACPI/PCI: Ignore _OSC negotiation result if pcie_ports_native is set.

On Fri, Jun 26, 2020 at 11:32:33AM -0700, sathyanarayanan.kuppusw...@linux.intel.com wrote: > From: Kuppuswamy Sathyanarayanan > > pcie_ports_native is set only if user requests native handling > of PCIe capabilities via pcie_port_setup command line option. > User input takes precedence over

Re: [PATCH v4 04/12] dt-bindings: vendor-prefixes: Add thingy.jp prefix

On Tue, 16 Jun 2020 21:15:17 +0900, Daniel Palmer wrote: > Add prefix for thingy.jp > > Signed-off-by: Daniel Palmer > --- > Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring

Re: [PATCH v4 03/12] dt-bindings: vendor-prefixes: Add 70mai vendor prefix

On Tue, 16 Jun 2020 21:15:16 +0900, Daniel Palmer wrote: > Add prefix for 70mai Co., Ltd > > Signed-off-by: Daniel Palmer > --- > Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring

Re: [PATCH v4 05/12] dt-bindings: arm: Add mstar YAML schema

On Tue, Jun 16, 2020 at 09:15:18PM +0900, Daniel Palmer wrote: > This adds some intial boards for Armv7 based mstar platforms. > > Signed-off-by: Daniel Palmer > --- > .../devicetree/bindings/arm/mstar.yaml| 34 +++ > MAINTAINERS | 7

Re: [PATCH v4 02/12] dt-bindings: vendor-prefixes: Add sstar vendor prefix

On Tue, 16 Jun 2020 21:15:15 +0900, Daniel Palmer wrote: > Add prefix for Xiamen Xingchen Technology Co., Ltd > > Signed-off-by: Daniel Palmer > --- > Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring

Re: [PATCH v4 01/12] dt-bindings: vendor-prefixes: Add mstar vendor prefix

On Tue, 16 Jun 2020 21:15:14 +0900, Daniel Palmer wrote: > Add prefix for MStar Semiconductor, Inc. > > Signed-off-by: Daniel Palmer > --- > Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring

Re: [PATCH v4 4/9] mips: bmips: add BCM63268 power domain definitions

On Sat, 13 Jun 2020 10:21:35 +0200, Álvaro Fernández Rojas wrote: > BCM63268 SoCs have a power domain controller to enable/disable certain > components in order to save power. > > Signed-off-by: Álvaro Fernández Rojas > --- > v4: Remove "dts: " from commit title. > v3: Separate dt-bindings

Re: [tip: perf/core] x86/cpufeatures: Add Architectural LBRs feature bit

On 7/8/20 2:51 AM, tip-bot2 for Kan Liang wrote: > diff --git a/arch/x86/include/asm/cpufeatures.h > b/arch/x86/include/asm/cpufeatures.h > index 02dabc9..72ba4c5 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -366,6 +366,7 @@ > #define

Re: [PATCH v4 5/9] mips: bmips: add BCM6318 power domain definitions

On Sat, 13 Jun 2020 10:21:36 +0200, Álvaro Fernández Rojas wrote: > BCM6318 SoCs have a power domain controller to enable/disable certain > components in order to save power. > > Signed-off-by: Álvaro Fernández Rojas > --- > v4: no changes. > v3: no changes (patch reordered). > v2: Add

Re: [PATCH v4 3/9] mips: bmips: add BCM6362 power domain definitions

On Sat, 13 Jun 2020 10:21:34 +0200, Álvaro Fernández Rojas wrote: > BCM6362 SoCs have a power domain controller to enable/disable certain > components in order to save power. > > Signed-off-by: Álvaro Fernández Rojas > --- > v4: Remove "dts: " from commit title. > v3: Separate dt-bindings

Re: [PATCH v4 2/9] mips: bmips: add BCM6328 power domain definitions

On Sat, 13 Jun 2020 10:21:33 +0200, Álvaro Fernández Rojas wrote: > BCM6328 SoCs have a power domain controller to enable/disable certain > components in order to save power. > > Signed-off-by: Álvaro Fernández Rojas > --- > v4: Remove "dts: " from commit title. > v3: Separate dt-bindings

Re: [PATCH v4 1/9] dt-bindings: soc: brcm: add BCM63xx power domain binding

On Sat, 13 Jun 2020 10:21:32 +0200, Álvaro Fernández Rojas wrote: > BCM6318, BCM6328, BCM6362 and BCM63268 SoCs have a power domain controller > to enable/disable certain components in order to save power. > > Signed-off-by: Álvaro Fernández Rojas > Reviewed-by: Florian Fainelli > --- > v4:

Re: [PATCH] tpm: Require that all digests are present in TCG_PCR_EVENT2 structures

On 2020-07-03 02:57:18, Jarkko Sakkinen wrote: > On Tue, Jun 30, 2020 at 01:33:21PM -0500, Tyler Hicks wrote: > > Jarkko, is this an ack from you? > > > > Is there anything I can do to help along this fix? > > > > I've spoke with two others that have poured through these specs to > > implement

Re: [PATCH v5 4/5] dt-bindings: display: imx: add bindings for DCSS

On Thu, Jul 09, 2020 at 07:47:32PM +0300, Laurentiu Palcu wrote: > From: Laurentiu Palcu > > Add bindings for iMX8MQ Display Controller Subsystem. > > Signed-off-by: Laurentiu Palcu > --- > .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 84 +++ > 1 file changed, 84

Re: [PATCH resend] binder: Prevent context manager from incrementing ref 0

On Thu, Jul 9, 2020 at 3:40 PM Jann Horn wrote: > > Binder is designed such that a binder_proc never has references to > itself. If this rule is violated, memory corruption can occur when a > process sends a transaction to itself; see e.g. >

Re: [PATCH v3 4/9] vfio/fsl-mc: Implement VFIO_DEVICE_GET_REGION_INFO ioctl call

On Mon, 6 Jul 2020 18:41:48 +0300 Diana Craciun wrote: > Expose to userspace information about the memory regions. > > Signed-off-by: Bharat Bhushan > Signed-off-by: Diana Craciun > --- > drivers/vfio/fsl-mc/vfio_fsl_mc.c | 77 ++- >

Re: [PATCH v5 2/4] dt-bindings: arm: rockchip: Add Rock Pi N8 binding

On Thu, 09 Jul 2020 15:37:54 +0530, Jagan Teki wrote: > Rock Pi N8 is a Rockchip RK3288 based SBC, which has > - VMARC RK3288 SOM (as per SMARC standard) from Vamrs. > - Compatible carrier board from Radxa. > > VMARC RK3288 SOM need to mount on top of dalang carrier > board for making Rock PI N8

Re: [PATCH] Documentation/security-bugs: Explain why plain text is preferred

On Thu, 9 Jul 2020, Kees Cook wrote: > The security contact list gets regular reports contained in archive > attachments. This tends to add some back-and-forth delay in dealing with > security reports since we have to ask for plain text, etc. > > Signed-off-by: Kees Cook Acked-by: Jiri Kosina

Re: [PATCH v5 1/2] dt-bindings: timer: Add Ingenic X1000 OST bindings.

On Sun, Jul 05, 2020 at 10:03:52PM +0800, 周琰杰 (Zhou Yanjie) wrote: > Add the OST bindings for the X1 SoC from Ingenic. > > Tested-by: 周正 (Zhou Zheng) > Signed-off-by: 周琰杰 (Zhou Yanjie) > Reviewed-by: Paul Cercueil > --- > > Notes: > v1->v2: > No change. > > v2->v3: >

[PATCH v7 03/11] dmaengine: Introduce min burst length capability

Some hardware aside from default 0/1 may have greater minimum burst transactions length constraints. Here we introduce the DMA device and slave capability, which if required can be initialized by the DMA engine driver with the device-specific value. Signed-off-by: Serge Semin Reviewed-by: Andy

[PATCH v7 05/11] dmaengine: Introduce DMA-device device_caps callback

There are DMA devices (like ours version of Synopsys DW DMAC) which have DMA capabilities non-uniformly redistributed between the device channels. In order to provide a way of exposing the channel-specific parameters to the DMA engine consumers, we introduce a new DMA-device callback. In case if

[PATCH v7 10/11] dmaengine: dw: Introduce max burst length hw config

IP core of the DW DMA controller may be synthesized with different max burst length of the transfers per each channel. According to Synopsis having the fixed maximum burst transactions length may provide some performance gain. At the same time setting up the source and destination multi size

[PATCH v7 09/11] dmaengine: dw: Initialize min and max burst DMA device capability

According to the DW APB DMAC data book the minimum burst transaction length is 1 and it's true for any version of the controller since isn't parametrised in the coreAssembler so can't be changed at the IP-core synthesis stage. The maximum burst transaction can vary from channel to channel and from

Re: [PATCH v5 2/6] dt-bindings: usb: Add Qualcomm PMIC type C controller dt-binding

On Thu, Jul 02, 2020 at 06:50:58PM -0700, Wesley Cheng wrote: > Introduce the dt-binding for enabling USB type C orientation and role > detection using the PM8150B. The driver will be responsible for receiving > the interrupt at a state change on the CC lines, reading the orientation/role, > and

[PATCH v7 07/11] dmaengine: dw: Set DMA device max segment size parameter

Maximum block size DW DMAC configuration corresponds to the max segment size DMA parameter in the DMA core subsystem notation. Lets set it with a value specific to the probed DW DMA controller. It shall help the DMA clients to create size-optimized SG-list items for the controller. This in turn

[PATCH v7 08/11] dmaengine: dw: Add dummy device_caps callback

Since some DW DMA controllers (like one installed on Baikal-T1 SoC) may have non-uniform DMA capabilities per device channels, let's add the DW DMA specific device_caps callback to expose that specifics up to the DMA consumer. It's a dummy function for now. We'll fill it in with capabilities

[PATCH v7 06/11] dmaengine: dw: Take HC_LLP flag into account for noLLP auto-config

Full multi-block transfers functionality is enabled in DW DMA controller only if CHx_MULTI_BLK_EN is set. But LLP-based transfers can be executed only if hardcode channel x LLP register feature isn't enabled, which can be switched on at the IP core synthesis for optimization. If it's enabled then

[PATCH v7 11/11] dmaengine: dw: Initialize max_sg_nents capability

Multi-block support provides a way to map the kernel-specific SG-table so the DW DMA device would handle it as a whole instead of handling the SG-list items or so called LLP block items one by one. So if true LLP list isn't supported by the DW DMA engine, then soft-LLP mode will be utilized to

[PATCH v7 02/11] dt-bindings: dma: dw: Add max burst transaction length property

This array property is used to indicate the maximum burst transaction length supported by each DMA channel. Signed-off-by: Serge Semin Reviewed-by: Rob Herring Acked-by: Viresh Kumar Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Arnd Bergmann Cc: Andy Shevchenko Cc:

[PATCH v7 04/11] dmaengine: Introduce max SG list entries capability

Some devices may lack the support of the hardware accelerated SG list entries automatic walking through and execution. In this case a burden of the SG list traversal and DMA engine re-initialization lies on the DMA engine driver (normally implemented by using a DMA transfer completion IRQ to

[PATCH RESEND v7 00/11] dmaengine: dw: Take Baikal-T1 SoC DW DMAC peculiarities into account

In the previous patchset I've written the next message: > Folks, note I've removed the next patches from the series: > [PATCH v7 04/11] dmaengine: Introduce max SG list entries capability > [PATCH v7 11/11] dmaengine: dw: Initialize max_sg_nents capability > It turns out the problem with the

[PATCH v7 01/11] dt-bindings: dma: dw: Convert DW DMAC to DT binding

Modern device tree bindings are supposed to be created as YAML-files in accordance with dt-schema. This commit replaces the Synopsis Designware DMA controller legacy bare text bindings with YAML file. The only required prorties are "compatible", "reg", "#dma-cells" and "interrupts", which will be

Re: [PATCH v3 2/9] vfio/fsl-mc: Scan DPRC objects on vfio-fsl-mc driver bind

On Mon, 6 Jul 2020 18:41:46 +0300 Diana Craciun wrote: > The DPRC (Data Path Resource Container) device is a bus device and has > child devices attached to it. When the vfio-fsl-mc driver is probed > the DPRC is scanned and the child devices discovered and initialized. > > Signed-off-by:

Re: [PATCH v5] x86/speculation/l1tf: Add KConfig for setting the L1D cache flush mode

On Thu, Jul 09, 2020 at 12:42:57PM -0700, Doug Anderson wrote: > Hi, > > On Thu, Jul 9, 2020 at 3:51 AM Thomas Gleixner wrote: > > > > Abhishek Bhardwaj writes: > > > This change adds a new kernel configuration that sets the l1d cache > > > flush setting at compile time rather than at run time.

[PATCH resend] binder: Prevent context manager from incrementing ref 0

Binder is designed such that a binder_proc never has references to itself. If this rule is violated, memory corruption can occur when a process sends a transaction to itself; see e.g. . There is a remaining edgecase through which such

Re: [PATCH v6] xfs: Fix false positive lockdep warning with sb_internal & fs_reclaim

On Tue, Jul 07, 2020 at 03:16:29PM -0400, Waiman Long wrote: > One way to avoid this splat is to add GFP_NOFS to the affected allocation > calls by using the memalloc_nofs_save()/memalloc_nofs_restore() pair. > This shouldn't matter unless the system is really running out of memory. > In that

Re: [PATCH v7 2/9] pidfd: Add missing sock updates for pidfd_getfd()

On Thu, Jul 09, 2020 at 10:00:42PM +0200, Jann Horn wrote: > On Thu, Jul 9, 2020 at 8:26 PM Kees Cook wrote: > > The sock counting (sock_update_netprioidx() and sock_update_classid()) > > was missing from pidfd's implementation of received fd installation. Add > > a call to the new

[PATCH] gpio: omap: handle pin config bias flags

Modify omap_gpio_set_config() to handle pin config bias flags by calling gpiochip_generic_config(). The pin group for the gpio line must have the corresponding pinconf properties: PIN_CONFIG_BIAS_PULL_UP requires "pinctrl-single,bias-pullup" PIN_CONFIG_BIAS_PULL_DOWN requires

[PATCH 6/6] irqchip/brcmstb-l2: Match UPG_AUX_AON_INTR2 compatible

The UPG_AUX_AON_INTR2 Level 2 interrupt controller node is defined with the "brcm,upg-aux-aon-l2-intc" compatible string in Device Tree and behaves as an edge triggered standard Broadcom STB L2 interrupt controller. Signed-off-by: Florian Fainelli --- drivers/irqchip/irq-brcmstb-l2.c | 2 ++ 1

[PATCH 4/6] irqchip/brcmstb-l2: Match HIF_SPI_INTR2 compatible

From: Kamal Dasu The HIF_SPI_INTR2 Level 2 interrupt controller node is defined with the "brcm,hif-spi-l2-intc" compatible string in Device Tree and behaves as an edge triggered standard Broadcom STB L2 interrupt controller. Signed-off-by: Kamal Dasu Signed-off-by: Florian Fainelli ---

[PATCH 5/6] dt-bindings: interrupt-controller: Document UPG auxiliary L2

Define the compatible string brcm,upg-aux-aon-l2-intc which is used by the Broadcom STB UPG auxiliary always-on interrupt controller. Signed-off-by: Florian Fainelli --- .../devicetree/bindings/interrupt-controller/brcm,l2-intc.txt| 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH 2/6] irqchip/brcmstb-l2: Set controller as wake-up source

From: Justin Chen Utilize the Broadcom interrupt controller standard property "brcm,irq-can-wake" to flag whether this particular interrupt controller instance is wake-up capable. Since we do not know what type of parent interrupt controller we are interfaced with, ensure that enable_irq_wake()

[PATCH 3/6] dt-bindings: interrupt-controller: Document Broadcom STB HIF L2

Add documentation for the brcm,hif-spi-l2-intc compatible string to the brcm,l2-intc.txt binding document. Signed-off-by: Florian Fainelli --- .../devicetree/bindings/interrupt-controller/brcm,l2-intc.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git

[PATCH 0/6] irqchip: Broadcom STB interrupt controller updates

Hi Marc, This patch series contains a number of updates for Broadcom STB L2 interrupt controllers to enable them as wake-up interrupt controllers, and add missing compatible strings that should be matched. Thanks! Florian Fainelli (3): dt-bindings: interrupt-controller: Document Broadcom STB

[PATCH 1/6] irqchip/bcm7120-l2: Set controller as wake-up source

From: Justin Chen Utilize the Broadcom interrupt controller standard property "brcm,irq-can-wake" to flag whether this particular interrupt controller instance is wake-up capable. Since we do not know what type of parent interrupt controller we are interfaced with, ensure that enable_irq_wake()

Re: [PATCH AUTOSEL 5.7 15/53] ASoC: SOF: Intel: add PCI IDs for ICL-H and TGL-H

On Thu, Jul 02, 2020 at 05:05:28PM +0100, Mark Brown wrote: On Thu, Jul 02, 2020 at 10:42:21AM -0500, Pierre-Louis Bossart wrote: On 7/2/20 6:18 AM, Mark Brown wrote: > On Wed, Jul 01, 2020 at 09:21:24PM -0400, Sasha Levin wrote: > > From: Pierre-Louis Bossart > > [ Upstream commit

Re: [PATCH AUTOSEL 5.7 11/53] btrfs: use kfree() in btrfs_ioctl_get_subvol_info()

On Thu, Jul 02, 2020 at 10:25:58AM +0200, David Sterba wrote: On Wed, Jul 01, 2020 at 09:21:20PM -0400, Sasha Levin wrote: From: Waiman Long [ Upstream commit b091f7fede97cc64f7aaad3eeb37965aebee3082 ] In btrfs_ioctl_get_subvol_info(), there is a classic case where kzalloc() was incorrectly

[PATCH v3] ARM: dts: am335x-pocketbeagle: set default mux for gpio pins

These pins on the PocketBeagle P1 and P2 headers are connected to AM3358 balls with gpio lines, and these pins are not used for any other peripherals by default. These GPIO lines are unclaimed and could be used by userspace program through the gpiod ABI. This patch adds a "default" state in the

Re: [PATCH] KVM: x86/mmu: Add capability to zap only sptes for the affected memslot

On 09/07/20 23:12, Sean Christopherson wrote: >> It's bad that we have no clue what's causing the bad behavior, but I >> don't think it's wise to have a bug that is known to happen when you >> enable the capability. :/ (Note that this wasn't a NACK, though subtly so). > I don't necessarily

Re: [RFC PATCH] usb: dwc3: fix maximum_speed check for usb2.0-only core

Hi, Chunfeng Yun wrote: > The maximum_speed will be USB_SPEED_SUPER_PLUS, but the > maximum_speed check for usb2.0-only core doesn't consider it, > so fix it, and move the ckeck into dwc3_check_params(). > > Signed-off-by: Chunfeng Yun > --- > Note: > > When I look at the code, find that this

Re: [PATCH] Documentation/security-bugs: Explain why plain text is preferred

On Thu, Jul 09, 2020 at 09:42:56PM +0100, Will Deacon wrote: > On Thu, Jul 09, 2020 at 11:11:30AM -0700, Kees Cook wrote: > > The security contact list gets regular reports contained in archive > > attachments. This tends to add some back-and-forth delay in dealing with > > security reports since

Re: [RFC PATCH 2/3] firmware: Add support for PSA FF-A transport for VM partitions

On Mon, Jun 1, 2020 at 2:45 AM Sudeep Holla wrote: > > Initial support for PSA FF-A interface providing APIs for non-secure VM > partitions. > ... > diff --git a/drivers/firmware/arm_psa_ffa/Kconfig > b/drivers/firmware/arm_psa_ffa/Kconfig > new file mode 100644 > index

Re: [PATCH v5 7/7] dt-bindings: hwmon: Add bindings for ADM1266

On Wed, Jun 24, 2020 at 06:17:36PM +0300, alexandru.tach...@analog.com wrote: > From: Alexandru Tachici > > Add bindings for the Analog Devices ADM1266 sequencer. > > Signed-off-by: Alexandru Tachici > --- > .../bindings/hwmon/adi,adm1266.yaml | 56 +++ > 1 file

Re: [PATCH 5/5] tracing: toplevel d_entry already initialized

On Fri, 3 Jul 2020 10:06:12 +0800 Wei Yang wrote: > Currently we have following call flow: > > tracer_init_tracefs() > tracing_init_dentry() > event_trace_init() > tracing_init_dentry() > > This shows tracing_init_dentry() is called twice in this flow and this

Re: [PATCH v5 2/4] dt-bindings: regulator: Add labibb regulator

On Mon, 22 Jun 2020 18:11:08 +0530, Sumit Semwal wrote: > From: Nisha Kumari > > Adding the devicetree binding for labibb regulator. > > Signed-off-by: Nisha Kumari > Signed-off-by: Sumit Semwal > [sumits: cleanup as per review comments and update to yaml] > > --- > v5: Addressed review

Re: [PATCH 1/2] KVM: X86: Move ignore_msrs handling upper the stack

On 09/07/20 23:50, Peter Xu wrote: >> Sean: Objection your honor. >> Paolo: Overruled, you're wrong. >> Sean: Phooey. >> >> My point is that even though I still object to this series, Paolo has final >> say. > > I could be wrong, but I feel like Paolo was really respecting your input, as > always.

Re: [PATCH v5 1/2] dt-bindings: phy: add bcm63xx-usbh bindings

On Fri, Jun 19, 2020 at 12:00:34PM +0200, Álvaro Fernández Rojas wrote: > Document BCM63xx USBH PHY bindings. > > Signed-off-by: Álvaro Fernández Rojas > Reviewed-by: Florian Fainelli > --- > v5: no changes. > v4: conditionally require 1/2 clocks and fix clock/reset values. > v3: no changes.

[merged][PATCH v3 00/16] Make the user mode driver code a better citizen

I have merged all of this into my exec-next tree. The code is also available on the frozen branch: git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm/user-namespace.git usermode-driver-cleanup The range-diff from the last posted version is below. I was asked "Is there a simpler

Re: [PATCH V2 0/3] riscv: Enable LOCKDEP

On Sat, 27 Jun 2020 06:57:05 PDT (-0700), guo...@kernel.org wrote: From: Guo Ren Lockdep is needed by proving the spinlocks and rwlocks. To support it, we need to add TRACE_IRQFLAGS codes in kernel/entry.S. These patches follow Documentation/irqflags-tracing.txt. Fixup 2 bugs that block the

Re: [PATCH 2/2] PCI/AER: Log correctable errors as warning, not error

On Tue, Jul 07, 2020 at 07:14:01PM -0500, Bjorn Helgaas wrote: > From: Matt Jolly > > PCIe correctable errors are recovered by hardware with no need for software > intervention (PCIe r5.0, sec 6.2.2.1). > > Reduce the log level of correctable errors from KERN_ERR to KERN_WARNING. > > The bug

Re: [PATCH 3/5] tracing: save one trace_event->type by using __TRACE_LAST_TYPE

On Fri, 3 Jul 2020 10:06:10 +0800 Wei Yang wrote: > Static defined trace_event->type stops at (__TRACE_LAST_TYPE - 1) and > dynamic trace_event->type starts from (__TRACE_LAST_TYPE + 1). > > To save one trace_event->type index, let's use __TRACE_LAST_TYPE. When I wrote this code, I purposely

Re: [PATCH v2 2/4] remoteproc: k3-r5: Add a remoteproc driver for R5F subsystem

Hi Mathieu, On 7/9/20 1:10 PM, Mathieu Poirier wrote: Good day Suman, On Mon, Jun 29, 2020 at 09:49:20PM -0500, Suman Anna wrote: The TI K3 family of SoCs typically have one or more dual-core Arm Cortex R5F processor clusters/subsystems (R5FSS). This R5F subsystem/cluster can be configured at

Re: [PATCH v3] spi: use kthread_create_worker() helper

On Thu, 9 Jul 2020 08:50:07 +0200, Marek Szyprowski wrote: > Use kthread_create_worker() helper to simplify the code. It uses > the kthread worker API the right way. It will eventually allow > to remove the FIXME in kthread_worker_fn() and add more consistency > checks in the future. Applied to

Re: [PATCH] spi: use kthread_create_worker() helper

On Wed, 8 Jul 2020 09:09:00 +0200, Marek Szyprowski wrote: > Since commit 4977caef05aa ("kthread: work could not be queued when worker > being destroyed") there is a warning when kworker is used without the > internal 'task' entry properly initialized. Fix this by using > a kthread_create_worker()

Re: [PATCH v3] ASoC: atmel-classd: remove codec component

On Wed, 8 Jul 2020 13:12:49 +0300, Codrin Ciubotariu wrote: > The CPU and the codec both are represented now as components, so for > CLASS-D we are registering two componenets with the same name. Since > there is no actual codec, we will merge the codec component into the > CPU one and use a dummy

Re: [PATCH] ASoC: atmel-pdmic: remove codec component

On Wed, 8 Jul 2020 19:33:59 +0300, Codrin Ciubotariu wrote: > The CPU and the codec both are represented now as components, so for > PDMIC we are registering two componenets with the same name. Since > there is no actual codec, we will merge the codec component into the > CPU one and use a dummy

Re: [PATCH] SPI SUBSYSTEM: Replace HTTP links with HTTPS ones

On Wed, 8 Jul 2020 21:44:00 +0200, Alexander A. Klimov wrote: > Rationale: > Reduces attack surface on kernel devs opening the links for MITM > as HTTPS traffic is much harder to manipulate. > > Deterministic algorithm: > For each file: > If not .svg: > For each line: > If doesn't

Re: [PATCH][next] spi: atmel: remove redundant label out_free

On Thu, 9 Jul 2020 11:12:03 +0100, Colin King wrote: > The error exit label out_free is no longer being used, it is redundant > and can be removed. > > Cleans up warning: > drivers/spi/spi-atmel.c:1680:1: warning: label ‘out_free’ defined but not > used [-Wunused-label] Applied to

Re: [PATCH 1/2] ASoC: tlv320adcx140: Add ASI enable for channel 5-8

On Thu, 9 Jul 2020 13:51:28 -0500, Dan Murphy wrote: > Add the ALSA controls to enable the ASI for channels 5-8 Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [1/2] ASoC: tlv320adcx140: Add ASI enable for channel 5-8 commit:

Re: [PATCH v2] spi: use kthread_create_worker() helper

On Wed, 8 Jul 2020 14:33:49 +0200, Marek Szyprowski wrote: > Use kthread_create_worker() helper to simplify the code. It uses > the kthread worker API the right way. It will eventually allow > to remove the FIXME in kthread_worker_fn() and add more consistency > checks in the future. Applied to

Re: [PATCH 2/5] tracing: simplify the logic by defining next to be "lasst + 1"

On Fri, 3 Jul 2020 10:06:09 +0800 Wei Yang wrote: > The value to be used and compared in trace_search_list() is "last + 1". > Let's just define next to be "last + 1" instead of doing the addition > each time. Yeah, this is a nice clean up. I'll take this one. -- Steve > > Signed-off-by: Wei

Re: [PATCH 1/5] tracing: use union to simplify the trace_event_functions initialization

On Fri, 3 Jul 2020 10:06:08 +0800 Wei Yang wrote: > There are for 4 fields in trace_event_functions with the same type of > trace_print_func. Initialize them in register_trace_event() one by one > looks redundant. I have mixed emotions about this patch. Yeah, it consolidates it a bit, but it

[PATCH 6/6] drivers: thermal: tsens: add set_trip support for 8960

Add custom set_trip function for 8960 needed to set trip point to the tsens driver for 8960 driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 78 +++ 1 file changed, 78 insertions(+) diff --git a/drivers/thermal/qcom/tsens-8960.c

[PATCH 0/6] Add support for ipq8064 tsens

Ipq8064 SoCs tsens driver is based on 8960 tsens driver. This patchset expand the 8960 unused driver with interrupt support and set_trip point. Ipq8064 needs to registed with a syscon phandle as the tsens regs on this platform are shared with the gcc controller. Ansuel Smith (6): drivers:

[PATCH 2/6] drivers: thermal: tsens: add ipq8064 support

Ipq8064 SoCs based use the same 8960 driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 39c4462e38f6..2985a064a0d1 100644 --- a/drivers/thermal/qcom/tsens.c

[PATCH 3/6] dt-bindings: thermal: tsens: document ipq8064 bindings

Document the use of regmap phandle for ipq8064 SoCs Signed-off-by: Ansuel Smith --- .../bindings/thermal/qcom-tsens.yaml | 51 --- 1 file changed, 44 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml

[PATCH 4/6] drivers: thermal: tsens: add interrupt support for 9860 driver

Add interrupt support for 9860 tsens driver used to set thermal trip point for the system. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 196 +++--- drivers/thermal/qcom/tsens.h | 1 + 2 files changed, 183 insertions(+), 14 deletions(-) diff

[PATCH 5/6] drivers: thermal: tsens: add support for custom set_trip function

8960 tsens driver have a custom implementation to set set_trip function. Permit the generic driver to use the custom function if provided. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 4 drivers/thermal/qcom/tsens.h | 2 ++ 2 files changed, 6 insertions(+) diff --git

[PATCH 1/6] drivers: thermal: tsens: load regmap from phandle for 8960

Devices based on 8060 tsens driver (ipq8064) use the reg of the gcc driver. Permit to load the regmap from a syscon phandle instead of fail as the reg are already used by another driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 9 +++-- 1 file changed, 7

Re: [PATCH 2/4] dma-pool: Get rid of dma_in_atomic_pool()

On Thu, 9 Jul 2020, Nicolas Saenz Julienne wrote: > The function is only used once and can be simplified to a one-liner. > > Signed-off-by: Nicolas Saenz Julienne I'll leave this one to Christoph to decide on. One thing I really liked about hacking around in kernel/dma is the coding style,

Re: [PATCH 1/2] KVM: X86: Move ignore_msrs handling upper the stack

On Thu, Jul 09, 2020 at 02:26:52PM -0700, Sean Christopherson wrote: > On Thu, Jul 09, 2020 at 05:09:19PM -0400, Peter Xu wrote: > > Again, using host_initiated or not should be a different issue? Frankly > > speaking, I don't know whether it's an issue or not, but it's different from > > what

Re: [PATCH] dma-pool: use single atomic pool for both DMA zones

On Wed, 8 Jul 2020, Christoph Hellwig wrote: > On Wed, Jul 08, 2020 at 06:00:35PM +0200, Nicolas Saenz Julienne wrote: > > On Wed, 2020-07-08 at 17:35 +0200, Christoph Hellwig wrote: > > > On Tue, Jul 07, 2020 at 02:28:04PM +0200, Nicolas Saenz Julienne wrote: > > > > When allocating atomic DMA

Re: [PATCH] irqdomain/treewide: Keep firmware node unconditionally allocated

On Thu, Jul 09, 2020 at 11:53:06AM +0200, Thomas Gleixner wrote: > Quite some non OF/ACPI users of irqdomains allocate firmware nodes of type > IRQCHIP_FWNODE_NAMED or IRQCHIP_FWNODE_NAMED_ID and free them right after > creating the irqdomain. The only purpose of these FW nodes is to convey > name

Re: [PATCH] dma-pool: Do not allocate pool memory from CMA

On Wed, 8 Jul 2020, Nicolas Saenz Julienne wrote: > There is no guarantee to CMA's placement, so allocating a zone specific > atomic pool from CMA might return memory from a completely different > memory zone. So stop using it. > > Fixes: c84dc6e68a1d ("dma-pool: add additional coherent pools to

Re: [PATCH v6 08/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register

On Wed, Jul 08, 2020 at 03:00:12PM +0530, Kishon Vijay Abraham I wrote: > Commit 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe > controller") in order to update Vendor ID, directly wrote to > PCI_VENDOR_ID register. However PCI_VENDOR_ID in root port configuration > space is

[PATCH net-next v6 4/4] net: enetc: Use DT protocol information to set up the ports

From: Alex Marginean Use DT information rather than in-band information from bootloader to set up MAC for XGMII. For RGMII use the DT indication in addition to RGMII defaults in hardware. However, this implies that PHY connection information needs to be extracted before netdevice creation, when

Re: [PATCH bpf] selftests: bpf: fix detach from sockmap tests

On 7/9/20 1:51 PM, Lorenz Bauer wrote: Fix sockmap tests which rely on old bpf_prog_dispatch behaviour. In the first case, the tests check that detaching without giving a program succeeds. Since these are not the desired semantics, invert the condition. In the second case, the clean up code

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