Jim Mattson writes:
> On Thu, Jul 9, 2020 at 10:15 AM Paolo Bonzini wrote:
>>
>> Commit 850448f35aaf ("KVM: nVMX: Fix VMX preemption timer migration",
>> 2020-06-01) accidentally broke nVMX live migration from older version
>> by changing the userspace ABI. Restore it and, while at it, ensure
>
Commit 850448f35aaf ("KVM: nVMX: Fix VMX preemption timer migration",
2020-06-01) accidentally broke nVMX live migration from older version
by changing the userspace ABI. Restore it and, while at it, ensure
that vmx->nested.has_preemption_timer_deadline is always initialized
according to the KVM_S
On Wed, Jul 8, 2020 at 7:50 PM Mickaël Salaün wrote:
> On 08/07/2020 15:49, Arnd Bergmann wrote:
> > On Wed, Jul 8, 2020 at 3:04 PM Mickaël Salaün wrote:
> >> On 08/07/2020 10:57, Arnd Bergmann wrote:
> >>> On Tue, Jul 7, 2020 at 8:10 PM Mickaël Salaün wrote:
> >>>
> >>> It looks like all you ne
Hi,
inline one more thing I forgot to comment on in my previous mail
On Thu, Jul 09, 2020 at 09:30:11PM +0530, Sandeep Maheswaram wrote:
> Add interconnect support in dwc3-qcom driver to vote for bus
> bandwidth.
>
> This requires for two different paths - from USB master to
> DDR slave. The oth
On 09/07/20 19:12, Jim Mattson wrote:
>> +
>> + /* The processor ignores EFER.LMA, but svm_set_efer needs it. */
>> + efer &= ~EFER_LMA;
>> + if ((nested_vmcb->save.cr0 & X86_CR0_PG)
>> + && (nested_vmcb->save.cr4 & X86_CR4_PAE)
>> + && (efer & EFER_LME))
>> +
On 09/07/20 19:16, Markus Elfring wrote:
>> +mempool_destroy(virtscsi_cmd_pool);
>> +virtscsi_cmd_pool = NULL;
>> +kmem_cache_destroy(virtscsi_cmd_cache);
>> +virtscsi_cmd_cache = NULL;
>> return ret;
>> }
>
> How do you think about to add a jump target so that the execution
On 09/07/20 19:23, Jim Mattson wrote:
> On Thu, Jul 9, 2020 at 10:15 AM Paolo Bonzini wrote:
>>
>> Commit 850448f35aaf ("KVM: nVMX: Fix VMX preemption timer migration",
>> 2020-06-01) accidentally broke nVMX live migration from older version
>> by changing the userspace ABI. Restore it and, while
On Thu, Jul 9, 2020 at 10:15 AM Paolo Bonzini wrote:
>
> Commit 850448f35aaf ("KVM: nVMX: Fix VMX preemption timer migration",
> 2020-06-01) accidentally broke nVMX live migration from older version
> by changing the userspace ABI. Restore it and, while at it, ensure
> that vmx->nested.has_preemp
Power Management Controller (PMC) can override the PLLM clock settings,
including the enable-state. Although PMC could only act as a second level
gate, meaning that PLLM needs to be enabled by the Clock and Reset
Controller (CaR) anyways if we want it to be enabled. Hence, when PLLM is
overridden b
Hi Sandeep,
On Thu, Jul 09, 2020 at 09:30:11PM +0530, Sandeep Maheswaram wrote:
> Add interconnect support in dwc3-qcom driver to vote for bus
> bandwidth.
>
> This requires for two different paths - from USB master to
> DDR slave. The other is from APPS master to USB slave.
>
> Signed-off-by: S
Hello,
On Wed, Jul 08, 2020 at 03:19:30PM +0800, Frank Lee wrote:
> Since we don't really have to care about the existing DT for boards,
> it would be great to make the gpio banks supplies required.
What if the borad doesn't use one of the banks? How would
I describe such a board if defining supp
On Mon 29 Jun 2020 at 22:39, Martin Blumenstingl
wrote:
> While trying to figure out how to set up the video clocks on the 32-bit
> SoCs I found that the current clock tree is missing two gates. This adds
> the missing gates based on evidence found in the public S805 datasheet,
> the GXBB cloc
> kmem_cache_destroy and mempool_destroy can correctly handle
> null pointer parameter, so there is no need to check if the
> parameter is null before calling kmem_cache_destroy and
> mempool_destroy.
Can another imperative wording be preferred for the change description?
…
> +++ b/drivers/scsi/
Commit 850448f35aaf ("KVM: nVMX: Fix VMX preemption timer migration",
2020-06-01) accidentally broke nVMX live migration from older version
by changing the userspace ABI. Restore it and, while at it, ensure
that vmx->nested.has_preemption_timer_deadline is always initialized
according to the KVM_S
I noticed on Nexus 7 that after rebooting from downstream kernel to
upstream, the GPIO interrupt is triggering non-stop despite interrupts
being disabled for all of GPIOs. This happens because Nexus 7 uses a
soft-reboot, meaning that bootloader should take care of resetting
hardware, but the bootlo
The requested interrupt is never released by the driver. Fix this by
using the resource-managed variant of request_threaded_irq().
Fixes: ab3dd9cc24d4 ("gpio: max77620: Fix interrupt handling")
Cc: # 5.5+
Reviewed-by: Andy Shevchenko
Acked-by: Laxman Dewangan
Signed-off-by: Dmitry Osipenko
---
The MAX77620_GPIO_NR enum value represents the total number of GPIOs,
let's use it instead of a raw value in order to improve the code's
readability a tad.
Reviewed-by: Andy Shevchenko
Acked-by: Laxman Dewangan
Signed-off-by: Dmitry Osipenko
---
drivers/gpio/gpio-max77620.c | 6 +++---
1 file
Hello!
This series addresses a problem that I discovered on Nexus 7 device where
GPIO interrupts may be left enabled after bootloader and the driver isn't
prepared to this. It also makes a small improvements to the code, fixes the
non-released interrupt bug and converts driver to use irqchip templ
The platform_get_irq() returns a positive interrupt number on success and
negative error code on failure (zero shouldn't ever happen in practice, it
would produce a noisy warning). Hence let's return the error code directly
instead of overriding it with -ENODEV.
Suggested-by: Andy Shevchenko
Revi
This change addresses one of the GPIO-core TODOs for the MAX77620 driver
which requires modern drivers to use the irqchip template. Instead of
using the GPIO's irqchip-helpers for creating the IRQ domain, the
gpio_irq_chip structure is now filled by the driver itself and then
gpiochip_add_data() ta
The gpiochip_add_data() takes care of setting the of_node to the parent's
device of_node, hence there is no need to do it manually in the driver's
code. This patch corrects the parent's device pointer and removes the
unnecessary setting of the of_node.
Suggested-by: Andy Shevchenko
Reviewed-by: A
On Thu, Jul 9, 2020 at 2:55 AM Paolo Bonzini wrote:
>
> AMD doesn't specify (unlike Intel) that EFER.LME, CR0.PG and
> EFER.LMA must be consistent, and for SMM state restore they say that
> "The EFER.LMA register bit is set to the value obtained by logically
> ANDing the SMRAM values of EFER.LME,
On Wed, Jul 08, 2020 at 08:33:49AM -0400, j...@joelfernandes.org wrote:
>
>
> On July 3, 2020 10:08:28 AM EDT, madhuparnabhowmi...@gmail.com wrote:
> >From: Madhuparna Bhowmik
> >
> >list/hlist_for_each_entry_rcu() provides an optional cond argument
> >to specify the lock held in the updater sid
On Thu, 09 Jul 2020 10:01:57 +0200, Miquel Raynal wrote:
> Silvaco provide a dual-role I3C master.
>
> Description is rather simple: it needs a register mapping, three
> clocks and an interrupt.
>
> Signed-off-by: Miquel Raynal
> ---
> .../bindings/i3c/svc,i3c-master.yaml | 59
On Wed, 2020-07-08 at 15:46 +0200, Bartosz Szczepanek wrote:
> Starting from commit "thermal/int340x_thermal: Don't require IDSP to
> exist", priv->current_uuid_index is initialized to -1. This value may
> be passed to int3400_thermal_run_osc() from int3400_thermal_set_mode,
> contributing to page
On Wed, 08 Jul 2020 15:00:15 +0530, Kishon Vijay Abraham I wrote:
> Add PCIe EP mode dt-bindings for TI's J721E SoC.
>
> Signed-off-by: Kishon Vijay Abraham I
> Reviewed-by: Rob Herring
> ---
> .../bindings/pci/ti,j721e-pci-ep.yaml | 89 +++
> 1 file changed, 89 insertio
On Thu, Jul 09, 2020 at 01:48:18PM +0300, Dan Carpenter wrote:
> The __per_cpu_offset[] array has "nr_cpu_ids" elements so change the >
> >= to prevent a read one element beyond the end of the array.
>
> Fixes: 0504bc41a62c ("kernel/smp: Provide CSD lock timeout diagnostics")
> Signed-off-by: Dan
A simple optimization for migrate_vma_*() when the source vma is not an
anonymous vma and a new test case to exercise it.
This is based on linux-mm and is for Andrew Morton's tree.
Ralph Campbell (2):
mm/migrate: optimize migrate_vma_setup() for holes
mm/migrate: add migrate-shared test for mi
Add a migrate_vma_*() self test for mmap(MAP_SHARED) to verify that
!vma_anonymous() ranges won't be migrated.
Signed-off-by: Ralph Campbell
---
tools/testing/selftests/vm/hmm-tests.c | 35 ++
1 file changed, 35 insertions(+)
diff --git a/tools/testing/selftests/vm/hmm-t
When migrating system memory to device private memory, if the source
address range is a valid VMA range and there is no memory or a zero page,
the source PFN array is marked as valid but with no PFN. This lets the
device driver allocate private memory and clear it, then insert the new
device privat
On Thu, Jul 9, 2020 at 9:48 AM Bjorn Andersson
wrote:
>
> On Thu 09 Jul 09:17 PDT 2020, Rob Clark wrote:
>
> > On Wed, Jul 8, 2020 at 10:01 PM Bjorn Andersson
> > wrote:
> [..]
> > > @@ -678,7 +680,11 @@ static int arm_smmu_init_domain_context(struct
> > > iommu_domain *domain,
> > > if
On Wed, 08 Jul 2020 15:19:32 +0800, Frank Lee wrote:
> Add a binding for A100's SID controller.
>
> Signed-off-by: Frank Lee
> ---
> Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
My bot found errors running 'make dt_binding_c
On 7/9/20 10:25 AM, vamshi.krishna.go...@intel.com wrote:
From: Brent Lu
Add a dapm route to provide ssp mclk/sclk early
for DMIC on SSP0(rt5514) and Headset on SSP1(rt5663)
since sclk for both codecs are different the
struct now defines SSP0 and SSP1 mclk , sclk separately
This change ensu
On Wed, Jul 08, 2020 at 03:19:30PM +0800, Frank Lee wrote:
> Since we don't really have to care about the existing DT for boards,
> it would be great to make the gpio banks supplies required.
>
> Signed-off-by: Frank Lee
> ---
> .../devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
On Wed, Jul 08, 2020 at 12:07:47PM +0800, Chris Ruehl wrote:
> Add documentation for the newly added DTS support in the shtc1 driver.
> To align with the drivers logic to have high precision by default
> a boolean sensirion,low_precision is used to switch to low precision.
>
> Signed-off-by: Chris
On Wed, 08 Jul 2020 15:19:30 +0800, Frank Lee wrote:
> Since we don't really have to care about the existing DT for boards,
> it would be great to make the gpio banks supplies required.
>
> Signed-off-by: Frank Lee
> ---
> .../devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
: x86_64-randconfig-r004-20200709 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project
02946de3802d3bc65bc9f2eb9b8d4969b5a7add8)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin
From: Laurentiu Palcu
This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
Some of its capabilities include:
* 4K@60fps;
* HDR10;
* one graphics and 2 video pipelines;
* on-the-fly decompression of compressed video and graphics;
The reference manual can be found here:
On Thu 09 Jul 09:17 PDT 2020, Rob Clark wrote:
> On Wed, Jul 8, 2020 at 10:01 PM Bjorn Andersson
> wrote:
[..]
> > @@ -678,7 +680,11 @@ static int arm_smmu_init_domain_context(struct
> > iommu_domain *domain,
> > if (smmu_domain->smmu)
> > goto out_unlock;
> >
> > -
From: Laurentiu Palcu
Add bindings for iMX8MQ Display Controller Subsystem.
Signed-off-by: Laurentiu Palcu
---
.../bindings/display/imx/nxp,imx8mq-dcss.yaml | 84 +++
1 file changed, 84 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-
On Thu, Jun 25, 2020 at 04:03:11PM +0800, Zhenyu Ye wrote:
> @@ -189,8 +195,9 @@ static inline void flush_tlb_page_nosync(struct
> vm_area_struct *vma,
> unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
>
> dsb(ishst);
> - __tlbi(vale1is, addr);
> - __tlbi_user(val
From: Laurentiu Palcu
This patch adds the node for iMX8MQ Display Controller Subsystem.
Signed-off-by: Laurentiu Palcu
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/ar
From: Laurentiu Palcu
Hi,
This patchset adds initial DCSS support for iMX8MQ chip. Initial support
includes only graphics plane support (no video planes), no HDR10 capabilities,
no graphics decompression (only linear, tiled and super-tiled buffers allowed).
Support for the rest of the features
From: Laurentiu Palcu
Component framework is needed by HDP driver.
Signed-off-by: Laurentiu Palcu
---
drivers/gpu/drm/imx/dcss/dcss-drv.c | 89 ++---
drivers/gpu/drm/imx/dcss/dcss-kms.c | 14 -
drivers/gpu/drm/imx/dcss/dcss-kms.h | 4 +-
3 files changed, 80 inserti
From: Laurentiu Palcu
Currently the drm/imx/ directory is compiled only if DRM_IMX is set. Adding a
new IMX related IP in the same directory would need DRM_IMX to be set, which
would
bring in also IPUv3 core driver...
The current patch would allow adding new IPs in the imx/ directory without
n
APPRAISE_BOOTPARAM has been marked as dependent on !ARCH_POLICY in compile
time, enforcing the appraisal whenever the kernel had the arch policy option
enabled.
However it breaks systems where the option is set but the system didn't
boot in a "secure boot" platform. In this scenario, anytime an ap
On Wed, Jul 1, 2020 at 4:10 PM Jason Wang wrote:
>
>
> On 2020/7/1 下午9:04, Eugenio Perez Martin wrote:
> > On Wed, Jul 1, 2020 at 2:40 PM Jason Wang wrote:
> >>
> >> On 2020/7/1 下午6:43, Eugenio Perez Martin wrote:
> >>> On Tue, Jun 23, 2020 at 6:15 PM Eugenio Perez Martin
> >>> wrote:
> On
On Wed, 08 Jul 2020 12:07:47 +0800, Chris Ruehl wrote:
> Add documentation for the newly added DTS support in the shtc1 driver.
> To align with the drivers logic to have high precision by default
> a boolean sensirion,low_precision is used to switch to low precision.
>
> Signed-off-by: Chris Ruehl
On Thu, Jul 09, 2020 at 12:13:44PM +0200, Dmitry Vyukov wrote:
> On Tue, Jul 7, 2020 at 6:26 PM Paul E. McKenney wrote:
> >
> > On Tue, Jul 07, 2020 at 05:51:48PM +0200, Dmitry Vyukov wrote:
> > > On Sat, Jul 4, 2020 at 8:34 PM Dmitry Vyukov wrote:
> > > >
> > > > On Sat, Jul 4, 2020 at 6:45 PM P
On Thu, Jul 9, 2020 at 7:05 PM Artur Rojek wrote:
>
> Hey Andy,
>
> On 2020-07-09 17:43, Andy Shevchenko wrote:
> > On Thu, Jul 9, 2020 at 6:22 PM Artur Rojek
> > wrote:
> >>
> >> Hi all,
> >>
> >> v8 of this patchset introduces some structural changes, which I deemed
> >> worthy highlighting her
On 7/9/20 9:34 AM, Zi Yan wrote:
> On 9 Jul 2020, at 11:34, Randy Dunlap wrote:
>
>> Hi,
>>
>> I have a few comments on this.
>>
>> a. I reported it very early and should have been Cc-ed.
>>
>> b. A patch that applies to mmotm or linux-next would have been better
>> than a full replacement patch.
On Mon, Jun 1, 2020 at 12:19 PM Vadim Pasternak wrote:
>
> Add support for attributes composed from few registers.
> Such attributes could occupy from 2 to 4 sequential registers.
> For word size register space complex attribute can occupy up to two
attributes
> register, for byte size - up to f
The hardware only supports 4:2:0 or 4:0:0 (monochrome),
8-bit depth content.
Verify that the SPS refers to a supported bitstream, and refuse
unsupported bitstreams by failing at TRY_EXT_CTRLS time.
Given the JPEG compression level control is the only one
that needs setting, a specific ops is prov
The hardware only supports 4:2:2, 4:2:0 or 4:0:0 (monochrome),
8-bit or 10-bit depth content.
Verify that the SPS refers to a supported bitstream, and refuse
unsupported bitstreams by failing at TRY_EXT_CTRLS time.
The driver is currently broken on 10-bit and 4:2:2
so disallow those as well.
Sig
Hi all,
Small patchset to add a check at TRY_EXT_CTRLS time,
via the H264 SPS control and reject unsupported bitstreams.
Properly refusing to decode unsupported bitstreams
allows applications to cleanly fallback to software
decoding.
Note that Rockchip VDEC hardware is capable of decoding High-1
09.07.2020 17:57, Laxman Dewangan пишет:
>
>
> On Thursday 09 July 2020 01:53 AM, Dmitry Osipenko wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> The requested interrupt is never released by the driver. Fix this by
>> using the resource-managed variant of request_threa
On Thu, 9 Jul 2020 17:13:51 +0100
Mark Brown wrote:
> On Thu, Jul 09, 2020 at 10:01:18AM -0600, Shuah Khan wrote:
> > On 7/9/20 4:43 AM, Mauro Carvalho Chehab wrote:
>
> > > For coherency, if "blacklist/whitelist" won't be used anymore, an
> > > alternative to graylist should also be provided.
On Thu, Jul 09, 2020 at 09:10:06AM -0700, Dan Williams wrote:
> On Thu, Jul 9, 2020 at 8:39 AM Jason Gunthorpe wrote:
> >
> > On Thu, Jul 09, 2020 at 04:00:51PM +0100, Christoph Hellwig wrote:
> > > On Mon, Jul 06, 2020 at 06:59:32PM -0700, Dan Williams wrote:
> > > > The runtime firmware activati
On 9 Jul 2020, at 11:34, Randy Dunlap wrote:
> Hi,
>
> I have a few comments on this.
>
> a. I reported it very early and should have been Cc-ed.
>
> b. A patch that applies to mmotm or linux-next would have been better
> than a full replacement patch.
>
> c. I tried replacing what I believe is th
On 7/7/20 11:31 PM, Mathieu Poirier wrote:
> This set applies on top of [1] and refactors the STM32 platform code in
> order to attach to the M4 remote processor when it has been started by the
> boot loader.
>
> New to V5:
> 1) Added Bjorn's reviewed-by to patch 06.
> 2) Removed Loic's reviewe
On Mon, Jun 1, 2020 at 12:19 PM Vadim Pasternak wrote:
>
> Send "udev" event with environmental data in order to allow handling
> "ENV{}" variables in "udev" rules.
...
> +static int
> +mlxreg_hotplug_udev_event_send(struct kobject *kobj,
> + struct mlxreg_core_data
On Thu, 2020-07-09 at 17:13 +0100, Mark Brown wrote:
> On Thu, Jul 09, 2020 at 10:01:18AM -0600, Shuah Khan wrote:
> > On 7/9/20 4:43 AM, Mauro Carvalho Chehab wrote:
> > > For coherency, if "blacklist/whitelist" won't be used anymore, an
> > > alternative to graylist should also be provided.
> > W
On Thu, Jul 09, 2020 at 02:10:41PM +0200, Rafael J. Wysocki wrote:
> On Tue, Jul 7, 2020 at 10:04 PM Gustavo A. R. Silva
> wrote:
> >
> > Replace the existing /* fall through */ comments and its variants with
> > the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary
> > fall-throug
From: Lee Jones
Looks as though they've never been used.
Fixes the following W=1 kernel build warning(s):
In file included from sound/soc/codecs/rt5659.c:25:
In file included from sound/soc/codecs/rt5659.c:25:
sound/soc/codecs/rt5659.c:1232:2: warning: ‘rt5659_ad_monor_asrc_enum’ defined
b
From: Lee Jones
Looks as though the result of snd_soc_update_bits() has never been checked.
Fixes the following W=1 kernel build warning(s):
sound/soc/codecs/ak4458.c: In function ‘ak4458_set_dai_mute’:
sound/soc/codecs/ak4458.c:408:16: warning: variable ‘ret’ set but not
used [-Wunused-but-set
From: Lee Jones
Looks like these have been unchecked since the driver's inception in 2012.
Fixes the following W=1 kernel build warning(s):
sound/soc/ux500/ux500_msp_i2s.c: In function ‘flush_fifo_rx’:
sound/soc/ux500/ux500_msp_i2s.c:398:6: warning: variable ‘reg_val_DR’
set but not used [-Wunu
Fixes the following W=1 kernel build warning(s):
sound/soc/codecs/rt5631.c:72: warning: Function parameter or member
'component' not described in 'rt5631_write_index'
sound/soc/codecs/rt5631.c:72: warning: Function parameter or member
'reg' not described in 'rt5631_write_index'
sound/soc/codecs/rt
Fixes the following W=1 kernel build warning(s):
sound/soc/qcom/qdsp6/q6asm.c:924: warning: Function parameter or
member 'codec_profile' not described in 'q6asm_open_write'
Cc: Patrick Lai
Cc: Banajit Goswami
Cc: Srinivas Kandagatla
Cc: Vinod Koul
Signed-off-by: Pierre-Louis Bossart
---
sou
From: Lee Jones
Property name descriptions need to match exactly.
Fixes the following W=1 kernel build warning(s):
sound/soc/sunxi/sun4i-spdif.c:178: warning: Function parameter or
member 'reg_dac_txdata' not described in 'sun4i_spdif_quirks'
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
Cc: Philipp Za
From: Lee Jones
This is the only use of kerneldoc in the sourcefile and no
descriptions are provided.
Fixes the following W=1 kernel build warning(s):
sound/soc/codecs/tlv320aic26.c:138: warning: Function parameter or
member 'dai' not described in 'aic26_mute'
sound/soc/codecs/tlv320aic26.c:138
Fix W=1 warnings - missing fields in description
sound/soc/sunxi/sun4i-i2s.c:160: warning: Function parameter or
member 'bclk_dividers' not described in 'sun4i_i2s_quirks'
sound/soc/sunxi/sun4i-i2s.c:160: warning: Function parameter or member
'num_bclk_dividers' not described in 'sun4i_i2s_quirks
Fix W=1 warning. The table uni_tdm_hw is declared in a header included
by multiple C file. This isn't really a good practice but for now
using __maybe_unused makes the following warning go away.
sound/soc/sti/sti_uniperif.c:12:
sound/soc/sti/uniperif.h:1351:38: warning: ‘uni_tdm_hw’ defined but
no
From: Lee Jones
This is the only use of kerneldoc in the sourcefile and full
descriptions are not provided.
Fixes the following W=1 kernel build warning(s):
sound/soc/pxa/pxa-ssp.c:186: warning: Function parameter or member
'ssp' not described in 'pxa_ssp_set_scr'
Cc: Daniel Mack
Cc: Haojian
Hi Mathieu
On 7/7/20 11:00 PM, Mathieu Poirier wrote:
> This set provides functionality allowing the remoteproc core to attach to
> a remote processor that was started by another entity.
>
> New in V5:
> 1) Added Bjorn's reviewed-by.
> 2) Removed PM runtime call from patch 04.
> 3) Used a 'case'
On 7/9/20 9:07 AM, Andy Lutomirski wrote:
> On Thu, Jul 9, 2020 at 8:56 AM Dave Hansen wrote:
>> On 7/9/20 8:44 AM, Andersen, John wrote:
>>> Bits which are allowed to be pinned default to WP for CR0 and SMEP,
>>> SMAP, and UMIP for CR4.
>> I think it also makes sense to have FSGSB
The function is only used once and can be simplified to a one-liner.
Signed-off-by: Nicolas Saenz Julienne
---
kernel/dma/pool.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/kernel/dma/pool.c b/kernel/dma/pool.c
index 8cfa01243ed2..7363640fc91c 100644
--- a/ker
This is my attempt at fixing one of the regressions we've seen[1] after
the introduction of per-zone atomic pools.
This combined with "dma-pool: Do not allocate pool memory from CMA"[2]
should fix the boot issues on Jeremy's RPi4 setup.
[1] https://lkml.org/lkml/2020/7/2/974
[2] https://lkml.org/
When allocating DMA memory from a pool, the core can only guess which
atomic pool will fit a device's constraints. If it doesn't, get a safer
atomic pool and try again.
Fixes: c84dc6e68a1d ("dma-pool: add additional coherent pools to map to gfp
mask")
Reported-by: Jeremy Linton
Suggested-by: Rob
dma_coherent_ok() checks if a physical memory area fits a device's DMA
constraints.
Signed-off-by: Nicolas Saenz Julienne
---
include/linux/dma-direct.h | 1 +
kernel/dma/direct.c| 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/linux/dma-direct.h b/include/li
dma-pool's dev_to_pool() creates the false impression that there is a
way to grantee a mapping between a device's DMA constraints and an
atomic pool. It tuns out it's just a guess, and the device might need to
use an atomic pool containing memory from a 'safer' (or lower) memory
zone.
To help miti
On Wed, Jul 8, 2020 at 10:01 PM Bjorn Andersson
wrote:
>
> Some firmware found on various Qualcomm platforms traps writes to S2CR
> of type BYPASS and writes FAULT into the register. This prevents us from
> marking the streams for the display controller as BYPASS to allow
> continued scanout of th
On 7/7/20 11:31 PM, Mathieu Poirier wrote:
> Split function stm32_rproc_parse_fw() in two parts, the first one
> to parse the memory regions and the second one to load the
> resource table. That way parsing of the memory regions can be
> re-used when attaching to the remote processor.
>
> Main
On Fri, Jul 03, 2020 at 09:04:49AM -0700, Rob Clark wrote:
> On Fri, Jul 3, 2020 at 7:53 AM Sai Prakash Ranjan
> wrote:
> >
> > Hi Will,
> >
> > On 2020-07-03 19:07, Will Deacon wrote:
> > > On Mon, Jun 29, 2020 at 09:22:50PM +0530, Sai Prakash Ranjan wrote:
> > >> diff --git a/drivers/gpu/drm/msm
Hi Mathieu,
On 7/7/20 11:31 PM, Mathieu Poirier wrote:
> Introduce the required mechanic to set the state of the M4 in order
> to properly deal with scenarios where the co-processor has been
> started by another entity.
>
> Mainly based on the work published by Arnaud Pouliquen [1].
>
> [1]. htt
On Thu, Jul 09, 2020 at 10:01:18AM -0600, Shuah Khan wrote:
> On 7/9/20 4:43 AM, Mauro Carvalho Chehab wrote:
> > For coherency, if "blacklist/whitelist" won't be used anymore, an
> > alternative to graylist should also be provided.
> What is "graylist"? Does it mean in between allow/deny?
Yes.
On Thu, Jul 9, 2020 at 8:39 AM Jason Gunthorpe wrote:
>
> On Thu, Jul 09, 2020 at 04:00:51PM +0100, Christoph Hellwig wrote:
> > On Mon, Jul 06, 2020 at 06:59:32PM -0700, Dan Williams wrote:
> > > The runtime firmware activation capability of Intel NVDIMM devices
> > > requires memory transactions
On 2020-07-01 12:59, Sibi Sankar wrote:
The Protection Domains (PD) have a mechanism to keep its resources
enabled until the PD down indication is acked. Reorder the PD state
indication ack so that clients get to release the relevant resources
before the PD goes down.
Fixes: fbe639b44a82 ("soc:
On Thu, Jul 09, 2020 at 04:50:02PM +0100, Matthew Wilcox wrote:
> On Thu, Jul 09, 2020 at 11:11:11PM +0800, Alex Shi wrote:
> > Hi Kirill & Matthew,
> >
> > In the func call chain, from split_huge_page() to lru_add_page_tail(),
> > Seems tail pages are added to lru list at line 963, but in this sc
From: kernel test robot
drivers/net/phy/mscc/mscc_ptp.c:1496:1-3: WARNING: PTR_ERR_OR_ZERO can be used
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
Generated by: scripts/coccinelle/api/ptr_ret.cocci
Fixes: 7d272e63e097 ("net: phy: mscc: timestamping and PHC support")
CC: Antoine
On 7/9/20 6:53 AM, Michael Ellerman wrote:
Nicholas Piggin writes:
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/paravirt.h | 28
arch/powerpc/include/asm/qspinlock.h | 66 +++
arch/powerpc/include/asm/qspinlock_paravirt.h | 7 ++
On Mon, Jun 1, 2020 at 12:19 PM Vadim Pasternak wrote:
>
> Create the 'sysfs' attributes according to configuration provided
> through the capability register, which purpose is to indicate the
> actual number of the components within the particular group.
> Such components could be, for example th
On Tue, 7 Jul 2020, Andrii Nakryiko wrote:
> On Fri, Jul 3, 2020 at 7:47 AM Alan Maguire wrote:
> >
> > The bpf helper bpf_trace_printk() uses trace_printk() under the hood.
> > This leads to an alarming warning message originating from trace
> > buffer allocation which occurs the first time a
Hey Andy,
On 2020-07-09 17:43, Andy Shevchenko wrote:
On Thu, Jul 9, 2020 at 6:22 PM Artur Rojek
wrote:
Hi all,
v8 of this patchset introduces some structural changes, which I deemed
worthy highlighting here:
Can you remind me if I gave you tags on the previous version?
I received no tags
On Thu, Jul 9, 2020 at 7:55 AM wrote:
>
> As a part of UV1 platform removal, delete the efi=old_map option,
> which should no longer be needed.
Can you also update kernel_parameters.txt?
--Andy
On 7/9/20 4:43 AM, Mauro Carvalho Chehab wrote:
Em Tue, 7 Jul 2020 01:58:21 +0200
Tibor Raschko escreveu:
Allowlist/denylist terms are intuitive and action based which have a
globally uniform meaning.
Nobody has a problem understanding "blacklist" and "whitelist". These
are universally under
This path series aims to add interconnect support in
dwc3-qcom driver on SDM845 and SC7180 SoCs.
Changes from v7 -> v8
> Only driver change is pending all other patches are merged so dropped
from the series.
> Removed the device_is_bound call and getting speed from device tree
and rear
Adding maximum speed property for DWC3 USB node which can be used
for setting interconnect bandwidth.
Signed-off-by: Sandeep Maheswaram
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc
Add interconnect support in dwc3-qcom driver to vote for bus
bandwidth.
This requires for two different paths - from USB master to
DDR slave. The other is from APPS master to USB slave.
Signed-off-by: Sandeep Maheswaram
Signed-off-by: Chandana Kishori Chiluveru
Reviewed-by: Matthias Kaehlcke
-
On 09/07/2020 16:44, Rob Herring wrote:
On Sun, Jun 14, 2020 at 12:27 AM Navid Emamdoost
wrote:
in panfrost_job_hw_submit, pm_runtime_get_sync is called which
increments the counter even in case of failure, leading to incorrect
ref count. In case of failure, decrement the ref count before retu
On Thu, 9 Jul 2020 14:45:05 +0200
Peter Zijlstra wrote:
> On Fri, Jun 19, 2020 at 10:15:51PM +0800, kernel test robot wrote:
> > tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
> > sched/fifo
> > head: 8b700983de82f79e05b2c1136d6513ea4c9b22c4
> > commit: 616d91b68cd56bcb195
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