Add the support code for "1dwq" mdev type. This mdev type follows the
standard VFIO mdev flow. The "1dwq" type will export a single dedicated wq
to the mdev. The dwq will have read-only configuration that is configured
by the host. The mdev type does not support PASID and SVA and will match
the
Update some of the device commands in order to support usage by the virtual
device commands emulated by the vdcm. Expose some of the commands' raw
status so the virtual commands can utilize them accordingly.
Signed-off-by: Dave Jiang
Reviewed-by: Kevin Tian
---
drivers/dma/idxd/cdev.c |2
Add all the helper functions that supports the emulation of the commands
that are submitted to the device command register.
Signed-off-by: Dave Jiang
Reviewed-by: Kevin Tian
---
drivers/dma/idxd/registers.h | 16 +-
drivers/dma/idxd/vdev.c | 398
Add support for IMS enabling on the mediated device.
On the actual hardware the MSIX vector 0 is misc interrupt and handles
events such as administrative command completion, error reporting,
performance monitor overflow, and etc. The MSIX vectors 1...N
are used for descriptor completion
Create a mediated device through the VFIO mediated device framework. The
mdev framework allows creation of an mediated device by the driver with
portion of the device's resources. The driver will emulate the slow path
such as the PCI config space, MMIO bar, and the command registers. The
Add device support helper functions in preparation of adding VFIO
mdev support.
Signed-off-by: Dave Jiang
Reviewed-by: Kevin Tian
---
drivers/dma/idxd/device.c | 61 +
drivers/dma/idxd/idxd.h |4 +++
2 files changed, 65 insertions(+)
diff
From: Megha Dey
The dev-msi interrupts are to be allocated/freed only for custom devices,
not standard PCI-MSIX devices.
These interrupts are device-defined and they are distinct from the already
existing msi interrupts:
pci-msi: Standard PCI MSI/MSI-X setup format
platform-msi: Platform
In preparation for support of VFIO mediated device for idxd driver, the
enabling for Interrupt Message Store (IMS) interrupts is added for the idxd
base driver. DEV-MSI is the generic kernel support that mechanisms like
IMS can use to get their interrupts enabled. With IMS support the idxd
driver
From: Megha Dey
platform-msi.c provides a generic way to handle non-PCI message
signaled interrupts. However, it assumes that only the message
needs to be customized. Given that an MSI is just a write
transaction, some devices may need custom callbacks to
mask/unmask their interrupts.
Hence,
On Tue, 21 Jul 2020 17:20:13 +0200, Marcin Sloniewski wrote:
> Add the "seeed" vendor prefix for Seeed Technology Co., Ltd
> Website: https://www.seeedstudio.com/
>
> Signed-off-by: Marcin Sloniewski
> Acked-by: Rob Herring
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
The VFIO mediated device for idxd driver will provide a virtual DSA
device by backing it with a workqueue. The virtual device will be limited
with the wq configuration registers set to read-only. Add support and
helper functions for the handling of a DSA device with the configuration
registers
Add support for requesting interrupt handle from the device. The interrupt
handle is put in the interrupt handle field of a descriptor for the device
to determine which interrupt vector to use be it MSI-X or IMS. On the host
device, the interrupt handle is indexed to the MSI-X table. This allows a
v2:
IMS (now dev-msi):
With recommendations from Jason/Thomas/Dan on making IMS more generic:
Pass a non-pci generic device(struct device) for IMS management instead of mdev
Remove all references to mdev and symbol_get/put
Remove all references to IMS in common code and replace with dev-msi
remove
From: Megha Dey
When DEV_MSI is enabled, the dev_msi_default_domain is updated to the
base DEV-MSI irq domain. If interrupt remapping is enabled, we create
a new IR-DEV-MSI irq domain and update the dev_msi_default domain to
the same.
For X86, introduce a new irq_alloc_type which will be used
From: Megha Dey
Add support for the creation of a new DEV_MSI irq domain. It creates a
new irq chip associated with the DEV_MSI domain and adds the necessary
domain operations to it.
Add a new config option DEV_MSI which must be enabled by any
driver that wants to support device-specific
On Mon, 20 Jul 2020 20:03:19 -0700
Sean Christopherson wrote:
> +Weijiang
>
> On Mon, Jul 13, 2020 at 12:06:50PM -0700, Sean Christopherson wrote:
> > The only ideas I have going forward are to:
> >
> > a) Reproduce the bug outside of your environment and find a resource that
> > can go
On Tue, 2020-07-21 at 18:27 +0300, Mika Westerberg wrote:
> On Tue, Jul 21, 2020 at 11:01:55AM -0400, Lyude Paul wrote:
> > Sure thing. Also, feel free to let me know if you'd like access to one of
> > the
> > systems we saw breaking with this patch - I'm fairly sure I've got one of
> > them
> >
On Tue 21-07-20 10:33:25, Alan Stern wrote:
[...]
Thanks a lot for your analysis. The laptop is slowly dying so this can
be related.
> So yes, this looks like a hardware design error. Turning off
> autosuspend by writing to the sysfs power/control file is probably the
> best way to handle the
On Tue, Jul 21, 2020 at 3:15 AM kernel test robot wrote:
>
> Greeting,
>
> FYI, we noticed a -9.5% regression of will-it-scale.per_process_ops due to
> commit:
>
>
> commit: c738fbabb0ff62d0f9a9572e56e65d05a1b34c6a ("fsnotify: fold fsnotify()
> call into fsnotify_parent()")
Strange, that's a
On Tue, Jul 21, 2020 at 08:27:34AM -0700, Andy Lutomirski wrote:
> On Fri, Jul 17, 2020 at 1:02 AM Stefano Garzarella
> wrote:
> >
> > On Thu, Jul 16, 2020 at 08:12:35AM -0700, Kees Cook wrote:
> > > On Thu, Jul 16, 2020 at 03:14:04PM +0200, Stefano Garzarella wrote:
>
> > > access (IIUC) is
On Fri, Jul 17, 2020 at 5:48 PM Suman Anna wrote:
>
> Add a bindings document that lists the common TI SCI properties
> used by the K3 R5F and DSP remoteproc devices.
>
> Signed-off-by: Suman Anna
> ---
> v4: Addressed both of Rob's review comments on ti,sci-proc-ids property
> v3:
On 7/21/2020 10:31 AM, pet...@infradead.org wrote:
On Tue, Jul 21, 2020 at 10:23:36AM -0400, Liang, Kan wrote:
Patch 13 forces the slots event to be part of a metric group. In patch 7,
for a metric group, we only update the values once with slots event.
I think the normal case mentioned
Reviewed-by: Lyude Paul
Thanks!
On Tue, 2020-07-21 at 15:17 +, Wei Yongjun wrote:
> When using single_open() for opening, single_release() should be
> used instead of seq_release(), otherwise there is a memory leak.
>
> Fixes: 12885ecbfe62 ("drm/nouveau/kms/nvd9-: Add CRC support")
>
On Tue 21-07-20 08:33:33, Linus Torvalds wrote:
> On Mon, Jul 20, 2020 at 11:33 PM Michal Hocko wrote:
> >
> > The lockup is in page_unlock in do_read_fault and I suspect that this is
> > yet another effect of a very long waitqueue chain which has been
> > addresses by 11a19c7b099f ("sched/wait:
On Mon, Jul 13, 2020 at 04:31:30PM +0530, Kishon Vijay Abraham I wrote:
> Certain platforms like TI's J721E using Cadence PCIe IP can perform only
> 32-bit accesses for reading or writing to Cadence registers. Convert all
> read and write accesses to 32-bit in Cadence PCIe driver in preparation
>
Hello Marcin,
On 7/21/20 5:20 PM, Marcin Sloniewski wrote:
> Add support for Seeed Studio's stm32mp157c odyssey board.
> Board consists of SoM with stm32mp157c with 4GB eMMC and 512 MB DDR3 RAM
> and carrier board with USB and ETH interfaces, SD card connector,
> wifi and BT chip AP6236.
>
> In
On Tue, Jul 21, 2020 at 05:43:15PM +0200, Arnd Bergmann wrote:
> On Tue, Jul 21, 2020 at 5:07 PM Naresh Kamboju
> wrote:
> >
> > This might add little value.
> >
> > arm build sets failed on linux next 20200721.
> > The defconfig ( +config fragmen
On 21/07/2020 10:54, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-07-09 06:52:31)
This series adds the missing clock drivers and dts nodes to enable
the GPU on both SM8150 and SM8250.
Note an extra drm/msm patch [1] is required for SM8250.
As noted by Dmitry, GMU init fails with newer
On Tue, Jul 21, 2020 at 05:04:11PM +0200, Konrad Dybcio wrote:
> So.. is this a no-no?
>
> I of course would like to omit this entirely, but SMMUs on sdm630 and
> friends are REALLY picky.. What seems to happen is that when the
> driver tries to do things the "standard" way, hypervisor decides to
On Tue, Jul 21, 2020 at 5:07 PM Naresh Kamboju
wrote:
>
> This might add little value.
>
> arm build sets failed on linux next 20200721.
> The defconfig ( +config fragments ) builds PASS.
> The tinyconfig and allnoconfig FAILED with gcc-8, gcc-9 and gcc-10.
>
> make -sk KB
For SMP systems using IPI based TLB invalidation, looking at
current->active_mm is entirely reasonable. This then presents the
following race condition:
CPU0 CPU1
flush_tlb_mm(mm) use_mm(mm)
tsk->active_mm = mm;
On Tue, Jul 21, 2020 at 7:42 AM Sergey Senozhatsky
wrote:
>
> OK, so basically, extending printk_caller_id() so that for IRQ/NMI
> we will have more info than just "0x8000 + raw_smp_processor_id()".
I think it's really preempt_count() that we want to have there.
That has the
On 07/21, Peter Zijlstra wrote:
>
> --- a/kernel/sched/core.c
> +++ b/kernel/sched/core.c
> @@ -4193,9 +4193,6 @@ static void __sched notrace __schedule(b
> local_irq_disable();
> rcu_note_context_switch(preempt);
>
> - /* See deactivate_task() below. */
> - prev_state =
As the idle framework's architecture is incomplete, hence instead of
checking for just the processor type advertised in the device tree CPU
features; check for the Processor Version Register (PVR) so that finer
granularity can be leveraged while making processor checks.
Hence, making the PVR
POWER9 onwards the support for the registers HID1, HID4, HID5 has been
receded.
Although mfspr on the above registers worked in Power9, In Power10
simulator is unrecognized. Moving their assignment under the
check for machines lower than Power9
Signed-off-by: Pratik Rajesh Sampat
Reviewed-by:
v3: https://lkml.org/lkml/2020/7/17/1093
Changelog v3-->v4:
Based on comments from Nicholas Piggin and Gautham Shenoy,
1. Changed the naming of pnv_first_spr_loss_level from
pnv_first_fullstate_loss_level to deep_spr_loss_state
2. Make the P9 PVR check only on the top level function
Replace the variable name from using "pnv_first_spr_loss_level" to
"deep_spr_loss_state".
pnv_first_spr_loss_level is supposed to be the earliest state that
has OPAL_PM_LOSE_FULL_CONTEXT set, in other places the kernel uses the
"deep" states as terminology. Hence renaming the variable to be
Add development information for the devicetree files for hardware
by Purism SPC.
Signed-off-by: Martin Kepplinger
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 760b5d02e726..46ff4d67ff1c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@
Add entries for the imx8mq based Librem 5 phone. The "Birch" and
"Chestnut" hardware revisions are supported by r2. The "Dogwood"
revision by r3.
See https://puri.sm/products/librem-5/ and https://developer.puri.sm/Librem5/
for the schematics and more information.
Signed-off-by: Martin Kepplinger
From: "Angus Ainslie (Purism)"
Add a devicetree description for the Librem 5 phone. 4 hardware revisions
have been available. Some revisions include changes that need different
software to be run. So far, r3 ("Dogwood") is one such example, see:
"Aspen" r0 not supported
Hi,
On Mon, Jul 20, 2020 at 6:32 PM Peter Oh wrote:
>
> I'll take my word back.
> It's not this patch problem, but by others.
> I have 2 extra patches before the 3 patches so my system looks like
>
> backports from ath.git 5.6-rc1 + linux kernel 4.4 (similar to OpenWrt)
> On top of the working
On Fri, Jul 3, 2020 at 5:47 AM Ondrej Jirman wrote:
>
> This patchset fixes warnings in the example in display/bridge/nwl-dsi.yaml
> revealed during port of display/panel/rocktech,jh057n00900.yaml to
> yaml.
>
> Please take a look.
>
> thank you and regards,
> Ondrej Jirman
>
> Ondrej Jirman
On Mon, Jul 20, 2020 at 11:33 PM Michal Hocko wrote:
>
> The lockup is in page_unlock in do_read_fault and I suspect that this is
> yet another effect of a very long waitqueue chain which has been
> addresses by 11a19c7b099f ("sched/wait: Introduce wakeup boomark in
> wake_up_page_bit")
On 7/21/20 9:27 AM, Andy Lutomirski wrote:
> On Fri, Jul 17, 2020 at 1:02 AM Stefano Garzarella
> wrote:
>>
>> On Thu, Jul 16, 2020 at 08:12:35AM -0700, Kees Cook wrote:
>>> On Thu, Jul 16, 2020 at 03:14:04PM +0200, Stefano Garzarella wrote:
>
>>> access (IIUC) is possible without actually
Dear RT Folks,
I'm pleased to announce the 5.4.52-rt31 stable release.
This release is just an update to the new stable 5.4.52 version
and no RT specific changes have been made.
It did have some issues with merging of v5.4.48, which caused a
conflict and required some updates to "sched: Move
On Fri, Jul 17, 2020 at 1:02 AM Stefano Garzarella wrote:
>
> On Thu, Jul 16, 2020 at 08:12:35AM -0700, Kees Cook wrote:
> > On Thu, Jul 16, 2020 at 03:14:04PM +0200, Stefano Garzarella wrote:
> > access (IIUC) is possible without actually calling any of the io_uring
> > syscalls. Is that
On Tue, Jul 21, 2020 at 11:01:55AM -0400, Lyude Paul wrote:
> Sure thing. Also, feel free to let me know if you'd like access to one of the
> systems we saw breaking with this patch - I'm fairly sure I've got one of them
> locally at my apartment and don't mind setting up AMT/KVM/SSH
Probably no
On 21.07.20 12:02, Colin King wrote:
From: Colin Ian King
The pointer bitmap is being initialized with a plain integer 0,
fix this by initializing it with a NULL instead.
Cleans up sparse warning:
arch/x86/xen/enlighten_pv.c:876:27: warning: Using plain integer
as NULL pointer
Signed-off-by:
On Tue, Jul 21, 2020 at 12:35:01PM +0200, Vitaly Kuznetsov wrote:
> Wanpeng Li writes:
>
> > From: Wanpeng Li
> >
> > Prevent setting the tscdeadline timer if the lapic is hw disabled.
> >
> > Signed-off-by: Wanpeng Li
A Fixes and/or Cc stable is probably needed for this.
> > ---
> >
On Tue, Jul 21, 2020 at 09:41:26AM +0800, Boqun Feng wrote:
> Pure function movement, no functional changes. The move is made, because
> in a later change, __vmbus_open() will rely on some static functions
> afterwards, so we sperate the move and the modification of
> __vmbus_open() in two patches
On Tue, 21 Jul 2020 at 18:15, Nicolas Saenz Julienne
wrote:
>
> On Tue, 2020-07-21 at 17:45 +0530, Amit Pundir wrote:
> > On Tue, 21 Jul 2020 at 16:45, Nicolas Saenz Julienne
> > wrote:
> > > On Tue, 2020-07-21 at 14:24 +0530, Amit Pundir wrote:
> > > > On Tue, 21 Jul 2020 at 14:09, Nicolas
On Tue, Jul 21, 2020 at 09:41:25AM +0800, Boqun Feng wrote:
> Since the hypervisor always uses 4K as its page size, the size of PFNs
> used for gpadl should be HV_HYP_PAGE_SIZE rather than PAGE_SIZE, so
> adjust this accordingly as the preparation for supporting 16K/64K page
> size guests.
It may
- On Jul 21, 2020, at 11:19 AM, Peter Zijlstra pet...@infradead.org wrote:
> On Tue, Jul 21, 2020 at 11:15:13AM -0400, Mathieu Desnoyers wrote:
>> - On Jul 21, 2020, at 11:06 AM, Peter Zijlstra pet...@infradead.org
>> wrote:
>>
>> > On Tue, Jul 21, 2020 at 08:04:27PM +1000, Nicholas
Document device tree bindings of Seeed SoM and carrier board.
Signed-off-by: Marcin Sloniewski
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
Add support for Seeed Studio's stm32mp157c odyssey board.
Board consists of SoM with stm32mp157c with 4GB eMMC and 512 MB DDR3 RAM
and carrier board with USB and ETH interfaces, SD card connector,
wifi and BT chip AP6236.
In this patch only basic kernel boot is supported and interfacing
SD card
From: Franck LENORMAND
The SNVS can trigger interruption when detecting a SECurity
VIOlation.
This patch adds the definition of the resource.
Signed-off-by: Franck LENORMAND
---
include/dt-bindings/firmware/imx/rsrc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Franck LENORMAND
The SNVS is a hardware component in the imx8 SoC. One of its
function is to detect hardware attacks, in which case it creates
a SECurity VIOlation.
This patch adds the support for the reception of these secvio and
report it to the audit framework.
It also gives the
Add the "seeed" vendor prefix for Seeed Technology Co., Ltd
Website: https://www.seeedstudio.com/
Signed-off-by: Marcin Sloniewski
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Franck LENORMAND
This patch adds the documentation for the SECurity VIOlation
driver using the SCU on imx8x and imx8q.
Signed-off-by: Franck LENORMAND
---
.../bindings/arm/freescale/fsl,imx-sc-secvio.yaml | 34 ++
1 file changed, 34 insertions(+)
create mode 100644
From: Franck LENORMAND
This patch adds the API to retrieve the status of an IRQ.
It also adds values used to process SECVIO IRQ from the SCU.
Signed-off-by: Franck LENORMAND
---
drivers/firmware/imx/imx-scu-irq.c | 37 -
include/linux/firmware/imx/sci.h
From: Franck LENORMAND
This patch adds the APIs:
- imx_sc_seco_build_info: get commit and sha of SECO
- imx_sc_seco_secvio_enable: enable SNVS IRQ handling
- imx_sc_seco_secvio_config: configure SNVS register
- imx_sc_seco_secvio_dgo_config: configure SNVS DGO register
Signed-off-by: Franck
From: Franck LENORMAND
This patchset aims to add support for the SECurity VIOlation (SECVIO) of the
SNVS. A secvio is a signal emitted by the SNVS when a hardware attack
is detected. On imx8x and imx8q SoC, the SNVS is controlled by the
SECO and it is possible to interact with it using the SCU
On 2020-07-21 17:37, Georgi Djakov wrote:
When an interconnect path is being disabled, currently we don't
aggregate
the requests for it afterwards. But the re-aggregation step shouldn't
be
skipped, as it may leave the nodes with outdated bandwidth data. This
outdated data may actually keep the
On Tue, Jul 21, 2020 at 11:15:13AM -0400, Mathieu Desnoyers wrote:
> - On Jul 21, 2020, at 11:06 AM, Peter Zijlstra pet...@infradead.org wrote:
>
> > On Tue, Jul 21, 2020 at 08:04:27PM +1000, Nicholas Piggin wrote:
> >
> >> That being said, the x86 sync core gap that I imagined could be
On Tue, Jul 14, 2020 at 5:00 PM Richard Guy Briggs wrote:
> On 2020-07-14 16:29, Paul Moore wrote:
> > On Tue, Jul 14, 2020 at 1:44 PM Richard Guy Briggs wrote:
> > > On 2020-07-14 12:21, Paul Moore wrote:
> > > > On Mon, Jul 13, 2020 at 3:52 PM Richard Guy Briggs
> > > > wrote:
> > > > >
> >
On 7/21/20 7:31 AM, Vaibhav Gupta wrote:
> Drivers using legacy power management .suspen()/.resume() callbacks
> have to manage PCI states and device's PM states themselves. They also
> need to take care of standard configuration registers.
>
> Switch to generic power management framework using a
- On Jul 21, 2020, at 11:06 AM, Peter Zijlstra pet...@infradead.org wrote:
> On Tue, Jul 21, 2020 at 08:04:27PM +1000, Nicholas Piggin wrote:
>
>> That being said, the x86 sync core gap that I imagined could be fixed
>> by changing to rq->curr == rq->idle test does not actually exist because
On Tue, Jul 21, 2020 at 01:52:31PM +0300, Maxim Levitsky wrote:
> Linux kernel only supports logical block sizes which are power of two,
> at least 512 bytes and no more that PAGE_SIZE.
>
> Check this instead of crashing later on.
>
> Note that there is no need to check physical block size since
On Tue, Jul 21, 2020 at 1:17 AM Sedat Dilek wrote:
>
> You happen to know if I can configure in my ~/.gitconfig to pull
> linux-git stuff from two repositories - check first git.kernel.org
> then GitHub.
Just script it. IOW, do
git pull ..kernel.org..
git pull ...github..
and if you
On Mon, Jun 22, 2020 at 1:59 AM Bjorn Andersson
wrote:
>
> Migrate the Qualcomm TCSR mutex binding to YAML to allow validation.
>
> Reviewed-by: Vinod Koul
> Signed-off-by: Bjorn Andersson
> ---
>
> Changes since v1:
> - Actually remove the old binding doc
>
>
When using single_open() for opening, single_release() should be
used instead of seq_release(), otherwise there is a memory leak.
Fixes: 12885ecbfe62 ("drm/nouveau/kms/nvd9-: Add CRC support")
Reported-by: Hulk Robot
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/nouveau/dispnv50/crc.c | 1 +
> +/**
> + * blk_check_logical_block_size - check if logical block size is supported
> + * by the kernel
> + * @size: the logical block size, in bytes
> + *
> + * Description:
> + * This function checks if the block layers supports given block size
> + **/
> +bool
On Sat, 2020-07-18 at 17:29 -0700, Randy Dunlap wrote:
> Drop the repeated word "for" in a comment.
>
> Signed-off-by: Randy Dunlap
> Cc: Srinivas Pandruvada
> Cc: platform-driver-...@vger.kernel.org
> Cc: Darren Hart
> Cc: Andy Shevchenko
Acked-by: Srinivas Pandruvada
> ---
> This
On 7/21/20 5:11 AM, Kirill A. Shutemov wrote:
> On Mon, Jul 20, 2020 at 04:51:44PM -0700, Andrew Morton wrote:
>> On Sun, 19 Jul 2020 14:10:19 -0700 syzbot
>> wrote:
>>
>>> syzbot has found a reproducer for the following issue on:
>>>
>>> HEAD commit:4c43049f Add linux-next specific files
This patch is compile-tested only.
--Vaibhav Gupta
On Tue, Jul 21, 2020 at 08:04:27PM +1000, Nicholas Piggin wrote:
> That being said, the x86 sync core gap that I imagined could be fixed
> by changing to rq->curr == rq->idle test does not actually exist because
> the global membarrier does not have a sync core option. So fixing the
>
Drivers using legacy power management .suspen()/.resume() callbacks
have to manage PCI states and device's PM states themselves. They also
need to take care of standard configuration registers.
Switch to generic power management framework using a single
"struct dev_pm_ops" variable to take the
The sparse tool complains as follows:
drivers/mtd/nand/raw/pasemi_nand.c:71:5: warning:
symbol 'pasemi_device_ready' was not declared. Should it be static?
This function is not used outside of pasemi_nand.c, so this commit
marks it static.
Reported-by: Hulk Robot
Signed-off-by: Wei Yongjun
This might add little value.
arm build sets failed on linux next 20200721.
The defconfig ( +config fragments ) builds PASS.
The tinyconfig and allnoconfig FAILED with gcc-8, gcc-9 and gcc-10.
make -sk KBUILD_BUILD_USER=TuxBuild -C/linux -j32 ARCH=arm
CROSS_COMPILE=arm-linux-gnueabihf- HOSTCC=gcc
The sparse tool complains as follows:
drivers/soc/ti/knav_qmss_acc.c:453:23: warning:
symbol 'knav_acc_range_ops' was not declared. Should it be static?
'knav_acc_range_ops' is not used outside of knav_qmss_acc.c,
so marks it static.
Reported-by: Hulk Robot
Signed-off-by: Wei Yongjun
---
From: Colin Ian King
Currently when reading of the device property for "qcom,tx-deamp_3_5db"
fails the default is being assigned incorrectly to phy_dwc3->rx_eq. This
looks like a copy-n-paste error and in fact should be assigning the
default instead to phy_dwc3->tx_deamp_3_5db
So.. is this a no-no?
I of course would like to omit this entirely, but SMMUs on sdm630 and
friends are REALLY picky.. What seems to happen is that when the
driver tries to do things the "standard" way, hypervisor decides to
hang the platform or force a reboot. Not very usable.
This thing is
On Tue, Jul 21, 2020 at 10:52 AM Paolo Pisati
wrote:
>
> Add a cleanup() path upon exit, making it possible to run the test twice in a
> row:
>
> $ sudo bash -x ./txtimestamp.sh
> + set -e
> ++ ip netns identify
> + [[ '' == \r\o\o\t ]]
> + main
> + [[ 0 -eq 0 ]]
> + run_test_all
> + setup
> + tc
Hi Jens,
Is this fine to be picked?
On Mon, Jul 6, 2020 at 1:06 AM Kanchan Joshi wrote:
>
> Changes since v1:
> - updated commit description
> - added reviewed-by
>
> Kanchan Joshi (1):
> block: fix error code for zone-append
>
> block/bio.c | 2 +-
> 1 file changed, 1 insertion(+), 1
Sure thing. Also, feel free to let me know if you'd like access to one of the
systems we saw breaking with this patch - I'm fairly sure I've got one of them
locally at my apartment and don't mind setting up AMT/KVM/SSH
On Tue, 2020-07-21 at 15:22 +0300, Mika Westerberg wrote:
> Hi,
>
> [Sorry
On Tue, Jul 21, 2020 at 12:43:43PM +0530, Sai Prakash Ranjan wrote:
> Add "arm,coresight-loses-context-with-cpu" property to coresight
> ETM nodes to avoid failure of trace session because of losing
> context on entering deep idle states.
>
> Signed-off-by: Sai Prakash Ranjan
> ---
>
On Tue 21-07-20 15:17:49, Chris Down wrote:
> I understand the pragmatic considerations here, but I'm quite concerned
> about the maintainability and long-term ability to reason about a patch like
> this. For example, how do we know when this patch is safe to remove? Also,
> what other precedent
On 21/07/2020 14:42, Pratik Rajesh Sampat wrote:
> v2: https://lkml.org/lkml/2020/7/17/369
> Changelog v2-->v3
> Based on comments from Gautham R. Shenoy adding the following in the
> selftest,
> 1. Grepping modules to determine if already loaded
> 2. Wrapper to enable/disable states
> 3.
On 2020-07-21, Sergey Senozhatsky wrote:
>> That said, we have traditionally used not just "current process", but
>> also "last irq-level" as the context information, so I do think it
>> would be good to continue to do that.
>
> OK, so basically, extending printk_caller_id() so that for IRQ/NMI
>
Hi,
On Wed, Jul 22, 2020 at 12:37:41AM +1000, Nicholas Piggin wrote:
> Excerpts from Pratik Sampat's message of July 21, 2020 8:29 pm:
> >
> >
> > On 20/07/20 5:27 am, Nicholas Piggin wrote:
> >> Excerpts from Pratik Rajesh Sampat's message of July 18, 2020 4:53 am:
> >>> Replace the variable
Dear Kees, dear Andrew,
No idea, if you are aware of it yet, but three people verified that
commit 3202fa62fb (slub: relocate freelist pointer to middle of object)
causes a regression on AMD hardware [1].
It’d be great, if you took a look, and advised if this commit (and
follow-ups) should
On Mon, Jul 20, 2020 at 09:43:00AM -0700, Ashok Raj wrote:
> PASID and PRI capabilities are only enumerated in PF devices. VF devices
> do not enumerate these capabilites. IOMMU drivers also need to enumerate
> them before enabling features in the IOMMU. Extending the same support as
> PASID
Add a cleanup() path upon exit, making it possible to run the test twice in a
row:
$ sudo bash -x ./txtimestamp.sh
+ set -e
++ ip netns identify
+ [[ '' == \r\o\o\t ]]
+ main
+ [[ 0 -eq 0 ]]
+ run_test_all
+ setup
+ tc qdisc add dev lo root netem delay 1ms
Error: Exclusivity flag on, cannot
On Tue, Jul 21, 2020 at 12:40 PM Greg KH wrote:
>
> On Mon, Jul 20, 2020 at 09:19:38PM -0700, Fangrui Song wrote:
> > When CROSS_COMPILE is set (e.g. aarch64-linux-gnu-), if
> > $(CROSS_COMPILE)elfedit is found at /usr/bin/aarch64-linux-gnu-elfedit,
> > GCC_TOOLCHAIN_DIR will be set to /usr/bin/.
Changed 'unsigned' to 'unsigned int'.
This makes the code more uniform, and compliant with the kernel coding style.
Signed-off-by: Abanoub Sameh
---
drivers/gpio/gpio-sch.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpio/gpio-sch.c
Added a lined between declarations and other statements according to the
kenel coding style.
Signed-off-by: Abanoub Sameh
---
drivers/gpio/gpio-msic.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpio/gpio-msic.c b/drivers/gpio/gpio-msic.c
index 0bef1a5a9b70..84e00e0ab953
Changed 'unsigned' to 'unsigned int'.
This makes the code more uniform, and compliant with the kernel coding style.
Signed-off-by: Abanoub Sameh
---
drivers/gpio/gpio-msic.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpio/gpio-msic.c
Added a lined between a declaration and other statements according to the
kenel coding style.
Signed-off-by: Abanoub Sameh
---
drivers/gpio/gpio-pch.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio-pch.c b/drivers/gpio/gpio-pch.c
index 71dde7ceb7af..039822978eaf 100644
Removed space before comma to fix coding style error.
Signed-off-by: Abanoub Sameh
---
drivers/gpio/gpio-msic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-msic.c b/drivers/gpio/gpio-msic.c
index 84e00e0ab953..37664e7b3ddd 100644
---
Added a lined between a declaration and other statements according to the
kenel coding style.
Signed-off-by: Abanoub Sameh
---
drivers/gpio/gpio-sch.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio-sch.c b/drivers/gpio/gpio-sch.c
index d7cade67717b..3a1b1adb08c6 100644
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