The pull request you sent on Mon, 24 Aug 2020 18:43:43 +0200:
> git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux.git for-5.9-rc2-tag
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/9907ab371426da8b3cffa6cc3e4ae54829559207
Thank you!
--
Deet-doot-dot, I am a
On Mon, Aug 24, 2020 at 12:18:40PM -0700, Andrew Morton wrote:
> On Mon, 24 Aug 2020 07:53:54 -0400 Miaohe Lin wrote:
>
> > Add else to split mutually exclusive case and avoid some unnecessary check.
> >
> > --- a/mm/mempool.c
> > +++ b/mm/mempool.c
> > @@ -60,9 +60,8 @@ static void check_elemen
On Mon, 24 Aug 2020 07:53:54 -0400 Miaohe Lin wrote:
> Add else to split mutually exclusive case and avoid some unnecessary check.
>
> --- a/mm/mempool.c
> +++ b/mm/mempool.c
> @@ -60,9 +60,8 @@ static void check_element(mempool_t *pool, void *element)
> /* Mempools backed by slab allocato
Add DTSI of Variscite VAR-SOM-MX8MM System on Module in a basic version,
delivered with Variscite Symphony Evaluation kit. This version comes
with:
- 2 GB of RAM,
- 16 GB eMMC,
- Gigabit Ethernet PHY,
- 802.11 ac/a/b/g/n WiFi with 4.2 Bluetooth (Cypress CYW43353),
- CAN bus,
- Audio codec (n
Add a DTS for Variscite Symphony evaluation kit with VAR-SOM-MX8MM
System on Module.
Signed-off-by: Krzysztof Kozlowski
---
Changes since v3:
1. None.
Changes since v2:
1. Use 'led' as node name to be generic,
2. Remove orphaned pinctrl-names.
3. Use more specific regulator node names.
Change
Add a binding for the Variscite VAR-SOM-MX8MM System on Module.
Signed-off-by: Krzysztof Kozlowski
---
Based on top of:
https://lore.kernel.org/linux-arm-kernel/20200823172019.18606-1-k...@kernel.org/
Changes since v1:
1. None
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file c
Add a binding for the Variscite Symphony evaluation kit board with
VAR-SOM-MX8MM System on Module.
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. None
---
Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicet
commit 4346b7c7941d ("mmc: tegra: Add Tegra186 support")
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK is set for Tegra186 from the
beginning of its support in driver.
Tegra186 SDMMC hardware by default uses timeout clock (TMCLK) instead
of SDCLK and this quirk should not be set.
So, this patch remove thi
commit b5a84ecf025a ("mmc: tegra: Add Tegra210 support")
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK is set for Tegra210 from the
beginning of Tegra210 support in the driver.
Tegra210 SDMMC hardware by default uses timeout clock (TMCLK)
instead of SDCLK and this quirk should not be set.
So, this patch r
commit b5a84ecf025a ("mmc: tegra: Add Tegra210 support")
Tegra210 and later has a separate sdmmc_legacy_tm (TMCLK) used by Tegra
SDMMC hawdware for data timeout to achive better timeout than using
SDCLK and using TMCLK is recommended.
USE_TMCLK_FOR_DATA_TIMEOUT bit in Tegra SDMMC register
SDHCI_T
Tegra210/Tegra186/Tegra194 has incorrectly enabled
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK from the beginning of their support.
Tegra210 and later SDMMC hardware default uses sdmmc_legacy_tm (TMCLK)
all the time for hardware data timeout instead of SDCLK and this TMCLK
need to be kept enabled by Tegra
Tegra210 and later uses separate SDMMC_LEGACY_TM clock for data
timeout.
So, this patch adds "tmclk" to Tegra sdhci clock property in the
device tree binding.
Signed-off-by: Sowjanya Komatineni
---
.../bindings/mmc/nvidia,tegra20-sdhci.txt | 23 +-
1 file changed, 2
commit 5425fb15d8ee ("arm64: tegra: Add Tegra194 chip device tree")
Tegra194 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.
Tegra194 SDMMC advertises 12Mhz as timeout clock frequency in host
capability register.
So, this clo
commit 39cb62cb8973 ("arm64: tegra: Add Tegra186 support")
Tegra186 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.
Tegra186 SDMMC advertises 12Mhz as timeout clock frequency in host
capability register and uses it by default.
commit 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support")
Tegra210 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.
Tegra SDMMC advertises 12Mhz as timeout clock frequency in host
capability register.
So, this clock should be
Hi Arvind,
On Sun, Aug 23, 2020 at 11:25 PM Arvind Sankar wrote:
>
> - Using a dummy input operand with an arbitrary constant address for the
> read functions, instead of a global variable. This will prevent reads
> from being reordered across writes, while allowing memory loads to be
> cac
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: d012a7190fc1fd72ed48911e77ca97ba4521bccd
commit: 670d0a4b10704667765f7d18f7592993d02783aa sparse: use identifiers to
define address spaces
date: 10 weeks ago
config: m68k-randconfig-s031-20200824
Early Intel hardware implementations of Memory Bandwidth Allocation (MBA)
could only control bandwidth at the processor core level. This meant that
when two processes with different bandwidth allocations ran simultaneously
on the same core the hardware had to resolve this difference. It did so by
a
Quoting Xu Wang (2020-08-17 23:26:51)
> Replace a comma between expression statements by a semicolon.
>
> Signed-off-by: Xu Wang
> ---
Reviewed-by: Stephen Boyd
This series enumerates Memory Bandwidth Allocation (MBA) per-thread
feature and introduces a new resctrl file "thread_throttle_mode".
The file shows either "per-thread" on newer systems that implement the MBA
per-thread feature or "max" on other systems that allocate maximum
throttling per-core.
D
Some systems support per-thread Memory Bandwidth Allocation (MBA) which
applies a throttling delay value to each hardware thread instead of to
a core. Per-thread MBA is enumerated by CPUID.
No feature flag is shown in /proc/cpuinfo. User applications need to
check a resctrl throttling mode info fi
On Mon, 2020-08-24 at 12:54 -0600, Jim Cromie wrote:
> commit 59cf47e7df31 dyndbg: export ddebug_exec_queries
> left a few configs broken, fix them with ifdef-stubs.
>
> Rename the export to dynamic_debug_exec_queries(). This is a more
> canonical function name, instead of exposing the 'ddebug' i
On Mon, Aug 24, 2020 at 04:03:53PM -0300, Fabio Estevam wrote:
> On Mon, Aug 24, 2020 at 3:57 PM Krzysztof Kozlowski wrote:
>
> > True, I'll fix it up, thanks.
> >
> > Any comments for the Symphony DTS before v4?
>
> It looks good.
>
> One suggestion is to remove pinctrl_pcie0 for now and add i
Since upgrading to linux-next based on 5.9.0-rc1 and 5.9.0-rc2 I have
had my mouse pointer disappear soon after logging in, and I have
observed the system freezing temporarily when clicking on objects and
when typing text.
I have also found records of push buffer errors in dmesg output:
[ 6625.4503
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski
---
arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 12 ++
The ROHM BD71847 PMIC has a 32.768 kHz clock. Adding necessary parent
allows to probe the bd718x7 clock driver fixing boot errors:
bd718xx-clk bd71847-clk.1.auto: No parent clk found
bd718xx-clk: probe of bd71847-clk.1.auto failed with error -22
Signed-off-by: Krzysztof Kozlowski
---
a
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski
---
.../boot/dts/freescale/imx8mq-librem5-devkit.dts | 12 +++
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 14 +++---
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 2 +-
1 f
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski
---
arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi | 8 --
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 14 +++
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski
---
arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi | 4 ++--
1
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski
---
arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts | 12 ++-
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 2 +-
1 file c
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski
---
.../boot/dts/freescale/imx8mq-hummingboard-pulse.dts | 8
Device tree schema expects pin configuration groups to end with 'grp'
suffix. This fixes dtbs_check warnings like:
pinctrl@3033: 'pcal6414-gpio', 'pmicirq', 'usdhc1grp100mhz',
'usdhc1grp200mhz', 'usdhc1grpgpio',
'usdhc2grp100mhz', 'usdhc2grp200mhz', 'usdhc2grpgpio', 'usdhc3grp100mhz',
Driver requires different amount of clocks for different SoCs. Describe
these requirements properly to fix dtbs_check warnings like:
arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dt.yaml:
nand-controller@33002000: clock-names:1: 'gpmi_apb' was expected
Signed-off-by: Krzysztof Kozlowski
Device tree schema expects regulator names to be lowercase. This fixes
dtbs_check warnings like:
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dt.yaml: pmic@4b:
regulators:LDO1:regulator-name:0: 'LDO1' does not match '^ldo[1-6]$'
Signed-off-by: Krzysztof Kozlowski
---
.../boot/dts/freesca
Since the "spi-cs-high" property is not present, the SPI chip select pin
polarity is active low.
Signed-off-by: Krzysztof Kozlowski
---
arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx
The input clock and number of clock provider cells are not required for
the PMIC to operate. They are needed only for the optional bd718x7
clock driver.
Add also clock-output-names as driver takes use of it.
This fixes dtbs_check warnings like:
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.
SD Cardreaders (especially) sometimes lose the state during suspend
and deliver a "media changed" unit attention when really only a
(runtime) suspend/resume cycle has been done.
Add a flag for drivers to use when this is expected. It's handled in the
scsi core error path and allows to use (runtime
Add support for test pattern control supported by the sensor.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/media/i2c/ov772x.c | 25 -
include/media/i2c/ov772x.h | 1 +
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/media/i2c/ov7
Hi All,
This patch series adds support for BT656 mode in the ov772x sensor
and also enables color bar test pattern control.
Cheers,
Prabhakar
Changes for v3:
* Dropped DT binding documentation patch as this is handled by Jacopo.
* Fixed review comments pointed by Jacopo.
[1] https://www.spinics
Add support to read the bus-type and enable BT656 mode if needed.
Also fail probe if unsupported bus_type is detected.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/media/i2c/ov772x.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers
On Mon, Aug 24, 2020 at 3:57 PM Krzysztof Kozlowski wrote:
> True, I'll fix it up, thanks.
>
> Any comments for the Symphony DTS before v4?
It looks good.
One suggestion is to remove pinctrl_pcie0 for now and add it when PCI
support is in place.
On 8/24/20 11:54 AM, Matthew Wilcox wrote:
On Mon, Aug 24, 2020 at 02:47:53PM -0400, Jeff Layton wrote:
Ok, I'll plan to pick it up providing no one has issues with exporting that
symbol.
_GPL, perhaps?
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
t=1598
Hi Chun-Kuan, Enric,
Is there any plan to merge the following commits in this series to the mainline?
drm/bridge: ps8640: Get the EDID from eDP control
drm/bridge_connector: Set default status connected for eDP connectors
I see that rest of the patchset is already merged and available in 5.9
On Fri, Aug 21, 2020 at 8:40 PM Sean Christopherson
wrote:
>
> On Thu, Aug 20, 2020 at 01:08:22PM -0700, Jim Mattson wrote:
> > On Wed, Apr 1, 2020 at 1:13 AM Vitaly Kuznetsov wrote:
> > > ---
> > > arch/x86/kvm/vmx/vmx.c | 12 +++-
> > > 1 file changed, 7 insertions(+), 5 deletions(-)
>
On Mon, Aug 24, 2020 at 03:33:50PM -0300, Fabio Estevam wrote:
> Hi Krzysztof,
>
> On Mon, Aug 24, 2020 at 1:03 PM Krzysztof Kozlowski wrote:
>
> > +&ecspi1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_ecspi1>;
> > + cs-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>,
>
On Mon, 2020-08-24 at 11:46 -0700, Linus Torvalds wrote:
> I think I'd have preferred to get this as a couple of scripts that do
> the obvious 1:1 direct conversion of the simple cases that cover 90%
> of it all, so then the manual fixups separately.
I created a script and sent it directly to you
On Mon, Aug 24, 2020 at 6:46 PM Michael Kelley wrote:
>
> Add ARM64-specific code to set up and handle the interrupts
> generated by Hyper-V for VMbus messages and for stimer expiration.
>
> This code is architecture dependent and is mostly driven by
> architecture independent code in the VMbus dr
commit 59cf47e7df31 dyndbg: export ddebug_exec_queries
left a few configs broken, fix them with ifdef-stubs.
Rename the export to dynamic_debug_exec_queries(). This is a more
canonical function name, instead of exposing the 'ddebug' internal
name prefix. Do this now, before export hits v5.9.0
I
- fix new export name, with a wrapper for more utility.
- parse format="foo bar" like "format" "foo bar"
- pretty-print
Jim Cromie (3):
dyndbg: give %3u width in pr-format, cosmetic only
dyndbg: refine export, rename to dynamic_debug_exec_queries()
dyndbg: fix problem parsing format="foo
24.08.2020 17:07, Sebastian Reichel пишет:
> Hi,
...
>> +static int a500_battery_get_serial_number(struct a500_battery *bat,
>> + union power_supply_propval *val)
>> +{
>> +unsigned int i;
>> +s32 ret = 0;
>> +
>> +if (bat->serial[0])
>> +
Specify the print-width so log entries line up nicely.
no functional changes.
Signed-off-by: Jim Cromie
---
lib/dynamic_debug.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c
index 1d012e597cc3..01b7d0210412 100644
--- a/lib/dynamic
14775b049642 dyndbg: accept query terms like file=bar and module=foo
That commit broke on a tokenization modality where a word could start
with a quote, but couldnt continue with one. So the above would
tokenize as 'format="foo' and 'bar"', and fail hard.
This commit fixes the tokenizer by term
On Mon, Aug 24, 2020 at 02:47:53PM -0400, Jeff Layton wrote:
> Ok, I'll plan to pick it up providing no one has issues with exporting that
> symbol.
_GPL, perhaps?
On Fri, Aug 21, 2020 at 1:28 AM Tetsuo Handa
wrote:
>
> syzbot is reporting that del_timer_sync() is called from
> mwifiex_usb_cleanup_tx_aggr() from mwifiex_unregister_dev() without
> checking timer_setup() from mwifiex_usb_tx_init() was called [1].
>
> Ganapathi Bhat proposed a possibly cleaner
On 2020-08-24 14:44:55, Mimi Zohar wrote:
> Hi Tyler,
>
> On Tue, 2020-08-11 at 14:26 -0500, Tyler Hicks wrote:
> > v2:
> > - Always return an ERR_PTR from ima_alloc_rule_opt_list() (Nayna)
> > - Add Lakshmi's Reviewed-by to both patches
> > - Rebased on commit 3db0d0c276a7 ("integrity: remove
/proc/cpuinfo shows features which the kernel supports. Some of these
flags are derived from CPUID, and others are derived from other sources,
including some that are entirely software-based. Currently, there is
not any documentation in the kernel about how /proc/cpuinfo flags are
generated and wha
On Mon, 2020-08-24 at 10:54 -0700, John Hubbard wrote:
> On 8/24/20 3:53 AM, Jeff Layton wrote:
> > This looks fine to me. Let me know if you need this merged via the ceph
> > tree. Thanks!
> >
> > Acked-by: Jeff Layton
> >
>
> Yes, please! It will get proper testing that way, and it doesn't ha
On Sun, Aug 23, 2020 at 8:42 PM Gustavo A. R. Silva
wrote:
>
> Not sure what the problem was with my pull-request for -rc2. So, I'm giving
> this a second try because I think it is worth it.
Just "a ton of lines changed across subsystems, I feel like I need to check it".
For example, you say tha
Hi Mauro.
> Before posting the big patch series again, let me send the new
> version folded into a single patch.
Review 1/N
Lots of small details I missed last time.
A good thing is that there is an opportunity to delete som more code.
Sam
> diff --git a/drivers/staging/hikey9xx/gpu/Kc
Hi Tyler,
On Tue, 2020-08-11 at 14:26 -0500, Tyler Hicks wrote:
> v2:
> - Always return an ERR_PTR from ima_alloc_rule_opt_list() (Nayna)
> - Add Lakshmi's Reviewed-by to both patches
> - Rebased on commit 3db0d0c276a7 ("integrity: remove redundant
>initialization of variable ret") of next-
From: Jordan Crouse
Add support to create a io-pgtable for use by targets that support
per-instance pagetables. In order to support per-instance pagetables the
GPU SMMU device needs to have the qcom,adreno-smmu compatible string and
split pagetables enabled.
Signed-off-by: Jordan Crouse
Signed-
From: Jordan Crouse
Add support for allocating private address space instances. Targets that
support per-context pagetables should implement their own function to
allocate private address spaces.
The default will return a pointer to the global address space.
Signed-off-by: Jordan Crouse
Signed
From: Jordan Crouse
Add support for using per-instance pagetables if all the dependencies are
available.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
Reviewed-by: Akhil P Oommen
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 63 +++
dri
From: Rob Clark
In $debugfs/gem we already show any vma(s) associated with an object.
Also show process names if the vma's address space is a per-process
address space.
Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 2 +-
drivers/gpu/drm/msm/msm_g
From: Jordan Crouse
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
split pagetables and per-instance pagetables for drm/msm.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 9 +
arch/arm64/boot/dts/qcom/sdm8
From: Rob Clark
For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
pending translations are not terminated on iova fault. Otherwise
a terminated CP read could hang the GPU by returning invalid
command-stream data.
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu
From: Jordan Crouse
Now that we can get the ctx from the submitqueue, the extra arg is
redundant.
Signed-off-by: Jordan Crouse
[split out of previous patch to reduce churny noise]
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +---
drivers/gpu/drm/msm/adren
From: Jordan Crouse
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adre
On 8/24/20 11:36 AM, John Hubbard wrote:
This code was using get_user_pages*(), in a "Case 2" scenario
(DMA/RDMA), using the categorization from [1]. That means that it's
time to convert the get_user_pages*() + put_page() calls to
pin_user_pages*() + unpin_user_pages() calls.
There is some helpf
From: Jordan Crouse
Every Qcom Adreno GPU has an embedded SMMU for its own use. These
devices depend on unique features such as split pagetables,
different stall/halt requirements and other settings. Identify them
with a compatible string so that they can be identified in the
arm-smmu implementat
From: Rob Clark
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
split pagetables and per-instance pagetables for drm/msm.
Signed-off-by: Rob Clark
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/
From: Rob Clark
Currently it doesn't matter, since we free the ctx immediately. But
when we start refcnt'ing the ctx, we don't want old dangling list
entries to hang around.
Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++-
1 file changed
From: Jordan Crouse
Do a bit of prep work to add the upcoming adreno-smmu implementation.
Add an hook to allow the implementation to choose which context banks
to allocate.
Move some of the common structs to arm-smmu.h in anticipation of them
being used by the implementations and update some of
From: Jordan Crouse
Each submitqueue is attached to a context. Add a pointer to the
context to the submitqueue at create time and refcount it so
that it stays around through the life of the queue.
Co-developed-by: Rob Clark
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gp
From: Jordan Crouse
Add a special implementation for the SMMU attached to most Adreno GPU
target triggered from the qcom,adreno-smmu compatible string.
The new Adreno SMMU implementation will enable split pagetables
(TTBR1) for the domain attached to the GPU device (SID 0) and
hard code it conte
On Mon, 24 Aug 2020 20:54:33 +0800 Alex Shi wrote:
> The new version which bases on v5.9-rc2. The first 6 patches was picked into
> linux-mm, and add patch 25-32 that do some further post optimization.
32 patches, version 18. That's quite heroic. I'm unsure whether I
should merge it up at this
From: Rob Clark
This series adds an Adreno SMMU implementation to arm-smmu to allow GPU hardware
pagetable switching.
The Adreno GPU has built in capabilities to switch the TTBR0 pagetable during
runtime to allow each individual instance or application to have its own
pagetable. In order to tak
From: Rob Clark
Sprinkle a few `const`s where helpers don't need write access.
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h
b/drivers/iommu/arm/arm-smmu/arm-sm
From: Jordan Crouse
Construct the io-pgtable config before calling the implementation specific
init_context function and pass it so the implementation specific function
can get a chance to change it before the io-pgtable is created.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
dr
From: Rob Clark
This interface will be used for drm/msm to coordinate with the
qcom_adreno_smmu_impl to enable/disable TTBR0 translation.
Once TTBR0 translation is enabled, the GPU's CP (Command Processor)
will directly switch TTBR0 pgtables (and do the necessary TLB inv)
synchronized to the GPU
From: Rob Clark
In a later patch, the drvdata will not directly be 'struct msm_gpu *',
so add a helper to reduce the churn.
Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 10 --
drivers/gpu/drm/msm/msm_gpu.c | 6 +++--
From: Rob Clark
This will be populated by adreno-smmu, to provide a way for coordinating
enabling/disabling TTBR0 translation.
Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 2 --
drivers/gpu/drm/msm/msm_gpu.c | 2 +-
drivers/
From: Jordan Crouse
Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected
by the io-pgtable configuration.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 21 -
drivers/iommu/arm/arm-smmu/arm-smmu.h | 25
On Mon, Aug 24, 2020 at 6:47 PM Michael Kelley wrote:
> +
> +#define hv_get_simp(val) (val = hv_get_vpreg(HV_REGISTER_SIPP))
> +
> +#define hv_get_siefp(val) (val = hv_get_vpreg(HV_REGISTER_SIFP))
Macros that modify their arguments are generally a bad idea. Since each one
of these only has a few
This code was using get_user_pages*(), in a "Case 2" scenario
(DMA/RDMA), using the categorization from [1]. That means that it's
time to convert the get_user_pages*() + put_page() calls to
pin_user_pages*() + unpin_user_pages() calls.
There is some helpful background in [2]: basically, this is a
Changes in v3:
- included missing preliminary patch to define the SB barrier instruction, see
patch change log for details on how it was back ported into v4.9
Changes in v2:
- added missing hunk in hyp/entry.S per Will's feedback
Will Deacon (2):
arm64: Add support for SB barrier and patch
From: Will Deacon
commit 679db70801da9fda91d26caf13bf5b5ccc74e8e8 upstream
Some CPUs can speculate past an ERET instruction and potentially perform
speculative accesses to memory before processing the exception return.
Since the register state is often controlled by a lower privilege level
at th
Changes in v2:
- included missing preliminary patch to define the SB barrier instruction
Will Deacon (2):
arm64: Add support for SB barrier and patch in over DSB; ISB sequences
arm64: entry: Place an SB sequence following an ERET instruction
arch/arm64/include/asm/assembler.h | 13
From: Will Deacon
commit bd4fb6d270bc423a9a4098108784f7f9254c4e6d upstream
We currently use a DSB; ISB sequence to inhibit speculation in set_fs().
Whilst this works for current CPUs, future CPUs may implement a new SB
barrier instruction which acts as an architected speculation barrier.
On CPU
From: Will Deacon
commit 679db70801da9fda91d26caf13bf5b5ccc74e8e8 upstream
Some CPUs can speculate past an ERET instruction and potentially perform
speculative accesses to memory before processing the exception return.
Since the register state is often controlled by a lower privilege level
at th
From: Will Deacon
commit 679db70801da9fda91d26caf13bf5b5ccc74e8e8 upstream
Some CPUs can speculate past an ERET instruction and potentially perform
speculative accesses to memory before processing the exception return.
Since the register state is often controlled by a lower privilege level
at th
From: Will Deacon
commit bd4fb6d270bc423a9a4098108784f7f9254c4e6d upstream
We currently use a DSB; ISB sequence to inhibit speculation in set_fs().
Whilst this works for current CPUs, future CPUs may implement a new SB
barrier instruction which acts as an architected speculation barrier.
On CPU
From: Will Deacon
commit bd4fb6d270bc423a9a4098108784f7f9254c4e6d upstream
We currently use a DSB; ISB sequence to inhibit speculation in set_fs().
Whilst this works for current CPUs, future CPUs may implement a new SB
barrier instruction which acts as an architected speculation barrier.
On CPU
Changes in v2:
- included missing preliminary patch to define the SB barrier instruction
Will Deacon (2):
arm64: Add support for SB barrier and patch in over DSB; ISB sequences
arm64: entry: Place an SB sequence following an ERET instruction
arch/arm64/include/asm/assembler.h | 13
On 8/24/20 11:28 AM, Jean-Philippe Brucker wrote:
>> +/**
>> + * struct ioasid_set - Meta data about ioasid_set
>> + * @type: Token types and other features
> nit: doesn't follow struct order
>
>> + * @token: Unique to identify an IOASID set
>> + * @xa: XArray to store ioasid_set pr
On Mon, Aug 24, 2020 at 6:48 PM Michael Kelley wrote:
>
> /*
> + * This function is invoked via the ACPI clocksource probe mechanism. We
> + * don't actually use any values from the ACPI GTDT table, but we set up
> + * the Hyper-V synthetic clocksource and do other initialization for
> + * intera
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