[tip: perf/core] perf/x86/intel: Fix Ice Lake event constraint table

The following commit has been merged into the perf/core branch of tip: Commit-ID: 010cb00265f150bf82b23c02ad1fb87ce5c781e1 Gitweb: https://git.kernel.org/tip/010cb00265f150bf82b23c02ad1fb87ce5c781e1 Author:Kan Liang AuthorDate:Mon, 28 Sep 2020 06:47:26 -07:00 Committer:

[tip: perf/core] perf/x86/msr: Add Jasper Lake support

The following commit has been merged into the perf/core branch of tip: Commit-ID: c3bb8a9fa31b99f5b7d2e45cd0a10db91349f4c9 Gitweb: https://git.kernel.org/tip/c3bb8a9fa31b99f5b7d2e45cd0a10db91349f4c9 Author:Kan Liang AuthorDate:Mon, 28 Sep 2020 05:30:42 -07:00 Committer:

[tip: perf/core] perf/x86/intel/uncore: Fix for iio mapping on Skylake Server

The following commit has been merged into the perf/core branch of tip: Commit-ID: f797f05d917ffef94249ee0aec4c14a5b50517b2 Gitweb: https://git.kernel.org/tip/f797f05d917ffef94249ee0aec4c14a5b50517b2 Author:Alexander Antonov AuthorDate:Mon, 28 Sep 2020 13:21:33 +03:00

[tip: perf/core] perf/x86/intel: Add Jasper Lake support

The following commit has been merged into the perf/core branch of tip: Commit-ID: dbfd638889a0396f5fe14ff3cc2263ec1e1cac62 Gitweb: https://git.kernel.org/tip/dbfd638889a0396f5fe14ff3cc2263ec1e1cac62 Author:Kan Liang AuthorDate:Mon, 28 Sep 2020 05:30:41 -07:00 Committer:

[tip: perf/core] perf/x86/intel/uncore: Fix the scale of the IMC free-running events

The following commit has been merged into the perf/core branch of tip: Commit-ID: 8191016a026b8dfbb14dea64efc8e723ee99fe65 Gitweb: https://git.kernel.org/tip/8191016a026b8dfbb14dea64efc8e723ee99fe65 Author:Kan Liang AuthorDate:Mon, 28 Sep 2020 06:32:40 -07:00 Committer:

[PATCH v14 06/15] mtd: spi-nor: core: use dummy cycle and address width info from SFDP

The xSPI Profile 1.0 table specifies how many dummy cycles and address bytes are needed for the Read Status Register command in octal DTR mode. Use that information to send the correct Read SR command. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 10 ++ 1 file changed,

[PATCH v14 02/15] mtd: spi-nor: add spi_nor_controller_ops_{read_reg,write_reg,erase}()

They are thin wrappers around nor->controller_ops->{read_reg,write_reg,erase}(). In a future commit DTR support will be added. These ops can not be supported by the controller_ops hooks and these helpers will make it easier to reject those calls. Signed-off-by: Pratyush Yadav ---

[PATCH v14 04/15] mtd: spi-nor: sfdp: get command opcode extension type from BFPT

Some devices in DTR mode expect an extra command byte called the extension. The extension can either be same as the opcode, bitwise inverse of the opcode, or another additional byte forming a 16-byte opcode. Get the extension type from the BFPT. For now, only flashes with "repeat" and "inverse"

[PATCH v14 07/15] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode

Some controllers, like the cadence qspi controller, have trouble reading only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in DTR mode, and then discard the second byte. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 15 +-- 1 file changed, 13

[PATCH v14 05/15] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table

This table is indication that the flash is xSPI compliant and hence supports octal DTR mode. Extract information like the fast read opcode, dummy cycles, the number of dummy cycles needed for a Read Status Register command, and the number of address bytes needed for a Read Status Register command.

[PATCH v14 08/15] mtd: spi-nor: core: enable octal DTR mode when possible

Allow flashes to specify a hook to enable octal DTR mode. Use this hook whenever possible to get optimal transfer speeds. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 35 +++ drivers/mtd/spi-nor/core.h | 2 ++ 2 files changed, 37 insertions(+)

[PATCH v14 03/15] mtd: spi-nor: add support for DTR protocol

Double Transfer Rate (DTR) is SPI protocol in which data is transferred on each clock edge as opposed to on each clock cycle. Make framework-level changes to allow supporting flashes in DTR mode. Right now, mixed DTR modes are not supported. So, for example a mode like 4S-4D-4D will not work. All

[PATCH v14 09/15] mtd: spi-nor: Introduce SNOR_F_IO_MODE_EN_VOLATILE

From: Tudor Ambarus We don't want to enter a stateful mode, where a X-X-X I/O mode is entered by setting a non-volatile bit, because in case of a reset or a crash, once in the non-volatile mode, we may not be able to recover in bootloaders and we may break the SPI NOR boot. Forbid by default

[PATCH v14 01/15] mtd: spi-nor: core: use EOPNOTSUPP instead of ENOTSUPP

ENOTSUPP is not a SUSV4 error code. Using EOPNOTSUPP is preferred in its stead. Reviewed-by: Tudor Ambarus Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c

[PATCH v14 10/15] mtd: spi-nor: Parse SFDP SCCR Map

From: Tudor Ambarus Parse just the 22nd dword and look for the 'DTR Octal Mode Enable Volatile bit'. SPI_NOR_IO_MODE_EN_VOLATILE should be set just for the flashes that don't define the optional SFDP SCCR Map. For the others, let the SFDP do its job and fill the SNOR_F_IO_MODE_EN_VOLATILE flag.

[PATCH v14 00/15] mtd: spi-nor: add xSPI Octal DTR support

Hi, This series adds support for Octal DTR flashes in the SPI NOR framework, and then adds hooks for the Cypress Semper and Micron Xcella flashes to allow running them in Octal DTR mode. This series assumes that the flash is handed to the kernel in Legacy SPI mode. Tested on Micron MT35X and

[GIT PULL] clk fixes for v5.9-rc7

The following changes since commit d2249bf25c565b6e310453962fef63f8d38677a6: clk: qcom: lpass: Correct goto target in lpass_core_sc7180_probe() (2020-09-10 13:42:35 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git

[PATCH v2 09/21] spi: dw: Refactor IRQ-based SPI transfer procedure

Current IRQ-based SPI transfer execution procedure doesn't work well at the final stage of the execution. If all the Tx data is sent out (written to the Tx FIFO) but there is some data left to receive, the Tx FIFO Empty IRQ will constantly happen until all of the requested inbound data is

[PATCH v2 13/21] spi: dw: De-assert chip-select on reset

SPI memory operations implementation will require to have the CS register cleared before executing the operation in order not to have the transmission automatically started prior the Tx FIFO is pre-initialized. Let's clear the register then on explicit controller reset to fulfil the requirements

[PATCH v2 05/21] spi: dw: Simplify the SPI bus speed config procedure

The code currently responsible for the SPI communication speed setting up is a bit messy. Most likely for some historical reason the bus frequency is saved in the peripheral chip private data. It's pointless now since the custom communication speed is a SPI-transfer-specific thing and only if

[PATCH v2 16/21] spi: dw: Add generic DW SSI status-check method

The DW SSI errors handling method can be generically implemented for all types of the transfers: IRQ, DMA and poll-based ones. It will be a function which checks the overflow/underflow error flags and resets the controller if any of them is set. In the framework of this commit we make use of the

[PATCH v2 03/21] spi: dw: Detach SPI device specific CR0 config method

Indeed there is no point in detecting the SPI peripheral device parameters and initializing the CR0 register fields each time an SPI transfer is executed. Instead let's define a dedicated CR0 chip-data member, which will be initialized in accordance with the SPI device settings at the moment of

[PATCH] proc: remove a pointless assignment

The variable 'env_start' has only been used for the if condition before this assignment and is never read after this. So, remove the assignement. Signed-off-by: Sudip Mukherjee --- fs/proc/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/proc/base.c b/fs/proc/base.c

[PATCH v2 10/21] spi: dw: Perform IRQ setup in a dedicated function

In order to make the transfer_one() callback method more readable and for unification with the DMA-based transfer, let's detach the IRQ setup procedure into a dedicated function. While at it rename the IRQ-based transfer handler function to be dw_spi-prefixe and looking more like the DMA-related

[PATCH v2 19/21] spi: dw: Add poll-based SPI transfers support

A functionality of the poll-based transfer has been removed by commit 1ceb09717e98 ("spi: dw: remove cs_control and poll_mode members from chip_data") with a justification that "there is no user of one anymore". It turns out one of our DW APB SSI core is synthesized with no IRQ line attached and

[PATCH v2 18/21] spi: dw: Introduce max mem-ops SPI bus frequency setting

In some circumstances the current implementation of the SPI memory operations may occasionally fail even though they are executed in the atomic context. This may happen if the system bus is relatively slow in comparison to the SPI bus frequency, or there is a concurrent access to it, which makes

Re: [PATCH v2] srcu: avoid escaped section names

On Wed, 2020-09-30 at 18:41 +0200, Sedat Dilek wrote: > On Tue, Sep 29, 2020 at 9:25 PM 'Nick Desaulniers' via Clang Built > Linux wrote: > > The stringification operator, `#`, in the preprocessor escapes strings. > > For example, `# "foo"` becomes `"\"foo\""`. GCC and Clang differ in how > >

[PATCH v2 15/21] spi: dw: Move num-of retries parameter to the header file

The parameter will be needed for another wait-done method being added in the framework of the SPI memory operation modification in a further commit. Signed-off-by: Serge Semin --- drivers/spi/spi-dw-dma.c | 5 ++--- drivers/spi/spi-dw.h | 2 ++ 2 files changed, 4 insertions(+), 3

[PATCH v2 14/21] spi: dw: Explicitly de-assert CS on SPI transfer completion

By design of the currently available native set_cs callback, the CS de-assertion will be done only if it's required by the corresponding controller capability. But in order to pre-fill the Tx FIFO buffer with data during the SPI memory ops execution the SER register needs to be left cleared before

[PATCH v2 21/21] spi: dw: Add Baikal-T1 SPI Controller glue driver

Baikal-T1 is equipped with three DW APB SSI-based MMIO SPI controllers. Two of them are pretty much normal: with IRQ, DMA, FIFOs of 64 words depth, 4x CSs, but the third one as being a part of the Baikal-T1 System Boot Controller has got a very limited resources: no IRQ, no DMA, only a single

[PATCH v2 01/21] spi: dw: Use an explicit set_cs assignment

Simplify the dw_spi_add_host() method a bit by replacing the currently implemented default set_cs callback setting up and later having it overwritten by a custom function with direct if-else-based callback assignment. Signed-off-by: Serge Semin --- Changelog v2: - Replace the ternary operator

[PATCH v2 11/21] spi: dw: Unmask IRQs after enabling the chip

It's theoretically erroneous to enable IRQ before the chip is turned on. If IRQ handler gets executed before the chip is enabled, then any data written to the Tx FIFO will be just ignored. I say "theoretically" because we haven't noticed any problem with that, but let's fix it anyway just in

[PATCH v2 02/21] spi: dw: Add DWC SSI capability

Currently DWC SSI core is supported by means of setting up the core-specific update_cr0() callback. It isn't suitable for multiple reasons. First of all having exported several methods doing the same thing but for different chips makes the code harder to maintain. Secondly the spi-dw-core driver

[PATCH v2 06/21] spi: dw: Update Rx sample delay in the config function

Rx sample delay can be SPI device specific, and should be synchronously initialized with the rest of the communication and peripheral device related controller setups. So let's move the Rx-sample delay setup into the DW APB SSI configuration update method. Signed-off-by: Serge Semin ---

[PATCH v2 12/21] spi: dw: Discard chip enabling on DMA setup error

It's pointless to enable the chip back if the DMA setup procedure fails, since we'll disable it on the next transfer anyway. For the same reason We don't do that in case of a failure detected in any other methods called from the transfer_one() method. While at it consider any non-zero value

[PATCH v2 00/21] spi: dw: Add full Baikal-T1 SPI Controllers support

Originally I intended to merge a dedicated Baikal-T1 System Boot SPI Controller driver into the kernel and leave the DW APB SSI driver untouched. But after a long discussion (see the link at the bottom of the letter) Mark and Andy persuaded me to integrate what we developed there into the DW APB

[PATCH v2 17/21] spi: dw: Add memory operations support

Aside from the synchronous Tx-Rx mode, which has been utilized to create the normal SPI transfers in the framework of the DW SSI driver, DW SPI controller supports Tx-only and EEPROM-read modes. The former one just enables the controller to transmit all the data from the Tx FIFO ignoring anything

[PATCH v2 20/21] dt-bindings: spi: dw: Add Baikal-T1 SPI Controllers

These controllers are based on the DW APB SSI IP-core and embedded into the SoC, so two of them are equipped with IRQ, DMA, 64 words FIFOs and 4 native CS, while another one as being utilized by the Baikal-T1 System Boot Controller has got a very limited resources: no IRQ, no DMA, only a single

[PATCH v2 08/21] spi: dw: Refactor data IO procedure

The Tx and Rx data write/read procedure can be significantly simplified by using Tx/Rx transfer lengths instead of the end pointers. By having the Tx/Rx data leftover lengths (in the number of transfer words) we can get rid of all subtraction and division operations utilized here and there in the

[PATCH v2 04/21] spi: dw: Update SPI bus speed in a config function

The SPI bus speed update functionality will be useful in another parts of the driver too (like to implement the SPI memory operations and from the DW SPI glue layers). Let's move it to the update_cr0() method then and since the later is now updating not only the CTRLR0 register alter its prototype

[PATCH v2 07/21] spi: dw: Add DW SPI controller config structure

DW APB SSI controller can be used by the two SPI core interfaces: traditional SPI transfers and SPI memory operations. The controller needs to be accordingly configured at runtime when the corresponding operations are executed. In order to do that for the both interfaces from a single function we

[PATCH blktests v2 09/11] nvme/036: Add test for testing reset command on nvme-passthru

Similar to test 022 but for passthru controllers. Signed-off-by: Logan Gunthorpe --- tests/nvme/036 | 37 + tests/nvme/036.out | 3 +++ 2 files changed, 40 insertions(+) create mode 100755 tests/nvme/036 create mode 100644 tests/nvme/036.out diff

[PATCH blktests v2 02/11] common/xfs: Create common helper to check for XFS support

Two nvme tests create and mount XFS filesystems and check for mkfs.xfs. They should also check for XFS support in the kernel so create a common helper for this. Signed-off-by: Logan Gunthorpe --- common/rc | 8 common/xfs | 11 +++ tests/nvme/012 | 6 --

[PATCH blktests v2 08/11] nvme/035: Add test to verify passthru controller with a filesystem

This is a similar test as nvme/012 and nvme/013, except with a passthru controller. Signed-off-by: Logan Gunthorpe --- tests/nvme/035 | 37 + tests/nvme/035.out | 3 +++ 2 files changed, 40 insertions(+) create mode 100755 tests/nvme/035 create mode

[PATCH blktests v2 01/11] common/fio: Remove state file in common helper

Instead of each individual test removing this file, just do it in the common helper. Signed-off-by: Logan Gunthorpe Reviewed-by: Chaitanya Kulkarni --- common/fio | 1 + tests/nvme/010 | 1 - tests/nvme/011 | 1 - tests/nvme/012 | 1 - tests/nvme/013 | 1 - 5 files changed, 1 insertion(+),

[PATCH blktests v2 00/11] NVMe Target Passthru Block Tests

Hi, This series adds blktests for the nvmet passthru feature that was merged for 5.9. It's been reconciled with Sagi's blktest series that Omar recently merged. This series is based off of the current blktests master and a git repo is available for this here:

[PATCH blktests v2 05/11] nvme: Add common helpers for passthru tests

Add some simple helpers to setup a passthru target that passes through to a nvme test device. Signed-off-by: Logan Gunthorpe --- tests/nvme/rc | 76 +++ 1 file changed, 76 insertions(+) diff --git a/tests/nvme/rc b/tests/nvme/rc index

[PATCH blktests v2 10/11] nvme/037: Add test which loops passthru connect and disconnect

Similar to test nvme/031 except for passthru controllers. Note: it's normal to get I/O errors in this test as when the controller disconnects it races with the partition table read. Signed-off-by: Logan Gunthorpe --- tests/nvme/037 | 35 +++

[PATCH blktests v2 06/11] nvme/033: Simple test to create and connect to a passthru target

This tests creates and connects to a passthru controller backed by a test NVMe namespace. It then verifies that some common fields in id-ctrl and id-ns are the same in the target and the orginial device. Signed-off-by: Logan Gunthorpe --- tests/nvme/033 | 67

[PATCH blktests v2 07/11] nvme/034: Add test for passthru data verification

Similar to test nvme/010 and nvme/011 but for a passthru controller Signed-off-by: Logan Gunthorpe --- tests/nvme/034 | 35 +++ tests/nvme/034.out | 3 +++ 2 files changed, 38 insertions(+) create mode 100755 tests/nvme/034 create mode 100644

[PATCH blktests v2 11/11] nvme/038: Test removal of un-enabled subsystem and ports

Test that we can remove a subsystem that has not been enabled by passthru or any ns. Do the same for ports while we are at it. This was an issue in the original passthru patches and is not commonly tested. So this test will ensure we don't regress this. Signed-off-by: Logan Gunthorpe ---

[PATCH blktests v2 04/11] nvme: Search for specific subsysnqn in _find_nvme_loop_dev

This ensures we find the correct nvme loop device if others exist on a given system (which is generally not expected on test systems). Additionally, this will be required in the upcomming test nvme/037 which will have controllers racing with ones being destroyed. Signed-off-by: Logan Gunthorpe

[PATCH blktests v2 03/11] common/xfs: Create common helper to verify block device with xfs

Make a common helper from the code in tests nvme/012 and nvme/013 to run an fio verify on a XFS file system backed by the specified block device. While we are at it, all the output is redirected to $FULL instead of /dev/null. Signed-off-by: Logan Gunthorpe --- common/xfs | 22

Re: [PATCH V9 4/4] fuse: Handle asynchronous read and write in passthrough

On Thu, Sep 24, 2020 at 3:13 PM Alessio Balsini wrote: > > Extend the passthrough feature by handling asynchronous IO both for read > and write operations. > > When an AIO request is received, if the request targets a FUSE file with > the passthrough functionality enabled, a new identical AIO

Re: [PATCH 11/22] kvm: mmu: Factor out allocating a new tdp_mmu_page

On Fri, Sep 25, 2020 at 5:22 PM Paolo Bonzini wrote: > > On 25/09/20 23:22, Ben Gardon wrote: > > Move the code to allocate a struct kvm_mmu_page for the TDP MMU out of the > > root allocation code to support allocating a struct kvm_mmu_page for every > > page of page table memory used by the TDP

Re: [PATCH v3 05/18] dmaengine: idxd: add IMS support in base driver

On Wed, Sep 30, 2020 at 08:47:00PM +0200, Thomas Gleixner wrote: > > + pci_read_config_dword(pdev, SIOVCAP(dvsec), ); > > + if ((val32 & 0x1) && idxd->hw.gen_cap.max_ims_mult) { > > + idxd->ims_size = idxd->hw.gen_cap.max_ims_mult * 256ULL; > > + dev_dbg(dev, "IMS size:

Re: [PATCH V9 3/4] fuse: Introduce synchronous read and write for passthrough

On Thu, Sep 24, 2020 at 3:13 PM Alessio Balsini wrote: > > All the read and write operations performed on fuse_files which have the > passthrough feature enabled are forwarded to the associated lower file > system file via VFS. > > Sending the request directly to the lower file system avoids the

Re: [PATCH] ARM: dts: document pinctrl-single,pins when #pinctrl-cells = 2

On Wed, Sep 30, 2020 at 2:47 AM Tony Lindgren wrote: > > * Trent Piepho [200930 09:34]: > > > > Where do these flags go? In pinctrl-single,pins? Like: > > > > pinctrl-single,pins = ; > > > > But PIN_INPUT_PULLUP is a generic flag? Which is translated into the > > proper value by?? > > Yes

[PATCH 2/2] pcmcia: at91_cf: remove platform data support

Board file support has been removed for at91rm9200 back in 2014, make the CF driver DT only. Signed-off-by: Alexandre Belloni --- drivers/pcmcia/Kconfig | 1 + drivers/pcmcia/at91_cf.c | 38 -- 2 files changed, 9 insertions(+), 30 deletions(-) diff --git

[PATCH 1/2] pcmcia: at91_cf: move definitions locally

struct at91_cf_data is only used in the driver since all the platforms moved to device tree, move its definition locally. Signed-off-by: Alexandre Belloni --- drivers/pcmcia/at91_cf.c| 11 +++ include/linux/platform_data/atmel.h | 12 2 files changed, 11

Re: [patch V2 24/46] PCI: vmd: Mark VMD irqdomain with DOMAIN_BUS_VMD_MSI

On Wed, Sep 30, 2020 at 01:08:27PM +, Derrick, Jonathan wrote: > +Megha > > On Wed, 2020-09-30 at 09:57 -0300, Jason Gunthorpe wrote: > > On Wed, Sep 30, 2020 at 12:45:30PM +, Derrick, Jonathan wrote: > > > Hi Jason > > > > > > On Mon, 2020-08-31 at 11:39 -0300, Jason Gunthorpe wrote: >

Re: [PATCH v3 05/18] dmaengine: idxd: add IMS support in base driver

On Tue, Sep 15 2020 at 16:28, Dave Jiang wrote: > struct idxd_device { > @@ -170,6 +171,7 @@ struct idxd_device { > > int num_groups; > > + u32 ims_offset; > u32 msix_perm_offset; > u32 wqcfg_offset; > u32 grpcfg_offset; > @@ -177,6 +179,7 @@ struct idxd_device { >

Re: [PATCH V9 2/4] fuse: Trace daemon creds

On Thu, Sep 24, 2020 at 3:13 PM Alessio Balsini wrote: > > Add a reference to the FUSE daemon credentials, so that they can be used to > temporarily raise the user credentials when accessing lower file system > files in passthrough. Hmm, I think it would be better to store the creds of the

[PATCH] tracing: remove a pointless assignment

The variable 'len' has been assigned a value but is not used after that. So, remove the assignement. Signed-off-by: Sudip Mukherjee --- kernel/trace/trace.c | 1 - 1 file changed, 1 deletion(-) diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index d3c75aab44ad..e13cb3baeff0 100644 ---

Re: [PATCH 03/22] kvm: mmu: Init / Uninit the TDP MMU

On Wed, Sep 30, 2020 at 10:39 AM Paolo Bonzini wrote: > > On 30/09/20 18:57, Sean Christopherson wrote: > >> + > >> +static bool __read_mostly tdp_mmu_enabled = true; > >> +module_param_named(tdp_mmu, tdp_mmu_enabled, bool, 0644); > > This param should not exist until the TDP MMU is fully

[PATCH v2 0/3] tracing: Add dynamic strings for synthetic events

Hi, This is v2 of the dynamic string support for synthetic events. v1 was missing some very important code in the in-kernel API functions that should have reserved room for dynamic strings. This adds it along also some additional test code in the synth_event_gen_test module that tests the

[PATCH v2 2/3] tracing: Fix parse_synth_field() error handling

synth_field_size() returns either a positive size or an error (zero or a negative value). However, the existing code assumes the only error value is 0. It doesn't handle negative error codes, as it assigns directly to field->size (a size_t; unsigned), thereby interpreting the error code as a valid

[PATCH v2 1/3] tracing: Change STR_VAR_MAX_LEN

32 is too small for this value, and anyway it makes more sense to use MAX_FILTER_STR_VAL, as this is also the value used for variable-length __strings. Signed-off-by: Tom Zanussi --- kernel/trace/trace_synth.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [PATCH 2/3] tracing: Fix parse_synth_field() error handling

Hi Axel, On Tue, 2020-09-29 at 14:56 -0700, Axel Rasmussen wrote: > On Tue, Sep 29, 2020 at 1:33 PM Tom Zanussi > wrote: > > > > synth_field_size() returns either the size or an error. However, > > the > > code assigns the return val to ssize_t which is unsigned, and then > > tests whether

[PATCH v2 3/3] tracing: Add support for dynamic strings to synthetic events

Currently, sythetic events only support static string fields such as: # echo 'test_latency u64 lat; char somename[32]' > /sys/kernel/debug/tracing/synthetic_events Which is fine, but wastes a lot of space in the event. It also prevents the most commonly-defined strings in the existing trace

[PATCH v3 2/4] arm: decompressor: define a new zImage tag

Add DCSZ tag which holds dynamic memory (stack, bss, malloc pool) requirements of the decompressor code. Signed-off-by: Łukasz Stelmach --- arch/arm/boot/compressed/vmlinux.lds.S | 9 - arch/arm/include/asm/image.h | 3 +++ 2 files changed, 11 insertions(+), 1 deletion(-)

[PATCH v3 1/4] arm: add image header definitions

This structure will be used later by kexec_file loader. Signed-off-by: Łukasz Stelmach --- arch/arm/boot/compressed/head.S| 3 +- arch/arm/boot/compressed/vmlinux.lds.S | 13 ++- arch/arm/include/asm/image.h | 50 ++ 3 files changed, 55

[PATCH v3 3/4] arm: Add kexec_image_info

Add kexec_image_info to print detailed information about a kexec image. Signed-off-by: Łukasz Stelmach --- arch/arm/kernel/machine_kexec.c | 28 1 file changed, 28 insertions(+) diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c index

[PATCH v3 4/4] arm: kexec_file: load zImage or uImage, initrd and dtb

This is kexec_file_load implementation for ARM. It loads zImage and initrd from file descripters and resuses DTB. Most code is derived from arm64 kexec_file_load implementation and from kexec-tools. Cc: AKASHI Takahiro Signed-off-by: Łukasz Stelmach --- arch/arm/Kconfig |

[PATCH v3 0/4] kexec_file_load() for arm

The following series of patches provides implementation of the kexec_file_load() system call form the arm architecture. zImage and uImage (legacy format) files are supported. Like on arm64,

Re: [PATCH 03/22] kvm: mmu: Init / Uninit the TDP MMU

On Tue, Sep 29, 2020 at 10:35 PM Sean Christopherson wrote: > > Nit on all the shortlogs, can you use "KVM: x86/mmu" instead of "kvm: mmu"? Will do. > > On Fri, Sep 25, 2020 at 02:22:43PM -0700, Ben Gardon wrote: > > diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c > > new

Re: remove alloc_vm_area v2

On Wed, Sep 30, 2020 at 4:48 PM Christoph Hellwig wrote: > > On Tue, Sep 29, 2020 at 03:43:30PM +0300, Joonas Lahtinen wrote: > > Hmm, those are both committed after our last -next pull request, so they > > would normally only target next merge window. drm-next closes the merge > > window around

Re: [PATCH v3 04/18] dmaengine: idxd: add interrupt handle request support

On Tue, Sep 15 2020 at 16:28, Dave Jiang wrote: > > +#define INT_HANDLE_IMS_TABLE 0x1 > +int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, > +int *handle, enum idxd_interrupt_type > irq_type) New lines exist for a reason and this glued

Re: [PATCH -next for tip:x86/pti] x86/tlb: drop unneeded local vars in enable_l1d_flush_for_task()

On Wed, Sep 30, 2020 at 08:00:59PM +0200, Thomas Gleixner wrote: > On Wed, Sep 30 2020 at 19:03, Peter Zijlstra wrote: > > On Wed, Sep 30, 2020 at 05:40:08PM +0200, Thomas Gleixner wrote: > > Also, that preempt_disable() in there doesn't actually do anything. > > Worse, preempt_disable();

Re: [PATCH] compiler.h: avoid escaped section names

On Wed, 2020-09-30 at 08:40 -0700, Joe Perches wrote: > On Tue, 2020-09-29 at 13:25 -0700, Nick Desaulniers wrote: > > And I don't remember what ever happened to Joe's script for treewide > > conversion of __section. > > Nor do I but here (attached) is the script. > > My recollection is there

Re: [PATCH v3 02/18] iommu/vt-d: Add DEV-MSI support

On Tue, Sep 15 2020 at 16:27, Dave Jiang wrote: > @@ -1303,9 +1303,10 @@ static void intel_irq_remapping_prepare_irte(struct > intel_ir_data *data, > case X86_IRQ_ALLOC_TYPE_HPET: > case X86_IRQ_ALLOC_TYPE_PCI_MSI: > case X86_IRQ_ALLOC_TYPE_PCI_MSIX: > + case

[PATCH] kunit: tool: fix display of make errors

CalledProcessError stores the output of the failed process as `bytes`, not a `str`. So when we log it on build error, the make output is all crammed into one line with "\n" instead of actually printing new lines. After this change, we get readable output with new lines, e.g. > CC

Re: [PATCH] RDMA/rtrs: remove unused field of rtrs_iu

On Wed, Sep 30, 2020 at 03:14:07PM +0200, Gioh Kim wrote: > From: Gioh Kim > > list field is not used anywhere > > Signed-off-by: Gioh Kim > Acked-by: Jack Wang > --- > drivers/infiniband/ulp/rtrs/rtrs-pri.h | 1 - > 1 file changed, 1 deletion(-) Applied to for-next, thanks Jason

Re: [PATCH v3 01/18] irqchip: Add IMS (Interrupt Message Storage) driver

On Tue, Sep 15 2020 at 16:27, Dave Jiang wrote: > From: Thomas Gleixner > +config IMS_MSI_ARRAY > + bool "IMS Interrupt Message Storm MSI controller for device memory > storage arrays" Hehe, you missed a Message Storm :) > + depends on PCI > + select IMS_MSI > + select

[PATCH v3] PCI: cadence: Retrain Link to work around Gen2 training defect.

Cadence controller will not initiate autonomous speed change if strapped as Gen2. The Retrain Link bit is set as quirk to enable this speed change. Signed-off-by: Nadeem Athani --- Changes in v3: - To set retrain link bit,checking device capability & link status. - 32bit read in place of 8bit. -

Re: [PATCH v2] PCI: keystone: Enable compile-testing on !ARM

On Sun, 06 Sep 2020 20:51:27 +0100, Alex Dewar wrote: > Currently the Keystone driver can only be compile-tested on ARM, but > this restriction seems unnecessary. Get rid of it to increase test > coverage. > > Build-tested with allyesconfig on x86, ppc, mips and riscv. > > Signed-off-by: Alex

Re: [v5] mm: khugepaged: recalculate min_free_kbytes after memory hotplug as expected by khugepaged

On 9/29/20 9:49 AM, Vijay Balakrishna wrote: > When memory is hotplug added or removed the min_free_kbytes should be > recalculated based on what is expected by khugepaged. Currently > after hotplug, min_free_kbytes will be set to a lower default and higher > default set when THP enabled is lost.

Re: [PATCH 21/22] kvm: mmu: Support MMIO in the TDP MMU

On Fri, Sep 25, 2020 at 02:23:01PM -0700, Ben Gardon wrote: > In order to support MMIO, KVM must be able to walk the TDP paging Probably worth clarifying that this is for emulated MMIO, as opposed to mapping MMIO host addresses. > structures to find mappings for a given GFN. Support this walk

Re: [net-next PATCH v1 3/7] net: phy: Introduce fwnode_get_phy_id()

On Wed, Sep 30, 2020 at 07:07:25PM +0100, Russell King - ARM Linux admin wrote: > On Wed, Sep 30, 2020 at 06:34:40PM +0200, Andrew Lunn wrote: > > > @@ -2866,7 +2888,15 @@ EXPORT_SYMBOL_GPL(device_phy_find_device); > > > */ > > > struct fwnode_handle *fwnode_get_phy_node(struct fwnode_handle

Re: [PATCH 2/2] PCI: aardvark: Fix initialization with old Marvell's Arm Trusted Firmware

On Wed, 02 Sep 2020 16:43:44 +0200, Pali Rohár wrote: > Old ATF automatically power on pcie phy and does not provide SMC call for > phy power on functionality which leads to aardvark initialization failure: > > [0.330134] mvebu-a3700-comphy d0018300.phy: unsupported SMC call, try > updating

Re: [PATCH 1/2] phy: marvell: comphy: Convert internal SMCC firmware return codes to errno

On Wed, 02 Sep 2020 16:43:43 +0200, Pali Rohár wrote: > Driver ->power_on and ->power_off callbacks leaks internal SMCC firmware > return codes to phy caller. This patch converts SMCC error codes to > standard linux errno codes. Include file linux/arm-smccc.h already provides > defines for SMCC

Re: [PATCH 20/22] kvm: mmu: NX largepage recovery for TDP MMU

On Fri, Sep 25, 2020 at 02:23:00PM -0700, Ben Gardon wrote: > +/* > + * Clear non-leaf SPTEs and free the page tables they point to, if those > SPTEs > + * exist in order to allow execute access on a region that would otherwise be > + * mapped as a large page. > + */ > +void

Re: [PATCH V2 6/7] PCI: qcom: Add ipq8074 PCIe controller support

On Wed, Jul 29, 2020 at 09:00:06PM +0530, Sivaprakash Murugesan wrote: > Add support for PCIe Gen3 port found in ipq8074 devices. > > Signed-off-by: Sivaprakash Murugesan > --- > drivers/pci/controller/dwc/pcie-qcom.c | 177 > - > 1 file changed, 176

Re: [PATCH] KVM: use struct_size() and flex_array_size() helpers in kvm_io_bus_unregister_dev()

Hi Sasha, On 9/21/20 07:54, Sasha Levin wrote: > > NOTE: The patch will not be queued to stable trees until it is upstream. > > How should we proceed with this patch? > This patch should not go to -stable. The author has resent it without the _stable_ stag. Thanks -- Gustavo

mb2q experience and couple issues

Hi Thomas, For the last couple years we've been using mb2q tool to normalize patches and it worked wonderfully. Recently we've hit few bugs: curl -s https://patchwork.kernel.org/patch/11807443/mbox/ > /tmp/mbox.i; ~/bin/mb2q --mboxout mbox.o /tmp/mbox.i Drop Message w/o Message-ID: No subject No

Re: [WARNING] kernel/rcu/tree.c:1058 rcu_irq_enter+0x15/0x20

On Thu, Sep 17, 2020 at 01:16:46PM -0400, Steven Rostedt wrote: > Hi Peter, > > I ran my tests on a series of patches on top of 5.9-rc4, and hit the > following splat: > > [ cut here ] > WARNING: CPU: 0 PID: 2557 at kernel/rcu/tree.c:1058 rcu_irq_enter+0x15/0x20 > RIP:

Re: [patch V2 00/46] x86, PCI, XEN, genirq ...: Prepare for device MSI

Megha, On Wed, Sep 30 2020 at 10:25, Megha Dey wrote: > On 9/30/2020 8:20 AM, Thomas Gleixner wrote: Your IMS patches? Why do you need something special again? > > By IMS patches, I meant your IMS driver patch that was updated (as it > was untested, it had some compile errors and we removed

Re: general protection fault in tcf_generic_walker

On Wed, Sep 30, 2020 at 10:42 AM syzbot wrote: > > syzbot has found a reproducer for the following issue on: > > HEAD commit:2b3e981a Merge branch 'mptcp-Fix-for-32-bit-DATA_FIN' > git tree: net > console output: https://syzkaller.appspot.com/x/log.txt?x=1653724790 > kernel config:

Re: WARNING: at kernel/workqueue.c:1473 __queue_work+0x3b8/0x3d0

On Fri, Sep 25, 2020 at 08:12:03PM +0200, Corentin Labbe wrote: > On Tue, Mar 03, 2020 at 04:31:11PM -0500, Daniel Jordan wrote: > > On Tue, Mar 03, 2020 at 08:48:19AM +0100, Corentin Labbe wrote: > > > The patch fix the issue. Thanks! > > > > Thanks for trying it! > > > > > So you could add: >

Re: [PATCH 17/22] kvm: mmu: Support dirty logging for the TDP MMU

On 30/09/20 20:04, Sean Christopherson wrote: >> +for_each_tdp_mmu_root(kvm, root) { >> +root_as_id = kvm_mmu_page_as_id(root); >> +if (root_as_id != slot->as_id) >> +continue; > This pattern pops up quite a few times, probably worth adding > >

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