On 10/13/20 10:44 PM, Ethan Zhao wrote:
This patch only reverts the commit bdb5ac85777d ?
or you'd better separate the revert and code you added.
We cannot revert the commit as it is. pcie_do_recovery()
function and Documentation/* folder changed a lot since
fatal and non-fatal error
When an I2C slave works, sometimes both IC_INTR_RX_FULL and
IC_INTR_STOP_DET are rising during an IRQ handle, especially when system
is busy or too late to handle interrupts.
If IC_INTR_RX_FULL is rising and the system doesn't handle immediately,
IC_INTR_STOP_DET may be rising and the system has
powerpc allnoconfig
x86_64 randconfig-a004-20201013
x86_64 randconfig-a002-20201013
x86_64 randconfig-a006-20201013
x86_64 randconfig-a001-20201013
x86_64 randconfig-a003-20201013
x86_64
> -Original Message-
> From: Joel Stanley
> Sent: Wednesday, October 14, 2020 1:28 PM
> To: Stephen Boyd
> Cc: Andrew Jeffery ; Michael Turquette
> ; Ryan Chen ;
> BMC-SW ; Linux ARM
> ; linux-aspeed
> ; linux-...@vger.kernel.org; Linux Kernel
> Mailing List
> Subject: Re: [PATCH 1/1]
Linus,
Please git pull the following tag:
git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git
for-linus-5.10b-rc1-tag
xen: branch for v5.10-rc1
It contains:
- 2 small cleanup patches
- A fix for avoiding error messages when initializing MCA banks in a
Xen dom0
- A small series for
On Tue, Oct 13, 2020 at 08:21:13AM -0700, Randy Dunlap wrote:
> On 10/13/20 8:12 AM, Mike Rapoport wrote:
> > On Tue, Oct 13, 2020 at 07:43:59AM -0700, Randy Dunlap wrote:
> >> On 10/13/20 1:09 AM, Mike Rapoport wrote:
> >>> On Mon, Oct 12, 2020 at 05:53:01PM +0800, Muchun Song wrote:
> On
gcc 10 optimizes the scheduler code differently than its predecessors.
When DEBUG_SECTION_MISMATCH config is enabled, Makefile forces gcc not
to inline some functions (-fno-inline-functions-called-once). Before gcc
10, "no-inlined" __schedule starts with the usual prologue (push %bp; mov
%sp,%bp).
On 14-10-2020 07:07, Randy Dunlap wrote:
> On 10/13/20 9:56 PM, Udo van den Heuvel wrote:
>> I.e.: it looks like I will lose some funcionality when I disable
>> SND_HDA_CODEC_REALTEK.
>
> OK. At present you can't have it both ways, i.e., SND_HDA_CODEC_REALTEK
> with no LEDS. That driver
On 07. 10. 20, 16:54, Josh Poimboeuf wrote:
-ENOPARSE on $SUBJECT.
Also please address it to x...@kernel.org, I think the tip maintainers
can pick up the fix directly.
Hmm, weird, I must have sent an older version as my current patch in the
tree has:
Cc: Miroslav Benes
Cc: Josh Poimboeuf
On 10/12/2020 12:59 PM, Ard Biesheuvel wrote:
> On Tue, 6 Oct 2020 at 08:36, Anshuman Khandual
> wrote:
>>
>>
>>
>> On 09/30/2020 01:32 PM, Anshuman Khandual wrote:
>>> But if __is_lm_address() checks against the effective linear range instead
>>> i.e [_PAGE_OFFSET(vabits_actual)..(PAGE_END -
The Marvell 88E6393X device is a single-chip integration of a 11-port
Ethernet switch with eight integrated Gigabit Ethernet (GbE) transceivers
and three 10-Gigabit interfaces.
This patch adds functionalities specific to mv88e6393x family (88E6393X,
88E6193X and 88E6191X)
Signed-off-by: Pavana
On 14-10-2020 06:49, Randy Dunlap wrote:
> If you disable SND_HDA_CODEC_REALTEK, then the rest of the
> LED kconfig symbols can be disabled.
Sure,
but:
# dmesg|grep audi
(...)
[ 19.971537] snd_hda_codec_generic hdaudioC0D0: ignore pin 0x7, too
many assigned pins
[ 19.973547]
Hi, Chunfeng:
On Tue, 2020-10-13 at 16:52 +0800, Chunfeng Yun wrote:
> Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml
>
> Signed-off-by: Chunfeng Yun
> ---
> v2: fix binding check warning of reg in example
> ---
> .../display/mediatek/mediatek,hdmi.txt| 17 +---
>
On 13-10-20, 17:17, Surendran K wrote:
> _setup_req(..) never returns negative value.
> Hence the condition ret < 0 is never met
The subsystem is "dmaengine", git log would tell you the tags to use
>
> Signed-off-by: Surendran K
> ---
> drivers/dma/pl330.c | 2 --
> 1 file changed, 2
On 13-10-2020 18:03, Randy Dunlap wrote:
> On 10/13/20 8:53 AM, Randy Dunlap wrote:
>> [adding LED people + list]
>>
>> On 10/13/20 6:24 AM, Udo van den Heuvel wrote:
(...)
So how do I disable this stuff?
>
> I was able to disable LEDS_CLASS and NEW_LEDS after I disabled the
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Thanks Mark Brown for your time !!!
On 10/13/2020 8:45 PM, Mark Brown wrote:
On Tue, Oct 13, 2020 at 07:09:46PM +0530, Srinivasa Rao Mandadapu wrote:
From: V Sujith Kumar Reddy
Disable MI2S bit clock from PAUSE/STOP/SUSPEND usecase
instead of shutdown time. Acheive this by invoking
I will add a dt-bindings commit for this change.
Thanks for review.
JC
On 9/28/20 9:18 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:35PM +0800, JC Kuo wrote:
>> PMC driver provides USB sleepwalk registers access to XUSB PADCTL
>> driver. This commit adds a "nvidia,pmc" property
I will amend commit accordingly and submit a new patch.
Thanks for review.
JC
On 9/28/20 9:17 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:34PM +0800, JC Kuo wrote:
>> This commit implements a register map which grants USB (UTMI and HSIC)
>> sleepwalk registers access to USB PHY
commit 64fa3aff89785b5a924ce3934f6595c35b4dffee
Author: Sharon Dvir
Date: Wed Aug 17 15:35:09 2016 +0300
iwlwifi: pcie: give a meaningful name to interrupt request
perhaps unintentionally for file:
drivers/net/wireless/intel/iwlwifi/pcie/internal.h
in function static inline const char
Document the higher level --insn-trace etc. perf script options.
Include the howto how to build xed into the manpage
Cc: adrian.hun...@intel.com
Signed-off-by: Andi Kleen
---
tools/perf/Documentation/perf-intel-pt.txt | 30 ++
1 file changed, 30 insertions(+)
diff --git
Peter suggested that using the exclusive mode in perf could
avoid some problems with bad scheduling of groups. Exclusive
is implemented in the kernel, but wasn't exposed by the perf tool,
so hard to use without custom low level API users.
Add support for marking groups or events with :e for
Hi,
Looks good to me. I add some comment. Please check them.
On 10/12/20 11:47 PM, Michael Auchter wrote:
> This patch adds an extcon driver for the TI TUSB320 USB Type-C device.
> This can be used to detect whether the port is configured as a
> downstream or upstream facing port.
>
>
On Tue, 13 Oct 2020 15:48:52 -0400
Steven Rostedt wrote:
> From: "Steven Rostedt (VMware)"
>
> After having a typo for writing a histogram trigger.
>
> Wrote:
> echo 'hist:key=pid:ts=common_timestamp.usec' >
> events/sched/sched_waking/trigger
>
> Instead of:
> echo
Asserting reset to a PLL when it's managed by hardware power sequencer would
break sequencer's state machine. Putting PLL in reset doesn't save some extra
power.
Thanks for review.
JC
On 9/28/20 9:06 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:30PM +0800, JC Kuo wrote:
>> Once
On 10/13/20 3:45 PM, Michael Ellerman wrote:
Christophe Leroy writes:
Le 13/10/2020 à 09:23, Aneesh Kumar K.V a écrit :
Christophe Leroy writes:
CPU_FTR_NODSISRALIGN has not been used since
commit 31bfdb036f12 ("powerpc: Use instruction emulation
infrastructure to handle alignment faults")
On Sun, 11 Oct 2020 23:52:53 +0530, Rayagonda Kokatanur wrote:
> --- a/drivers/i2c/busses/i2c-bcm-iproc.c
> +++ b/drivers/i2c/busses/i2c-bcm-iproc.c
>
> - } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
> - /* Start of SMBUS for Master Read */
> +
MT8192 msdc is an independent sub system, we need control more bus
clocks for it.
Add support for the additional subsys clocks to allow it to be
configured appropriately.
Signed-off-by: Wenbin Mei
Reviewed-by: Nicolas Boichat
---
drivers/mmc/host/mtk-sd.c | 74
This commit adds mmc device node for mt8192
Signed-off-by: Wenbin Mei
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 34
2 files changed, 123 insertions(+)
diff --git
Convert the mtk-sd binding to DT schema format using json-schema.
Signed-off-by: Wenbin Mei
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mmc/mtk-sd.txt| 75
.../devicetree/bindings/mmc/mtk-sd.yaml | 165 ++
2 files changed, 165 insertions(+), 75
MT8192 mmc host ip is compatible with MT8183.
Add support for this.
Signed-off-by: Wenbin Mei
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
Change in v7:
1)add "unevaluatedProperties" in mtk-sd.yaml
2)add Reviewed-by tag
Change in v6:
1)use devm_clk_get function for required clocks
Change in v5:
1)remove Reviewed-by tag
2)use devm_clk_bulk_get_optional instead of devm_clk_get_optional
for bulk clks
Change in v4:
1)drop "vmmc" and
Quoting Paul Cercueil (2020-09-02 18:50:44)
> The to_clk_info() previously had a BUG_ON() to check that it was only
> called for PLL clocks. Yet, all the other clocks were doing the exact
> same thing the macro does, in-line.
>
> Move the to_clk_info() macro to the top of the file, remove the
>
Quoting Paul Cercueil (2020-09-02 18:50:45)
> Use the readl_poll_timeout() function instead of rolling our own
> busy-wait loops. This makes the code simpler.
>
> Signed-off-by: Paul Cercueil
> ---
Applied to clk-next
Quoting Paul Cercueil (2020-09-02 18:50:47)
> The custom clocks have custom functions to round, get or set their rate.
> Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag.
>
> Signed-off-by: Paul Cercueil
> ---
Applied to clk-next
Quoting Paul Cercueil (2020-09-02 18:50:46)
> CLK_SET_RATE_GATE means that the clock must be gated when being
> reclocked. This is not the case for the PLLs in Ingenic SoCs.
>
> Signed-off-by: Paul Cercueil
> ---
Applied to clk-next
Quoting Paul Cercueil (2020-09-02 18:50:48)
> Clocks that don't have a divider are in our case all marked with the
> CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation
> should modify the value pointed to by parent_rate, in order to propagate
> the rate change to the parent, as
Quoting Navid Emamdoost (2020-08-09 16:11:58)
> In the implementation of bcm2835_register_pll(), the allocated pll is
> leaked if devm_clk_hw_register() fails to register hw. Release pll if
> devm_clk_hw_register() fails.
>
> Signed-off-by: Navid Emamdoost
> ---
Applied to clk-next
Quoting Claudiu Beznea (2020-08-24 23:59:11)
> Fix variable set but not used compilation warning.
>
> Fixes: 43b1bb4a9b3e ("clk: at91: clk-sam9x60-pll: re-factor to support plls
> with multiple outputs")
> Reported-by: kernel test robot
> Signed-off-by: Claudiu Beznea
> ---
Applied to
Quoting Claudiu Beznea (2020-08-24 23:59:09)
> There is no need to check parent_name variable while assigning it to
> init.parent_names. parent_name variable is already checked at
> the beginning of at91_clk_register_peripheral() function.
>
> Fixes: 6114067e437eb ("clk: at91: add PMC peripheral
Quoting Claudiu Beznea (2020-08-24 23:59:10)
> SAMA5D2 datasheet specifies on chapter 33.22.8 (PMC Clock Generator
> Main Oscillator Register) that writing any value other than
> 0x37 on KEY field aborts the write operation. Use the key when
> selecting main clock parent.
>
> Fixes: 27cb1c2083373
Quoting Xu Wang (2020-09-20 20:45:22)
> In case of error, the function clk_register() returns ERR_PTR()
> and never returns NULL. The NULL test in the return value check
> should be replaced with IS_ERR().
>
> Signed-off-by: Xu Wang
> ---
Applied to clk-next
Quoting Lubomir Rintel (2020-09-25 16:39:14)
> The LCD clock dividers are apparently based on one. No datasheet,
> determined empirically, but seems to be confirmed by line 19 of lcd.fth in
> OLPC laptop's Open Firmware [1]:
>
>h# 0700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz
>
Quoting Ryan Chen (2020-09-28 00:01:08)
> In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are
> default for Host SuperIO UART device, eSPI clk for Host eSPI bus access
> eSPI slave channel, those clks can't be disable should keep default,
> otherwise will affect Host side
Quoting Qiang Zhao (2020-09-15 20:03:10)
> From: Zhao Qiang
>
> On LS2088A, Watchdog need clk divided by 32,
> so modify MAX_PLL_DIV to 32
>
> Signed-off-by: Zhao Qiang
> ---
Applied to clk-next
Quoting Serge Semin (2020-09-20 04:03:35)
> We've discovered that disabling the so called Ethernet PLL causes reset of
> the devices consuming its outgoing clock. The resets happen automatically
> even if each underlying clock gate is turned off. Due to that we can't
> disable the Ethernet PLL
Patch 1 is a preparatory patch to reduce conflicts. Patch 2 fixes
balance failure due to ENOSPC in btrfs/156 on arm64 systems with
pagesize=64k. Minor conflicts in fs/btrfs/block-group.c are resolved.
Thanks.
Josef Bacik (2):
btrfs: don't pass system_chunk into can_overcommit
btrfs: take
Quoting Alexandru Ardelean (2020-10-01 01:59:47)
> From: Lars-Peter Clausen
>
> The axi-clkgen has (optional) fractional dividers on the output clock
> divider and feedback clock divider path. Utilizing the fractional dividers
> allows for a better resolution of the output clock, being able to
>
Quoting Alexandru Ardelean (2020-10-01 01:59:48)
> From: Lars-Peter Clausen
>
> Using the fractional dividers requires some additional power bits to be
> set.
>
> The fractional power bits are not documented and the current heuristic
> for setting them seems be insufficient for some cases. Just
From: Josef Bacik
commit 9f246926b4d5db4c5e8c78e4897757de26c95be6 upstream
We have the space_info, we can just check its flags to see if it's the
system chunk space info.
Reviewed-by: Nikolay Borisov
Reviewed-by: Qu Wenruo
Reviewed-by: Johannes Thumshirn
Signed-off-by: Josef Bacik
From: Josef Bacik
commit a30a3d2067536cbcce26c055e70cc3a6ae4fd45c upstream
inc_block_group_ro does a calculation to see if we have enough room left
over if we mark this block group as read only in order to see if it's ok
to mark the block group as read only.
The problem is this calculation
Quoting Krzysztof Kozlowski (2020-10-01 09:56:45)
> The Exynos clock output (clkout) driver uses same register address space
> (Power Management Unit address space) as Exynos PMU driver and same set
> of compatibles. It was modeled as clock provider instantiated with
> CLK_OF_DECLARE_DRIVE().
>
Quoting Krzysztof Kozlowski (2020-10-01 09:56:46)
> diff --git a/drivers/clk/samsung/clk-exynos-clkout.c
> b/drivers/clk/samsung/clk-exynos-clkout.c
> index 34ccb1d23bc3..68af082d4716 100644
> --- a/drivers/clk/samsung/clk-exynos-clkout.c
> +++ b/drivers/clk/samsung/clk-exynos-clkout.c
> @@
1. Support for some new features
2. fix up some error
Chang in V4:
[PATCH v3 1/5] : Update the commit message.
[PATCH v3 2/5] : Update the commit message.
Chang in V3:
[PATCH v2 3/6] : It's been merged
So rebased and resubmit.
Chang in V2:
[PATCH v2 5/6] : fix up the Register error, and add
support fractional divider with one level and two level parent clock
.i.e:
normal fractional divider is:
|--\
---[GPLL]---| \ |--\
---[CPLL]---|mux|--[GATE]--[DIV]---| \
---[NPLL]---| /|
If setting freq is not support in rockchip_pll_rate_table,
It can calculate and set pll params by auto.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-pll.c | 215 ++---
1 file changed, 200 insertions(+), 15 deletions(-)
diff --git
Can you check your get_maintainers script invocation? Not sure why arm64
maintainers are Cced on a clk patch.
Quoting Varadarajan Narayanan (2020-09-27 22:15:34)
> Add programming sequence support for managing the Stromer
> PLLs.
>
> Signed-off-by: Varadarajan Narayanan
> ---
>
Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the pmugrf.
Use MUXPMUGRF() to cover this special clock-type.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk.c | 9 +
drivers/clk/rockchip/clk.h | 17
set pll sequence:
->set pll to slow mode or other plls
->set pll down
->set pll params
->set pll up
->wait pll lock status
->set pll to normal mode
To slove the system error:
wait_pll_lock: timeout waiting for pll to lock
pll_set_params: pll update
>From Rockchips fractional divider usage, some clocks can be generated
by fractional divider, but the input clock frequency of fractional
divider should be less than a specified value.
.i.e:
|--\
---[GPLL]---| \ |--\
Reviewed-by: Alex Shi
在 2020/10/14 上午10:20, Bailu Lin 写道:
> This is a Chinese translated version of
> Documentation/arm64/hugetlbpage.rst
>
> Signed-off-by: Bailu Lin
> ---
> Changes in v3:
> - Modify a translation as Alex sugguested.
> Changes in v2:
> - Fix Sphinx 2.4.4's waring by
On Tue, 2020-10-13 at 17:10 +0200, Matthias Brugger wrote:
>
> On 12/10/2020 14:45, Wenbin Mei wrote:
> > MT8192 msdc is an independent sub system, we need control more bus
> > clocks for it.
> > Add support for the additional subsys clocks to allow it to be
> > configured appropriately.
> >
> >
Quoting Varadarajan Narayanan (2020-09-27 22:15:36)
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 0583273..d1a2504 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -155,6 +155,14 @@ config IPQ_GCC_8074
> i2c, USB, SD/eMMC, etc.
Yes, it's safe to apply "clk: tegra: Don't enable PLLE HW sequencer at init"
before the others have applied. Disabling PLLE hardware power sequencer will not
cause any functionality problem to XUSB/PCIE/SATA. The only thing changed is
PLLE won't be powered off by hardware when all clients are in
> On Sun, Oct 11, 2020 at 08:54:38AM -0700, t...@redhat.com wrote:
> > From: Tom Rix
> >
> > The clang build reports this warning
> >
> > fw.c:1485:21: warning: address of array 'rtwdev->chip->fw_fifo_addr'
> > will always evaluate to 'true'
> > if (!rtwdev->chip->fw_fifo_addr) {
> >
This is a Chinese translated version of
Documentation/arm64/hugetlbpage.rst
Signed-off-by: Bailu Lin
---
Changes in v3:
- Modify a translation as Alex sugguested.
Changes in v2:
- Fix Sphinx 2.4.4's waring by increasing underline' size.
---
Documentation/arm64/hugetlbpage.rst | 2
On 2020/9/8 11:34, Leizhen (ThunderTown) wrote:
>
>
> On 2020/9/8 10:40, Guenter Roeck wrote:
>> On 9/7/20 12:50 AM, Leizhen (ThunderTown) wrote:
>>> Hi, Wim Van Sebroeck, Guenter Roeck:
>>> What's your opinion? Guenter Roeck given "Reviewed-by" two weeks ago.
>>>
>>
>> The patch is in my
Protection Keys for Supervisor Pages (PKS) uses IA32_PKRS MSR (PKRS) at
index 0x6E1 to allow software to manage supervisor protection key
rights. For performance consideration, PKRS intercept will be disabled
so that the guest can access the PKRS without VM exits.
PKS introduces dedicated control
PKRU represents the PKU register utilized in the protection key rights
check for user pages. Protection Keys for Superviosr Pages (PKS) extends
the protection key architecture to cover supervisor pages.
Rename the *pkru* related variables and functions to *pkr* which stands
for both of the PKRU
This unit-test is intended to test the KVM support for Protection Keys
for Supervisor Pages (PKS). If CR4.PKS is set in long mode, supervisor
pkeys are checked in addition to normal paging protections and Access or
Write can be disabled via a MSR update without TLB flushes when
permissions change.
PKS MSR passes through guest directly. Configure the MSR to match the
L0/L1 settings so that nested VM runs PKS properly.
Signed-off-by: Chenyi Qiang
---
arch/x86/kvm/vmx/nested.c | 37 +++--
arch/x86/kvm/vmx/vmcs12.c | 2 ++
arch/x86/kvm/vmx/vmcs12.h | 6
pkr_mask bitmap indicates if protection key checks are needed for user
pages currently. It is indexed by page fault error code bits [4:1] with
PFEC.RSVD replaced by the ACC_USER_MASK from the page tables. Refactor
it by reverting to the use of PFEC.RSVD. After that, PKS and PKU can
share the same
PKS(Protection Keys for Supervisor Pages) is a feature that extends the
Protection Key architecture to support thread-specific permission
restrictions on supervisor pages.
A new PKS MSR(PKRS) is defined in kernel to support PKS, which holds a
set of permissions associated with each protection
Protection Keys for Supervisor Pages(PKS) is a feature that extends the
Protection Keys architecture to support thread-specific permission
restrictions on supervisor pages.
PKS works similar to an existing feature named PKU(protecting user pages).
They both perform an additional check after all
Advertise pkr_mask to cache the conditions where pretection key checks
for supervisor pages are needed. When the accessed pages are those with
a translation for which the U/S flag is 0 in at least one
paging-structure entry controlling the translation, they are the
supervisor pages and PKRS
Existence of PKS is enumerated via CPUID.(EAX=7H,ECX=0):ECX[31]. It is
enabled by setting CR4.PKS when long mode is active. PKS is only
implemented when EPT is enabled and requires the support of VM_{ENTRY,
EXIT}_LOAD_IA32_PKRS currently.
Signed-off-by: Chenyi Qiang
---
Quoting Taniya Das (2020-10-13 10:11:49)
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml
> b/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml
> new file mode 100644
> index 000..07bd38e
> --- /dev/null
> +++
On Tue, Oct 13, 2020 at 11:23:08AM -0700, Dave Hansen wrote:
> On 10/9/20 12:42 PM, ira.we...@intel.com wrote:
> > +/*
> > + * PKS is independent of PKU and either or both may be supported on a CPU.
> > + * Configure PKS if the cpu supports the feature.
> > + */
>
> Let's at least be consistent
Quoting Taniya Das (2020-10-13 10:11:48)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c
> b/drivers/clk/qcom/clk-alpha-pll.c
> index 26139ef..17e1fc0 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -1561,3 +1571,73 @@ const struct clk_ops
Hi Tom,
On Tue, 13 Oct 2020 09:17:58 -0500
Tom Zanussi wrote:
> Add a selftest that verifies that the syntax error messages and caret
> positions are correct for most of the possible synthetic event syntax
> error cases.
>
> Signed-off-by: Tom Zanussi
> ---
>
Quoting Taniya Das (2020-10-13 10:11:50)
> diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
> new file mode 100644
> index 000..e954d21
> --- /dev/null
> +++ b/drivers/clk/qcom/camcc-sc7180.c
> @@ -0,0 +1,1737 @@
[...]
> +
> +enum {
> + P_BI_TCXO,
> +
On Tue, Oct 13, 2020 at 12:38:36PM -0400, Alan Stern wrote:
> On Tue, Oct 13, 2020 at 09:33:54AM -0700, Paul E. McKenney wrote:
> > On Tue, Oct 13, 2020 at 02:14:29PM +0200, Mauro Carvalho Chehab wrote:
> > > - The sysfs.txt file was converted to ReST and renamed;
> > > - The
On Tue, Oct 13, 2020 at 10:46:08PM +0200, Mauro Carvalho Chehab wrote:
> Em Tue, 13 Oct 2020 09:34:04 -0700
> "Paul E. McKenney" escreveu:
>
> > On Tue, Oct 13, 2020 at 01:54:25PM +0200, Mauro Carvalho Chehab wrote:
> > > Changeset 53c72b590b3a ("rcu/tree: cache specified number of objects")
> >
On 2020/10/14 1:53, Dan Murphy wrote:
> Zhen
>
> On 10/13/20 11:08 AM, Zhen Lei wrote:
>> There are so many properties have not been described in this yaml file,
>> and a lot of errors will be reported. Especially, some yaml files such as
>> google,cros-ec-typec.yaml, extcon-usbc-cros-ec.yaml
Quoting Srinivas Kandagatla (2020-09-25 03:31:14)
> GFM Muxes in AUDIO_CC control clocks to LPASS WSA and RX Codec Macros.
> This patch adds support to these muxes.
>
> Signed-off-by: Srinivas Kandagatla
> ---
> drivers/clk/qcom/Kconfig| 6 +
> drivers/clk/qcom/Makefile
Hi Maintainers,
Does this patch ready to merge?
On 2020/7/7 下午7:25, Sandy Huang wrote:
don't mask possible_crtcs if remote-point is disabled.
Signed-off-by: Sandy Huang
---
drivers/gpu/drm/drm_of.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/drm_of.c
Quoting Srinivas Kandagatla (2020-09-25 03:31:11)
> This patchset adds support for GFM Muxes found in LPASS
> (Low Power Audio SubSystem) IP in Audio Clock Controller
> and Always ON clock controller.
>
> Clocks derived from these muxes are consumed by LPASS Digital Codec.
> Currently the driver
allyesconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a005-20201013
i386 randconfig-a006-20201013
i386 randconfig-a001-20201013
i386 randconfig-a003-20201013
i386
defconfig
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a004-20201013
x86_64
allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a004-20201013
x86_64 randconfig-a002-20201013
-a005-20201013
i386 randconfig-a006-20201013
i386 randconfig-a001-20201013
i386 randconfig-a003-20201013
i386 randconfig-a004-20201013
i386 randconfig-a002-20201013
x86_64 randconfig-a004-20201013
x86_64
On 9/26/20 9:18 PM, William Breathitt Gray wrote:
This patch introduces a character device interface for the Counter
subsystem. Device data is exposed through standard character device read
operations. Device data is gathered when a Counter event is pushed by
the respective Counter device
ring_request_msix() misses to call ida_simple_remove() in an error path.
Add a label 'err_ida_remove' and jump to it.
Fixes: 046bee1f9ab8 ("thunderbolt: Add MSI-X support")
Signed-off-by: Jing Xiangfeng
---
drivers/thunderbolt/nhi.c | 17 ++---
1 file changed, 14 insertions(+), 3
On 10/13/2020 10:19 AM, Georgi Djakov wrote:
Let's simplify the cmp_vcd() function and replace the conditionals
with just a single statement, which also improves readability.
Signed-off-by: Georgi Djakov
---
drivers/interconnect/qcom/bcm-voter.c | 15 ---
1 file changed, 4
On 2020-10-09 09:42, Manivannan Sadhasivam wrote:
On Fri, Sep 18, 2020 at 07:02:33PM -0700, Bhaumik Bhatt wrote:
Move MHI to a firmware download error state for a failure to find
the firmware files or to load SBL or EBL image using BHI/BHIe. This
helps detect an error state sooner and shortens
From: Peng Fan
Add usb alias for bootloader emulator the controller in correct order.
Signed-off-by: Peng Fan
---
arch/arm/boot/dts/imx6qdl.dtsi | 4
arch/arm/boot/dts/imx6sl.dtsi | 3 +++
arch/arm/boot/dts/imx6sll.dtsi | 2 ++
arch/arm/boot/dts/imx6sx.dtsi | 3 +++
Quoting Jonathan Marek (2020-09-27 12:06:51)
> Add support for the display clock controller found on SM8150 and SM8250.
>
> Signed-off-by: Jonathan Marek
> Tested-by: Dmitry Baryshkov (SM8250)
> ---
Applied to clk-next
Quoting Jonathan Marek (2020-09-27 12:06:50)
> Add device tree bindings for display clock controller for
> Qualcomm Technology Inc's SM8150 and SM8250 SoCs.
>
> Signed-off-by: Jonathan Marek
> Tested-by: Dmitry Baryshkov (SM8250)
> ---
Applied to clk-next
On 2020/10/14 1:32, Dan Murphy wrote:
> Zhen
>
> On 10/13/20 11:08 AM, Zhen Lei wrote:
>> The property name used in arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts is
>> cmd-gpio.
>>
>> arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts:235:
>> cmd-gpio = < 155 GPIO_ACTIVE_HIGH>;
>>
>> Signed-off-by: Zhen Lei
> -Original Message-
> From: Alex Williamson [mailto:alex.william...@redhat.com]
> Sent: Wednesday, October 14, 2020 1:50 PM
> To: Song Bao Hua (Barry Song)
> Cc: tiantao (H) ; eric.au...@redhat.com;
> coh...@redhat.com; k...@vger.kernel.org; linux-kernel@vger.kernel.org;
> Linuxarm
>
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