> I wouldn't expect all hypervisors to necessarily set CPUID.01H:ECX[bit
> 31]. Architecturally, on Intel CPUs, that bit is simply defined as
> "not used." There is no documented contract between Intel and
> hypervisor vendors regarding the use of that bit. (AMD, on the other
> hand, *does* documen
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 407ab579637ced6dc32cfb2295afb7259cca4b22
commit: e5fc436f06eef54ef512ea55a9db8eb9f2e76959 sparse: use static inline for
__chk_{user,io}_ptr()
date: 2 months ago
config: sh-randconfig-s031-20201110 (attache
On 11/4/20 5:30 PM, chris hyser wrote:
On 10/19/20 9:43 PM, Joel Fernandes (Google) wrote:
In order to prevent interference and clearly support both per-task and CGroup
APIs, split the cookie into 2 and allow it to be set from either per-task, or
CGroup API. The final cookie is the combined valu
From: Eric Dumazet
Date: Mon, 9 Nov 2020 15:13:47 -0800
> From: Eric Dumazet
>
> This came while reviewing Alexander Lobakin patch against UDP GRO:
>
> We want to make sure skb wont be changed by these helpers
> while it is owned by GRO stack.
>
> Eric Dumazet (2):
> inet: constify inet_sdif(
Chun-Kuang Hu 於 2020年10月29日 週四 下午11:27寫道：
>
> mtk_mipi_dsi_phy is currently placed inside mediatek drm driver, but it's
> more suitable to place a phy driver into phy driver folder, so move
> mtk_mipi_dsi_phy driver into phy driver folder.
Applied the whole series into mediatek-drm-next [1].
[1]
Hi Zhou,
Le sam. 7 nov. 2020 à 19:52, 周琰杰 (Zhou Yanjie)
a écrit :
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
nodes for CU1000-Neo.
3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
On Thu, 05 Nov 2020 21:29:01 + Alexander Lobakin wrote:
> Similar to commit fda55eca5a33f
> ("net: introduce skb_transport_header_was_set()"), avoid resetting
> transport offsets that were already set by GRO layer. This not only
> mirrors the behavior of __netif_receive_skb_core(), but also mak
On 11/9/20 5:54 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.4.242 release.
There are 86 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made
On Tue, Nov 03, 2020 at 12:17:17PM +, Will Deacon wrote:
> Hi all,
>
> These patches were previously posted as part of a larger series enabling
> architectures to override __READ_ONCE():
>
> v3: https://lore.kernel.org/lkml/20200710165203.31284-1-w...@kernel.org/
>
> With the bulk of that
On Mon, Nov 9, 2020 at 2:57 PM Luck, Tony wrote:
>
> > I thought Linux had long ago gone the route of turning rdmsr/wrmsr
> > into rdmsr_safe/wrmsr_safe, so that the guest would ignore the #GPs on
> > writes and return zero to the caller for #GPs on reads.
>
> Linux just switched that around for t
On 11/9/20 5:55 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.14.205 release.
There are 48 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made
On 11/9/20 5:53 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.9.242 release.
There are 117 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made
On 11/9/20 5:55 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.14.205 release.
There are 48 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made
On Tue, 20 Oct 2020 09:50:34 +0200, Jerome Brunet wrote:
> There now the menu entries for the amlogic clock controllers.
> Do not select these when ARM64 is enabled so it possible to ship only the
> required.
Applied, thanks!
[1/1] arm64: meson: ship only the necessary clock controllers
(no
Hi,
On Mon, Nov 9, 2020 at 1:37 PM Douglas Anderson wrote:
>
> +int i2c_hid_acpi_probe(struct i2c_client *client,
> + const struct i2c_device_id *dev_id)
> +{
> + struct device *dev = &client->dev;
> + struct i2c_hid_acpi *ihid_acpi;
> + u16 hid_descriptor_a
Booting as a guest under KVM results in error messages about
unchecked MSR access:
[6.814328][T0] unchecked MSR access error: RDMSR from 0x17f at rIP:
0x84483f16 (mce_intel_feature_init+0x156/0x270)
because KVM doesn't provide emulation for random model specific registers.
Check
On 10/19/20 9:43 PM, Joel Fernandes (Google) wrote:
In order to prevent interference and clearly support both per-task and CGroup
APIs, split the cookie into 2 and allow it to be set from either per-task, or
CGroup API. The final cookie is the combined value of both and is computed when
the stop-
On 11/9/20 5:54 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.19.156 release.
There are 71 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made
On 11/9/20 5:54 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 5.4.76 release.
There are 85 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made b
On 11/9/20 5:54 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 5.9.7 release.
There are 133 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made b
Hi Mark
> > This series is a prepraration for using generic graph driver for Tegra210
> > audio. Tegra audio graph series will be sent in a separate series because
> > it has some dependency over other series for documentation work. This
> > series can focus on the generic ASoC driver updates. B
On Mon, Nov 9, 2020 at 2:23 PM Jordan Crouse wrote:
>
> Use the new adreno-smmu-priv fault info function to get more SMMU
> debug registers and print the current TTBR0 to debug per-instance
> pagetables and figure out which GPU block generated the request.
>
> Signed-off-by: Jordan Crouse
> ---
>
On Mon, 9 Nov 2020 12:10:43 +0100
Peter Zijlstra wrote:
> > SYM_INNER_LABEL(ftrace_caller_op_ptr, SYM_L_GLOBAL)
> > /* Load the ftrace_ops into the 3rd parameter */
> > movq function_trace_op(%rip), %rdx
> >
> > - /* regs go into 4th parameter (but make it NULL) */
> > - movq $0, %
On 10/29/20 7:15 AM, tip-bot2 for Thomas Gleixner wrote:
> The following commit has been merged into the x86/apic branch of tip:
>
> Commit-ID: a27dca645d2c0f31abb7858aa0e10b2fa0f2f659
> Gitweb:
> https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=a27dca645d2c0f31ab
On Mon, Nov 9, 2020 at 2:23 PM Jordan Crouse wrote:
>
> Add a callback in adreno-smmu-priv to read interesting SMMU
> registers to provide an opportunity for a richer debug experience
> in the GPU driver.
>
> Signed-off-by: Jordan Crouse
> ---
>
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 19
The following changes since commit 3cea11cd5e3b00d91caf0b4730194039b45c5891:
Linux 5.10-rc2 (2020-11-01 14:43:51 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git tags/fscrypt-for-linus
for you to fetch changes up to 92cfcd030e4b1de11a6b1ed
On Fri, Oct 23, 2020 at 10:36 AM Sami Tolvanen wrote:
>
> On Wed, Oct 21, 2020 at 05:22:59PM -0700, Sami Tolvanen wrote:
> > There are a couple of differences, like the first "undefined stack
> > state" warning pointing to set_bringup_idt_handler.constprop.0()
> > instead of __switch_to_asm(). I t
ANWALTSKANZLEI: ABOGADO VITALIS MANUEL COLON.
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E mail. analyn.hernan...@mail2lawyer.com
AKTENZEICHEN: JMCB-ES/11-547/05-17
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Abschließende Mitteilung für die Zahlung des nicht beanspruchten Preisgeldes.
On Mon, Nov 09, 2020 at 01:54:54PM +0100, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.19.156 release.
> There are 71 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me kno
On Mon, Nov 09, 2020 at 01:54:22PM +0100, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.9.7 release.
> There are 133 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
On Mon, Nov 09, 2020 at 01:53:46PM +0100, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.9.242 release.
> There are 117 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me kno
On Mon, Nov 09, 2020 at 01:54:57PM +0100, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.4.76 release.
> There are 85 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
On Mon, Nov 09, 2020 at 01:55:09PM +0100, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.14.205 release.
> There are 48 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me kno
On Mon, Nov 09, 2020 at 01:54:07PM +0100, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.4.242 release.
> There are 86 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know
Hi Dongjiu,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on clk/clk-next]
[also build test WARNING on v5.10-rc3 next-20201109]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--bas
On Fri, 6 Nov 2020 07:21:06 -0300 Marcelo Ricardo Leitner wrote:
> On Fri, Nov 06, 2020 at 10:48:24AM +0100, Petr Malat wrote:
> > On Fri, Nov 06, 2020 at 05:46:34AM -0300, Marcelo Ricardo Leitner wrote:
> > > On Thu, Nov 05, 2020 at 11:39:47AM +0100, Petr Malat wrote:
> > > > Function sctp_dst
> I thought Linux had long ago gone the route of turning rdmsr/wrmsr
> into rdmsr_safe/wrmsr_safe, so that the guest would ignore the #GPs on
> writes and return zero to the caller for #GPs on reads.
Linux just switched that around for the machine check banks ... if they #GP
fault, then something
On Mon, Nov 9, 2020 at 5:50 PM Jakub Kicinski wrote:
>
> But please at least repost for net and CC Mark and the SPI list
> for input.
>
> Maybe Mark has a different idea on how client drivers should behave.
>
> Also please obviously CC the author of the patch who introduced
> the breakage.
I
On Mon, Nov 9, 2020 at 4:39 PM Michael Walle wrote:
>
> Am 2020-11-09 23:05, schrieb Rob Herring:
> > On Sun, Nov 08, 2020 at 07:51:07PM +0100, Michael Walle wrote:
> >> To avoid future mistakes in the device tree for the clockgen module,
> >> add
> >> constants for the clockgen subtype as well as
On 10/11/20 4:08 am, Henrik Rydberg wrote:
> Hi Brad,
>
>> Out of morbid curiosity I grabbed an older MacOS AppleSMC.kext (10.7) and
>> ran it through the disassembler.
>>
>> Every read/write to the SMC starts the same way with a check to make sure
>> the SMC is in a sane state. If it's not, a r
On Wed, Sep 23, 2020 at 01:01:46AM +, Daniel Rosenberg wrote:
> These patches are on top of the f2fs dev branch
>
> F2FS currently supports casefolding and encryption, but not at
> the same time. These patches aim to rectify that. In a later follow up,
> this will be added for Ext4 as well. I'
On Mon, 9 Nov 2020 17:39:22 -0500 Sven Van Asbroeck wrote:
> What I already posted (as v1) should be the minimal fix.
> Can we proceed on that basis? I'll follow up with the helper
> after the net -> net-next merge, as you suggested.
Well, you cut off the relevant part of my email where I said:
LLD does not yet support any big endian architectures. Make this config
non-selectable when using LLD until LLD is fixed.
Link: https://github.com/ClangBuiltLinux/linux/issues/965
Signed-off-by: Nick Desaulniers
---
arch/arm/mm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm
Hi,
Le dim. 8 nov. 2020 à 0:36, Rikard Falkeborn
a écrit :
The only usage of ingenic_rproc_ops is to pass its address to
devm_rproc_alloc(), which accepts a const pointer. Make it const to
allow the compiler to put it in read-only memory.
Signed-off-by: Rikard Falkeborn
Acked-by: Paul Cerc
On 11/9/20 2:28 PM, Casey Schaufler wrote:
> On 11/7/2020 2:05 PM, John Johansen wrote:
>> On 11/7/20 1:15 AM, Greg KH wrote:
>>> On Fri, Nov 06, 2020 at 04:20:43PM -0800, Casey Schaufler wrote:
On 11/5/2020 1:22 AM, Greg KH wrote:
> On Wed, Nov 04, 2020 at 03:41:03PM -0800, Casey Schaufle
A client can attempt to unprepare certain channels for transfer even
after the execution environment they are supposed to run in has changed.
In the event that happens, the device need not be notified of the reset
and the host can proceed with clean up for the channel context and
memory allocated f
MHI specification shows a state machine with support for STOP channel command
and the validity of certain state transitions. MHI host currently does not
provide any mechanism to stop a channel and restart it without resetting it.
There are also times when the device moves on to a different executio
Add support to enable sending the stop channel command and
improve the channel handling state machine such that all commands
go through a common function. This can help ensure that the state
machine is not violated in any way and adheres to the MHI
specification.
Signed-off-by: Bhaumik Bhatt
---
Add support to receive the response to a STOP channel command to the
MHI bus. If a client would like to STOP a channel instead of issuing
a RESET to it, this would provide support for it.
Signed-off-by: Bhaumik Bhatt
---
drivers/bus/mhi/core/init.c | 5 +++--
drivers/bus/mhi/core/main.c | 5
Some MHI clients may want to request for pausing or resuming of the
data transfers for their channels. Enable them to do so using the new
APIs provided for the same.
Signed-off-by: Bhaumik Bhatt
---
drivers/bus/mhi/core/main.c | 41 +
include/linux/mhi.h
On Mon, Nov 09, 2020 at 01:44:03PM -0800, si-wei liu wrote:
>
> On 11/8/2020 7:21 PM, Jason Wang wrote:
> >
> > On 2020/11/6 上午6:57, si-wei liu wrote:
> > >
> > > On 11/4/2020 7:26 PM, Jason Wang wrote:
> > > >
> > > > On 2020/11/5 上午7:33, Si-Wei Liu wrote:
> > > > > Pinned pages are not proper
On Mon, Nov 09 2020 at 13:30, Jason Gunthorpe wrote:
> On Mon, Nov 09, 2020 at 12:21:22PM +0100, Thomas Gleixner wrote:
>> >> Is the IOMMU/Interrupt remapping unit able to catch such messages which
>> >> go outside the space to which the guest is allowed to signal to? If yes,
>> >> problem solved.
On Mon, Nov 09, 2020 at 01:30:34PM -0400, Jason Gunthorpe wrote:
>
> > Again, trap emulate does not work for IMS when the IMS store is software
> > managed guest memory and not part of the device. And that's the whole
> > reason why we are discussing this.
>
> With PASID tagged interrupts and a I
On Mon, Nov 9, 2020 at 5:36 PM Jakub Kicinski wrote:
>
> Yes, most certainly. Especially with 5.10 being LTS.
>
> You can send a minimal fix (perhaps what you got already?), and follow
> up with the helper as suggested by Andrew after ~a week when net is
> merged into net-next.
>
What I already p
Am 2020-11-09 23:05, schrieb Rob Herring:
On Sun, Nov 08, 2020 at 07:51:07PM +0100, Michael Walle wrote:
To avoid future mistakes in the device tree for the clockgen module,
add
constants for the clockgen subtype as well as a macro for the PLL
divider.
Signed-off-by: Michael Walle
---
Changes
On Mon, Nov 9, 2020 at 2:09 PM Luck, Tony wrote:
>
> What does KVM do with model specific MSRs?
"Model specific model-specific registers?" :-)
KVM only implements a small subset of MSRs. By default, any access to
the rest raises #GP.
> Looks like you let the guest believe it was running on one
On Mon, 9 Nov 2020 17:27:28 -0500 Sven Van Asbroeck wrote:
> On Mon, Nov 9, 2020 at 5:23 PM Jakub Kicinski wrote:
> >
> > Is it only broken for you in linux-next or just in the current 5.10
> > release?
>
> It's broken for me in the current 5.10 release. That means it should
> go to net, not ne
From: Tom Lendacky
An SEV-ES guest is started by invoking a new SEV initialization ioctl,
KVM_SEV_ES_INIT. This identifies the guest as an SEV-ES guest, which is
used to drive the appropriate ASID allocation, VMSA encryption, etc.
Before being able to run an SEV-ES vCPU, the vCPU VMSA must be en
From: Tom Lendacky
An SEV-ES vCPU requires additional VMCB initialization requirements for
vCPU creation and vCPU load/put requirements. This includes:
General VMCB initialization changes:
- Set a VMCB control bit to enable SEV-ES support on the vCPU.
- Set the VMCB encrypted VM save area ad
From: Tom Lendacky
The run sequence is different for an SEV-ES guest compared to a legacy or
even an SEV guest. The guest vCPU register state of an SEV-ES guest will
be restored on VMRUN and saved on VMEXIT. There is no need to restore the
guest registers directly and through VMLOAD before VMRUN
From: Tom Lendacky
SEV and SEV-ES guests each have dedicated ASID ranges. Update the ASID
allocation routine to return an ASID in the respective range.
Signed-off-by: Tom Lendacky
---
arch/x86/kvm/svm/sev.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff
From: Tom Lendacky
Typically under KVM, an AP is booted using the INIT-SIPI-SIPI sequence,
where the guest vCPU register state is updated and then the vCPU is VMRUN
to begin execution of the AP. For an SEV-ES guest, this won't work because
the guest register state is encrypted.
Following the GHC
From: Tom Lendacky
The GHCB specification defines how NMIs are to be handled for an SEV-ES
guest. To detect the completion of an NMI the hypervisor must not
intercept the IRET instruction (because a #VC while running the NMI will
issue an IRET) and, instead, must receive an NMI Complete exit even
From: Tom Lendacky
An SEV-ES vCPU requires additional VMCB vCPU load/put requirements. SEV-ES
hardware will restore certain registers on VMEXIT, but not save them on
VMRUM (see Table B-3 and Table B-4 of the AMD64 APM Volume 2), so make the
following changes:
General vCPU load changes:
- Durin
From: Tom Lendacky
The SVM host save area is used to restore some host state on VMEXIT of an
SEV-ES guest. After allocating the save area, clear it and add the
encryption mask to the SVM host save area physical address that is
programmed into the VM_HSAVE_PA MSR.
Signed-off-by: Tom Lendacky
---
From: Tom Lendacky
For SEV-ES guests, the interception of control register write access
is not recommended. Control register interception occurs prior to the
control register being modified and the hypervisor is unable to modify
the control register itself because the register is located in the
e
From: Tom Lendacky
The guest FPU state is automatically restored on VMRUN and saved on VMEXIT
by the hardware, so there is no reason to do this in KVM. Eliminate the
allocation of the guest_fpu save area and key off that to skip operations
related to the guest FPU state.
Signed-off-by: Tom Lenda
From: Tom Lendacky
For SEV-ES guests, the interception of control register write access
is not recommended. Control register interception occurs prior to the
control register being modified and the hypervisor is unable to modify
the control register itself because the register is located in the
e
From: Tom Lendacky
SEV-ES guests do not currently support SMM. Update the has_emulated_msr()
kvm_x86_ops function to take a struct kvm parameter so that the capability
can be reported at a VM level.
Since this op is also called during KVM initialization and before a struct
kvm instance is availa
From: Tom Lendacky
Since many of the registers used by the SEV-ES are encrypted and cannot
be read or written, adjust the __get_sregs() / __set_sregs() to take into
account whether the VMSA/guest state is encrypted.
For __get_sregs(), return the actual value that is in use by the guest
for all r
From: Tom Lendacky
For SEV-ES guests, the interception of control register write access
is not recommended. Control register interception occurs prior to the
control register being modified and the hypervisor is unable to modify
the control register itself because the register is located in the
e
On 11/7/2020 2:05 PM, John Johansen wrote:
> On 11/7/20 1:15 AM, Greg KH wrote:
>> On Fri, Nov 06, 2020 at 04:20:43PM -0800, Casey Schaufler wrote:
>>> On 11/5/2020 1:22 AM, Greg KH wrote:
On Wed, Nov 04, 2020 at 03:41:03PM -0800, Casey Schaufler wrote:
> Create a new entry "display" in th
From: Tom Lendacky
For an SEV-ES guest, string-based port IO is performed to a shared
(un-encrypted) page so that both the hypervisor and guest can read or
write to it and each see the contents.
For string-based port IO operations, invoke SEV-ES specific routines that
can complete the operation
From: Tom Lendacky
For SEV-ES guests, the interception of EFER write access is not
recommended. EFER interception occurs prior to EFER being modified and
the hypervisor is unable to modify EFER itself because the register is
located in the encrypted register state.
SEV-ES support introduces a ne
From: Tom Lendacky
For an SEV-ES guest, MMIO is performed to a shared (un-encrypted) page
so that both the hypervisor and guest can read or write to it and each
see the contents.
The GHCB specification provides software-defined VMGEXIT exit codes to
indicate a request for an MMIO read or an MMIO
From: Tom Lendacky
Add trace events for entry to and exit from VMGEXIT processing. The vCPU
id and the exit reason will be common for the trace events. The exit info
fields will represent the input and output values for the entry and exit
events, respectively.
Signed-off-by: Tom Lendacky
---
a
From: Tom Lendacky
The GHCB specification defines a GHCB MSR protocol using the lower
12-bits of the GHCB MSR (in the hypervisor this corresponds to the
GHCB GPA field in the VMCB).
Function 0x002 is a request to set the GHCB MSR value to the SEV INFO as
per the specification via the VMCB GHCB G
From: Tom Lendacky
This is a pre-patch to consolidate some exit handling code into callable
functions. Follow-on patches for SEV-ES exit handling will then be able
to use them from the sev.c file.
Signed-off-by: Tom Lendacky
---
arch/x86/kvm/svm/svm.c | 64 +
From: Tom Lendacky
The GHCB specification defines a GHCB MSR protocol using the lower
12-bits of the GHCB MSR (in the hypervisor this corresponds to the
GHCB GPA field in the VMCB).
Function 0x004 is a request for CPUID information. Only a single CPUID
result register can be sent per invocation,
From: Tom Lendacky
Add trace events for entry to and exit from VMGEXIT MSR protocol
processing. The vCPU will be common for the trace events. The MSR
protocol processing is guided by the GHCB GPA in the VMCB, so the GHCB
GPA will represent the input and output values for the entry and exit
events
From: Tom Lendacky
The GHCB specification defines a GHCB MSR protocol using the lower
12-bits of the GHCB MSR (in the hypervisor this corresponds to the
GHCB GPA field in the VMCB).
Function 0x100 is a request for termination of the guest. The guest has
encountered some situation for which it ha
From: Tom Lendacky
When a guest is running as an SEV-ES guest, it is not possible to emulate
instructions. Add support to prevent instruction emulation.
Signed-off-by: Tom Lendacky
---
arch/x86/kvm/svm/svm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/kvm/svm/svm.c b/arc
From: Tom Lendacky
SEV-ES adds a new VMEXIT reason code, VMGEXIT. Initial support for a
VMGEXIT includes mapping the GHCB based on the guest GPA, which is
obtained from a new VMCB field, and then validating the required inputs
for the VMGEXIT exit reason.
Since many of the VMGEXIT exit reasons c
From: Tom Lendacky
Since the guest register state of an SEV-ES guest is encrypted, debugging
is not supported. Update the code to prevent guest debugging when the
guest has protected state.
Additionally, an SEV-ES guest must only and always intercept DR7 reads and
writes. Update set_dr_intercept
From: Tom Lendacky
When a guest is running under SEV-ES, the hypervisor cannot access the
guest register state. There are numerous places in the KVM code where
certain registers are accessed that are not allowed to be accessed (e.g.
RIP, CR0, etc). Add checks to prevent register accesses and add
On Mon, Nov 9, 2020 at 5:23 PM Jakub Kicinski wrote:
>
> Is it only broken for you in linux-next or just in the current 5.10
> release?
It's broken for me in the current 5.10 release. That means it should
go to net, not net-next, correct?
From: Tom Lendacky
When performing VMGEXIT processing for an SEV-ES guest, register values
will be synced between KVM and the GHCB. Prepare for detecting when a GPR
has been updated (marked dirty) in order to determine whether to sync the
register to the GHCB.
Signed-off-by: Tom Lendacky
---
a
From: Tom Lendacky
When a SHUTDOWN VMEXIT is encountered, normally the VMCB is re-initialized
so that the guest can be re-launched. But when a guest is running as an
SEV-ES guest, the VMSA cannot be re-initialized because it has been
encrypted. For now, just return -EINVAL to prevent a possible a
From: Tom Lendacky
Allocate a page during vCPU creation to be used as the encrypted VM save
area (VMSA) for the SEV-ES guest. Provide a flag in the kvm_vcpu_arch
structure that indicates whether the guest state is protected.
When freeing a VMSA page that has been encrypted, the cache contents mu
From: Tom Lendacky
Add support to KVM for determining if a system is capable of supporting
SEV-ES as well as determining if a guest is an SEV-ES guest.
Signed-off-by: Tom Lendacky
---
arch/x86/kvm/Kconfig | 3 ++-
arch/x86/kvm/svm/sev.c | 47 ++
arch/
From: Tom Lendacky
On systems that do not have hardware enforced cache coherency between
encrypted and unencrypted mappings of the same physical page, the
hypervisor can use the VM page flush MSR (0xc001011e) to flush the cache
contents of an SEV guest page. When a small number of pages are being
From: Tom Lendacky
Update the GHCB accessor functions to add functions for retrieve GHCB
fields by name. Update existing code to use the new accessor functions.
Signed-off-by: Tom Lendacky
---
arch/x86/include/asm/svm.h | 10 ++
arch/x86/kernel/cpu/vmware.c | 12 ++--
2 files
From: Tom Lendacky
When both KVM support and the CCP driver are built into the kernel instead
of as modules, KVM initialization can happen before CCP initialization. As
a result, sev_platform_status() will return a failure when it is called
from sev_hardware_setup(), when this isn't really an err
From: Tom Lendacky
This patch series provides support for running SEV-ES guests under KVM.
Secure Encrypted Virtualization - Encrypted State (SEV-ES) expands on the
SEV support to protect the guest register state from the hypervisor. See
"AMD64 Architecture Programmer's Manual Volume 2: System P
On Mon, Nov 9, 2020 at 4:15 PM Alexander Lobakin wrote:
>
> While testing UDP GSO fraglists forwarding through driver that uses
> Fast GRO (via napi_gro_frags()), I was observing lots of out-of-order
> iperf packets:
>
> [ ID] Interval Transfer Bitrate Jitter
> [SUM] 0.0-40.
Add a callback in adreno-smmu-priv to read interesting SMMU
registers to provide an opportunity for a richer debug experience
in the GPU driver.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 19 +
drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++
in
This is an RFC to add an Adreno GPU specific handler for pagefaults. The first
patch starts by wiring up report_iommu_fault for arm-smmu. The next patch adds
a adreno-smmu-priv function hook to capture a handful of important debugging
registers such as TTBR0, CONTEXTIDR, FSYNR0 and others. This is
On Mon, 9 Nov 2020 17:19:48 -0500 Sven Van Asbroeck wrote:
> On Mon, Nov 9, 2020 at 5:04 PM Jakub Kicinski wrote:
> >
> > Yup
>
> Just a minute. Earlier in the thread, Andrew Lunn is suggesting I
> create a new spi helper function, and cross-post to the spi group(s).
>
> That doesn't sound lik
Call report_iommu_fault() to allow upper-level drivers to register their
own fault handlers.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
b/driv
Use the new adreno-smmu-priv fault info function to get more SMMU
debug registers and print the current TTBR0 to debug per-instance
pagetables and figure out which GPU block generated the request.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +-
drivers/gpu/drm/ms
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