On Mon, Nov 16, 2020 at 9:41 AM Lee Jones wrote:
>
> Very little attempt has been made to document these functions.
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c:227: warning: Function parameter or
> member 'ctl' not described in 'mdp5_ctl_set_
Including Heikki, who I forgot to add in the original patch email.
On Thu, Nov 05, 2020 at 06:03:05PM -0800, Prashant Malani wrote:
> On occasion, the Chrome Embedded Controller (EC) can send a mux
> configuration which doesn't map to a particular data mode. For instance,
> dedicated Type C charge
On Tuesday 17 Nov 2020 at 17:30:33 (+0100), Rafael J. Wysocki wrote:
[..]
> > > > Ionela Voinescu (8):
> > > > cppc_cpufreq: fix misspelling, code style and readability issues
> > > > cppc_cpufreq: clean up cpu, cpu_num and cpunum variable use
> > > > cppc_cpufreq: simplify use of performance
On Mon, Nov 16, 2020 at 05:40:51PM +, Lee Jones wrote:
> ... and demote non-conformant kernel-doc header.
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/nouveau/nvkm/core/firmware.c:71: warning: Function parameter
> or member 'subdev' not described in 'nvkm_firmwar
On Mon, Nov 16, 2020 at 5:40 PM Randy Dunlap wrote:
>
> riscv's uses barrier() so it should
> #include to prevent build errors.
>
> Fixes this build error:
> CC [M] drivers/net/ethernet/emulex/benet/be_main.o
> In file included from ./include/vdso/processor.h:10,
> from ./arc
On 11/17/20 7:28 PM, Borislav Petkov wrote:
On Tue, Nov 17, 2020 at 07:12:07PM +0100, Alexandre Chartre wrote:
Yes. L1TF/MDS allow some inter cpu-thread attacks which are not mitigated at
the moment. In particular, this allows a guest VM to attack another guest VM
or the host kernel running o
The 11/17/2020 14:30, Xiaoliang Yang wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> This patch introduce a redundancy flow action to implement frame
> replication and elimination for reliability, which is defined in
> IEEE P802.1CB.
>
>
Nit: please don't just make up random styles for the subject. Run
"git log --oneline" on the file and/or the directory and try to follow
the existing convention. Using random styles adds noise to the
system.
On Tue, Nov 17, 2020 at 09:42:14PM +0800, Chen Baozi wrote:
> Some PCIe designs require
On Tue, 17 Nov 2020 23:16:29 +0800, Zenghui Yu wrote:
> It was recently reported that if GICR_TYPER is accessed before the RD base
> address is set, we'll suffer from the unset @rdreg dereferencing. Oops...
>
> gpa_t last_rdist_typer = rdreg->base + GICR_TYPER +
> (rdre
On Tue, Nov 17, 2020 at 10:23:58AM -0800, Linus Torvalds wrote:
> On Mon, Nov 16, 2020 at 10:35 AM Mimi Zohar wrote:
> >
> > We need to differentiate between signed files, which by definition are
> > immutable, and those that are mutable. Appending to a mutable file,
> > for example, would result
On Tue, Nov 17, 2020 at 04:03:12AM +, Daniel Rosenberg wrote:
> I've included one ext4 patch from the previous set since it isn't in the f2fs
> branch, but is needed for the fscrypt changes.
Note that this is no longer the case, as this ext4 patch was merged in 5.10
(commit f8f4acb6cded: "ext4
On Mon, 16 Nov 2020 20:13:43 -0800 Michael Chan wrote:
> On Mon, Nov 16, 2020 at 7:01 PM Zhang Changzhong wrote:
> >
> > Fix to return a negative error code from the error handling
> > case instead of 0, as done elsewhere in this function.
> >
> > Fixes: 39a6f4bce6b4 ("b44: replace the ssb_dma API
Remove a superfluous semicolon following a closing function block
bracket.
Signed-off-by: Tyrel Datwyler
---
drivers/scsi/ibmvscsi/ibmvfc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/scsi/ibmvscsi/ibmvfc.c b/drivers/scsi/ibmvscsi/ibmvfc.c
index 01fe65de9086..0cab
The vfcFrame correlation field is 64bit handle that is intended to trace
I/O operations through both the client stack and VIOS stack when the
underlying physical FC adapter supports tagging.
Tag vfcFrames with the associated ibmvfc_event pointer handle.
Signed-off-by: Tyrel Datwyler
---
drivers
Both ibmvfc_show_host_(capabilities|npiv_version) functions retrieve
values from vhost->login_buf.resp buffer. This is the MAD response
buffer from the VIOS and as such any multi-byte non-string values are in
big endian format.
Byte swap these values to host cpu endian format for better human
read
On Tue, Nov 17, 2020 at 04:03:15AM +, Daniel Rosenberg wrote:
> Expand f2fs's casefolding support to include encrypted directories. To
> index casefolded+encrypted directories, we use the SipHash of the
> casefolded name, keyed by a key derived from the directory's fscrypt
> master key. This
Hello:
This patch was applied to netdev/net.git (refs/heads/master):
On Mon, 16 Nov 2020 21:07:13 +0800 you wrote:
> Fix to return a negative error code from the error handling
> case instead of 0, as done elsewhere in this function.
>
> Fixes: 469981b17a4f ("qed: Add unaligned and packed packet
While the current domain and cpu lists are appropriate for ALL and ANY
coordination types where single structures are kept for the domain and
CPU data, they can be inefficient for NONE and HW coordination types,
where domain information can end up being allocated either for a single
CPU or a small
On Tue, 17 Nov 2020 03:09:56 +0100 Andrew Lunn wrote:
> On Mon, Nov 16, 2020 at 12:01:55PM -0500, Sven Van Asbroeck wrote:
> > From: Sven Van Asbroeck
> >
> > The code in this driver which parses the devicetree to determine
> > the phy/fixed link setup, can be replaced by a single library
> > fun
On Mon, Nov 16, 2020 at 7:04 PM John Hubbard wrote:
>
> Hi,
>
> I just ran into this and it's a real pain to figure out, because even
> with the very latest Fedora 33 on my test machine, which provides clang
> version 11.0.0:
Hi John,
Thanks for the report. The patch was picked up by AKPM and is
On Tue, Nov 17, 2020 at 8:11 AM Colin King wrote:
>
> From: Colin Ian King
>
> There are two spelling mistakes in dev_warn messages. Fix these.
>
> Signed-off-by: Colin Ian King
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 4 ++--
> 1 file changed, 2 inse
On Mon, Nov 16, 2020 at 02:44:56PM -0800, Linus Torvalds wrote:
> On Mon, Nov 16, 2020 at 2:15 PM Linus Torvalds
> wrote:
> >
> > So I've verified that at least on x86-64, this doesn't really make
> > code generation any worse, and I'm ok with the patch from that
> > standpoint.
>
> .. looking cl
Some usb type-c dongle use irq_hpd request to perform device connection
and disconnection. This patch add handling of both connection and
disconnection are based on the state of hpd_state and sink_count.
Changes in V2:
-- add dp_display_handle_port_ststus_changed()
-- fix kernel test robot complai
On Tue, Nov 17, 2020 at 07:34:55PM +0100, Krzysztof Kozlowski wrote:
> > Looking a bit further, I now find that we ended up disabling
> > CONFIG_COMPILE_TEST
> > entirely for arch/um, which is clearly an option that would also work for
> > s390.
>
> Yes, that was the easier solution than to spre
On Tue, Nov 17, 2020 at 10:07 AM Jonathan Cameron
wrote:
>
> On Tue, 17 Nov 2020 08:34:38 -0800
> Ben Widawsky wrote:
>
> > On 20-11-17 15:31:22, Jonathan Cameron wrote:
> > > On Tue, 10 Nov 2020 21:43:54 -0800
> > > Ben Widawsky wrote:
> > >
> > > > Create a function to handle sending a command
On 11/15/20 10:52 AM, Martin Blumenstingl wrote:
> Amlogic Meson G12A (and newer: G12B, SM1) SoCs have a more advanced RX
> delay logic. Instead of fine-tuning the delay in the nanoseconds range
> it now allows tuning in 200 picosecond steps. This support comes with
> new bits in the PRG_ETH1[19:16
On 11/15/20 10:52 AM, Martin Blumenstingl wrote:
> Newer SoCs starting with the Amlogic Meson G12A have more a precise
> RGMII RX delay configuration register. This means more complexity in the
> code. Extract the existing RGMII delay configuration code into a
> separate function to make it easier
On 11/15/20 10:52 AM, Martin Blumenstingl wrote:
> Amlogic Meson G12A, G12B and SM1 SoCs have a more advanced RGMII RX
> delay register which allows picoseconds precision. Parse the new
> "amlogic,rgmii-rx-delay-ps" property or fall back to the old
> "amlogic,rx-delay-ns".
>
> Signed-off-by: Marti
On Tue, Nov 17, 2020 at 10:16:49AM -0800, Eric Biggers wrote:
>
> Here's a suggestion which I think explains it a lot better. It's still
> possible
> I'm misunderstanding something, though, so please check it carefully:
>
> /**
> * generic_set_encrypted_ci_d_ops - helper for setting d_ops for
On Mon, Nov 16, 2020 at 10:21:26AM +0100, Arnd Bergmann wrote:
> On Mon, Nov 16, 2020 at 9:37 AM Geert Uytterhoeven
> wrote:
> > On Mon, Nov 16, 2020 at 9:33 AM Arnd Bergmann wrote:
> > > On Mon, Nov 16, 2020 at 5:33 AM Randy Dunlap
> > > wrote:
> > > > On 11/13/20 3:27 PM, kernel test robot w
On 11/15/20 10:52 AM, Martin Blumenstingl wrote:
> The timing-adjustment clock only has to be enabled when a) there is a
> 2ns RX delay configured using device-tree and b) the phy-mode indicates
> that the RX delay should be enabled.
>
> Only enable the RX delay if both are true, instead of (by ac
On Tue, Nov 17, 2020 at 9:38 AM Enrico Weigelt, metux IT consult
wrote:
>
> The library function memcat_p() is currently used only once.
> (drivers/hwtracing/stm). So, often completely unused.
Any harm in just moving the definition into drivers/hwtracing/stm?
Then we don't need any Kconfig additi
On Fri, 16 Oct 2020 11:56:55 -0700, Sudarshan Rajagopalan wrote:
> V1: The initial patch used the approach to abort at the first instance of
> PMD_SIZE
> allocation failure, unmaps all previously mapped sections using vmemmap_free
> and maps the entire request with vmemmap_populate_basepages to al
On 11/15/20 10:52 AM, Martin Blumenstingl wrote:
> Amlogic Meson G12A, G12B and SM1 SoCs have a more advanced RGMII RX
> delay register which allows picoseconds precision. Deprecate the old
> "amlogic,rx-delay-ns" in favour of a new "amlogic,rgmii-rx-delay-ps"
> property.
>
> For older SoCs the on
On Tue, Nov 17, 2020 at 04:03:14AM +, Daniel Rosenberg wrote:
> diff --git a/include/linux/fscrypt.h b/include/linux/fscrypt.h
> index a8f7a43f031b..df2c66ca370e 100644
> --- a/include/linux/fscrypt.h
> +++ b/include/linux/fscrypt.h
> @@ -741,8 +741,9 @@ static inline int fscrypt_prepare_rename
On Mon, Nov 16, 2020 at 10:21:26AM +0100, Arnd Bergmann wrote:
> > Don't we need the dependencies on HAS_IOMEM for the CONFIG_UML=y
> > case, too?
>
> I would have expected that as well, but I don't see the problem when building
> an arch/um kernel, all I get is
>
> ERROR: modpost: "devm_platform
On Tue, Nov 17, 2020 at 11:52:36AM +0100, Marco Elver wrote:
> On Fri, Nov 13, 2020 at 09:57AM -0800, Paul E. McKenney wrote:
> > On Thu, Nov 12, 2020 at 09:54:06AM -0800, Paul E. McKenney wrote:
> > > On Thu, Nov 12, 2020 at 05:14:39PM +0100, Marco Elver wrote:
> >
> > [ . . . ]
> >
> > > > | [
On Tue, Nov 17, 2020 at 5:26 AM Martin Schiller wrote:
>
> On 2020-11-17 12:32, Xie He wrote:
> >
> > I think for a DCE, it doesn't need to initiate the L2
> > connection on device-up. It just needs to wait for a connection to
> > come. But L3 seems to be still instructing it to initiate the L2
>
On Tue, Nov 17, 2020 at 07:12:07PM +0100, Alexandre Chartre wrote:
> Yes. L1TF/MDS allow some inter cpu-thread attacks which are not mitigated at
> the moment. In particular, this allows a guest VM to attack another guest VM
> or the host kernel running on a sibling cpu-thread. Core Scheduling will
On Mon, 16 Nov 2020 22:15:01 +0100 Antoine Tenart wrote:
> Quoting Julia Lawall (2020-11-16 16:34:44)
> > From: kernel test robot
> >
> > Condition !A || A && B is equivalent to !A || B.
> >
> > Generated by: scripts/coccinelle/misc/excluded_middle.cocci
> >
> > Fixes: b76f0ea01312 ("coccinelle
Hi "Enrico,
I love your patch! Perhaps something to improve:
[auto build test WARNING on gpio/for-next]
[also build test WARNING on joel-aspeed/for-next v5.10-rc4 next-20201117]
[cannot apply to xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And
Hi!
> This is the start of the stable review cycle for the 4.4.244 release.
> There are 64 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
CIP testing did not find any problems here:
https://gitlab.
On 11/17/20 6:07 PM, Borislav Petkov wrote:
On Tue, Nov 17, 2020 at 09:19:01AM +0100, Alexandre Chartre wrote:
We are not reversing PTI, we are extending it.
You're reversing it in the sense that you're mapping more kernel memory
into the user page table than what is mapped now.
PTI remove
The following commit has been merged into the x86/cleanups branch of tip:
Commit-ID: 09a217c10504bcaef911cf2af74e424338efe629
Gitweb:
https://git.kernel.org/tip/09a217c10504bcaef911cf2af74e424338efe629
Author:Hui Su
AuthorDate:Fri, 13 Nov 2020 21:39:43 +08:00
Committer:
The iMX DRM LVDS driver uses Common Clock Framework thus it cannot be
built on platforms without it (e.g. compile test on MIPS with RALINK and
SOC_RT305X):
/usr/bin/mips-linux-gnu-ld: drivers/gpu/drm/imx/imx-ldb.o: in function
`imx_ldb_encoder_disable':
imx-ldb.c:(.text+0x400): undefined
On Mon, Nov 16, 2020 at 10:35 AM Mimi Zohar wrote:
>
> We need to differentiate between signed files, which by definition are
> immutable, and those that are mutable. Appending to a mutable file,
> for example, would result in the file hash not being updated.
> Subsequent reads would fail.
Why w
On 11/17/20 10:38 AM, Matthew Wilcox wrote:
On Tue, Nov 17, 2020 at 09:34:24AM -0700, Shuah Khan wrote:
seqnum_inc() should just return the new value -- seqnum_inc_return is
too verbose. And do we not need a seqnum_add()?
I had the patch series with seqnum_inc() all ready to go and then
revis
On 11/17/20 10:38 AM, Matthew Wilcox wrote:
On Tue, Nov 17, 2020 at 09:34:24AM -0700, Shuah Khan wrote:
seqnum_inc() should just return the new value -- seqnum_inc_return is
too verbose. And do we not need a seqnum_add()?
I had the patch series with seqnum_inc() all ready to go and then
revis
Hi Jyoti,
just some initial feedback down below.
I'll get back to this series again next days.
On Fri, Nov 13, 2020 at 05:06:11PM +, Jyoti Bhayana wrote:
> This change provides ARM SCMI Protocol based IIO device.
> This driver provides support for Accelerometer and Gyroscope using
> new SCMI
COMMON_CLK is a user-selectable option with its own dependencies. The
most important dependency is !HAVE_LEGACY_CLK. User-selectable drivers
should not select COMMON_CLK because they will create a dependency cycle
and build failures. For example on MIPS a configuration with COMMON_CLK
(selected
Hi Linus,
please pull some small s390 updates for 5.10-rc5.
Thanks,
Heiko
The following changes since commit f8394f232b1eab649ce2df5c5f15b0e528c92091:
Linux 5.10-rc3 (2020-11-08 16:10:16 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/s390/linu
On Sun, Nov 15, 2020 at 11:05:48AM +0800, Hillf Danton wrote:
> On Fri, 13 Nov 2020 00:01:21 +0200
> > From: Sean Christopherson
> >
> > Background
> > ==
> >
> > 1. SGX enclave pages are populated with data by copying from normal memory
> >via ioctl() (SGX_IOC_ENCLAVE_ADD_PAGES), wh
This fixes the following warning:
`drivers/pwm/core.c:1341: WARNING: Symbolic permissions 'S_IRUGO' are
not preferred. Consider using octal permissions '0444'.`
generated by the following script:
`./scripts/checkpatch.pl --file --terse drivers/pwm/core.c`
On Tue, 17 Nov 2020 at 23:42, Lee Jone
From: Hyesoo Yu
Document devicetree binding for chunk heap on dma heap framework
Signed-off-by: Hyesoo Yu
Signed-off-by: Minchan Kim
---
.../bindings/dma-buf/chunk_heap.yaml | 52 +++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindin
From: Hyesoo Yu
The heaps could be added as module, so some functions should
be exported to register dma-heaps. And dma-heap of module can use
cma area to allocate and free. However the function related cma
is not exported now. Let's export them for next patches.
Signed-off-by: Hyesoo Yu
Signed
From: Hyesoo Yu
This patch supports chunk heap that allocates the buffers that are
made up of a list of fixed size chunks taken from a CMA.
The chunk heap doesn't use heap-helper although it can remove
duplicated code since heap-helper is under deprecated process.[1]
[1] https://lore.kernel.org
There is a need for special HW to require bulk allocation of
high-order pages. For example, 4800 * order-4 pages, which
would be minimum, sometimes, it requires more.
To meet the requirement, a option reserves 300M CMA area and
requests the whole 300M contiguous memory. However, it doesn't
work if
Hi Utkarsh,
On Fri, Nov 13, 2020 at 12:25:01PM -0800, Utkarsh Patel wrote:
> Configure Thunderbolt3/USB4 cable generation value by filing Thunderbolt 3
> cable discover mode VDO to support rounded and non-rounded Thunderbolt3/
> USB4 cables.
> While we are here use Thunderbolt 3 cable discover mod
This patchset introduces a new dma heap, chunk heap that makes it
easy to perform the bulk allocation of high order pages.
It has been created to help optimize the 4K/8K HDR video playback
with secure DRM HW to protect contents on memory. The HW needs
physically contiguous memory chunks up to sever
On Tue, Nov 17, 2020 at 04:03:13AM +, Daniel Rosenberg wrote:
>
> Currently the casefolding dentry operation are always set if the
> filesystem defines an encoding because the features is toggleable on
> empty directories. Since we don't know what set of functions we'll
> eventually need, and
Move the initialization of kvm_nvhe_init_params in a dedicated function
that is run early, and only once during KVM init, rather than every time
the KVM vectors are set and reset.
This also opens the opportunity for the hypervisor to change the init
structs during boot, hence simplifying the repla
Move the registers relevant to host stage 2 enablement to
kvm_nvhe_init_params to prepare the ground for enabling it in later
patches.
Signed-off-by: Quentin Perret
---
arch/arm64/include/asm/kvm_asm.h | 3 +++
arch/arm64/kernel/asm-offsets.c| 3 +++
arch/arm64/kvm/arm.c | 5
> On Tue, Nov 17, 2020 at 12:20:36AM +0200, Viorel Suman (OSS) wrote:
>
> > static void ak4458_power_off(struct ak4458_priv *ak4458) {
> > - if (ak4458->reset_gpiod) {
> > - gpiod_set_value_cansleep(ak4458->reset_gpiod, 0);
> > - usleep_range(1000, 2000);
> > + if (ak4458
When KVM runs in protected nVHE mode, make use of a stage 2 page-table
to give the hypervisor some control over the host memory accesses. At
the moment all memory aborts from the host will be instantly idmapped
RWX at stage 2 in a lazy fashion. Later patches will make use of that
infrastructure to
Extend the memory pool allocated for the hypervisor to include enough
pages to map all of memory at page granularity for the host stage 2.
While at it, also reserve some memory for device mappings.
Signed-off-by: Quentin Perret
---
arch/arm64/kvm/hyp/include/nvhe/mm.h | 36 ++
The hypervisor will need the list of memblock regions sorted by
increasing start address to make look-ups more efficient. Make the
host do the hard work early while it is still trusted to avoid the need
for a sorting library at EL2.
Signed-off-by: Quentin Perret
---
arch/arm64/include/asm/kvm_ho
Refactor __populate_fault_info() to introduce __get_fault_info() which
will be used once the host is wrapped in a stage 2.
Signed-off-by: Quentin Perret
---
arch/arm64/kvm/hyp/include/hyp/switch.h | 36 +++--
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/arc
The current stage2 page-table allocator uses a memcache to get
pre-allocated pages when it needs any. To allow re-using this code at
EL2 which uses a concept of memory pools, make the memcache argument to
kvm_pgtable_stage2_map() anonymous. and let the mm_ops zalloc_page()
callbacks use it the way
Refactor __load_guest_stage2() to introduce __load_stage2() which will
be re-used when loading the host stage 2.
Signed-off-by: Quentin Perret
---
arch/arm64/include/asm/kvm_mmu.h | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch
In order to re-use some of the stage 2 setup at EL2, factor parts of
kvm_arm_setup_stage2() out into static inline functions.
No functional change intended.
Signed-off-by: Quentin Perret
---
arch/arm64/include/asm/kvm_mmu.h | 48
arch/arm64/kvm/reset.c
In order to make use of the stage 2 pgtable code for the host stage 2,
use struct kvm_arch in lieu of struct kvm as the host will have the
former but not the latter.
Signed-off-by: Quentin Perret
---
arch/arm64/include/asm/kvm_pgtable.h | 5 +++--
arch/arm64/kvm/hyp/pgtable.c | 6 +++---
Previous commits have introduced infrastructure at EL2 to enable the Hyp
code to manage its own memory, and more specifically its stage 1 page
tables. However, this was preliminary work, and none of it is currently
in use.
Put all of this together by elevating the hyp mappings creation at EL2
when
In order to make use of the stage 2 pgtable code for the host stage 2,
change kvm_s2_mmu to use a kvm_arch pointer in lieu of the kvm pointer,
as the host will have the former but not the latter.
Signed-off-by: Quentin Perret
---
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/include/asm/k
When memory protection is enabled, the Hyp code needs the ability to
create and manage its own page-table. To do so, introduce a new set of
hypercalls to initialize Hyp memory protection.
During the init hcall, the hypervisor runs with the host-provided
page-table and uses the trivial early page a
In order to re-map the guest vectors at EL2 when pKVM is enabled,
refactor __kvm_vector_slot2idx() and kvm_init_vector_slot() to move all
the address calculation logic in a static inline function.
Signed-off-by: Quentin Perret
---
arch/arm64/include/asm/kvm_mmu.h | 8
arch/arm64/kvm/arm
Introduce early_init_dt_add_memory_hyp() to allow KVM to conserve a copy
of the memory regions parsed from DT. This will be needed in the context
of the protected nVHE feature of KVM/arm64 where the code running at EL2
will be cleanly separated from the host kernel during boot, and will
need its ow
When memory protection is enabled, the hyp code will require a basic
form of memory management in order to allocate and free memory pages at
EL2. This is needed for various use-cases, including the creation of hyp
mappings or the allocation of stage 2 page tables.
To address these use-case, introd
Introduce the infrastructure in KVM enabling to copy CPU feature
registers into EL2-owned data-structures, to allow reading sanitised
values directly at EL2 in nVHE.
Given that only a subset of these features are being read by the
hypervisor, the ones that need to be copied are to be listed under
In order to use the kernel list library at EL2, introduce stubs for the
CONFIG_DEBUG_LIST out-of-lines calls.
Signed-off-by: Quentin Perret
---
arch/arm64/kvm/hyp/nvhe/Makefile | 2 +-
arch/arm64/kvm/hyp/nvhe/stub.c | 22 ++
2 files changed, 23 insertions(+), 1 deletion(-)
In order to allow the usage of code shared by the host and the hyp in
static inline library function, allow the usage of kvm_nvhe_sym() at el2
by defaulting to the raw symbol name.
Signed-off-by: Quentin Perret
---
arch/arm64/include/asm/hyp_image.h | 4
arch/arm64/include/asm/kvm_asm.h |
With nVHE, the host currently creates all s1 hypervisor mappings at EL1
during boot, installs them at EL2, and extends them as required (e.g.
when creating a new VM). But in a world where the host is no longer
trusted, it cannot have full control over the code mapped in the
hypervisor.
In preparat
Currently, the KVM page-table allocator uses a mix of put_page() and
free_page() calls depending on the context even though page-allocation
is always achieved using variants of __get_free_page().
Make the code consitent by using put_page() throughout, and reduce the
memory management API surface u
kvm_call_hyp() has some logic to issue a function call or a hypercall
depending the EL at which the kernel is running. However, all the code
compiled under __KVM_NVHE_HYPERVISOR__ is guaranteed to run only at EL2,
and in this case a simple function call is needed.
Add ifdefery to kvm_host.h to sym
Currently, the hyp code cannot make full use of a bss, as the kernel
section is mapped read-only.
While this mapping could simply be changed to read-write, it would
intermingle even more the hyp and kernel state than they currently are.
Instead, introduce a __hyp_bss section, that uses reserved pa
In preparation for enabling the creation of page-tables at EL2, factor
all memory allocation out of the page-table code, hence making it
re-usable with any compatible memory allocator.
No functional changes intended.
Signed-off-by: Quentin Perret
---
arch/arm64/include/asm/kvm_pgtable.h | 32 ++
On Fri, Nov 13, 2020 at 10:25:43AM +, Mel Gorman wrote:
> On Fri, Nov 13, 2020 at 12:01:21AM +0200, Jarkko Sakkinen wrote:
> > From: Sean Christopherson
> >
> > Background
> > ==
> >
> > 1. SGX enclave pages are populated with data by copying from normal memory
> >via ioctl() (SG
From: Will Deacon
We will soon need to synchronise multiple CPUs in the hyp text at EL2.
The qspinlock-based locking used by the host is overkill for this purpose
and requires a working "percpu" implementation for the MCS nodes.
Implement a simple ticket locking scheme based heavily on the code
From: Will Deacon
clear_page() and copy_page() are suitable for use outside of the kernel
address space, so annotate them as position-independent code.
Signed-off-by: Will Deacon
---
arch/arm64/lib/clear_page.S | 4 ++--
arch/arm64/lib/copy_page.S | 4 ++--
2 files changed, 4 insertions(+), 4
Hi all,
This RFC series provides the infrastructure enabling to wrap the host
kernel with a stage 2 when running KVM in nVHE. This can be useful for
several use-cases, but the primary motivation is to (eventually) be able
to protect guest memory from the host kernel. More details about the
overall
From: Will Deacon
Pull clear_page(), copy_page(), memcpy() and memset() into the nVHE hyp
code and ensure that we always execute the '__pi_' entry point on the
offchance that it changes in future.
[ qperret: Commit title nits ]
Signed-off-by: Will Deacon
Signed-off-by: Quentin Perret
---
arc
On Sat, Nov 14, 2020 at 05:32:56PM +0800, Hillf Danton wrote:
> On Fri, 13 Nov 2020 00:01:20 +0200 Jarkko Sakkinen wrote:
> >
> > The previous patch initialized a simple SGX page allocator. Add functions
> > for runtime allocation and free.
> >
> > This allocator and its algorithms are as simple
On Tue, 17 Nov 2020, Lee Jones wrote:
> On Tue, 17 Nov 2020, Daniel Vetter wrote:
>
> > On Mon, Nov 16, 2020 at 05:40:33PM +, Lee Jones wrote:
> > > Fixes the following W=1 kernel build warning(s):
> > >
> > > drivers/gpu/drm/drm_dp_mst_topology.c: In function
> > > ‘drm_dp_send_query_stre
On Sat, Nov 14, 2020 at 05:07:08PM +0800, Hillf Danton wrote:
> On Fri, 13 Nov 2020 00:01:17 +0200
> >
> > From: Sean Christopherson
> >
> > The x86 architecture has a set of page fault error codes. These indicate
> > things like whether the fault occurred from a write, or whether it
> > origi
On Tue, 17 Nov 2020, Daniel Vetter wrote:
> On Mon, Nov 16, 2020 at 05:40:33PM +, Lee Jones wrote:
> > Fixes the following W=1 kernel build warning(s):
> >
> > drivers/gpu/drm/drm_dp_mst_topology.c: In function
> > ‘drm_dp_send_query_stream_enc_status’:
> > drivers/gpu/drm/drm_dp_mst_topol
On Tue, Nov 17, 2020 at 1:00 PM Rafael J. Wysocki
wrote:
>
> On 11/16/2020 10:05 PM, Steven Rostedt wrote:
> > On Mon, 16 Nov 2020 12:55:29 -0800
> > Peiyong Lin wrote:
> >
> >> Hi there,
> >>
> >> May I ask whether the merge window has passed? If so is it possible to
> >> ask for a review?
> > T
On Tue, 17 Nov 2020, Soham Biswas wrote:
> Fixed Warning.
Which warning does this fix?
> Replaced symbolic permission 'S_IRUGO' with octal permission '0444'.
This is semantically equivalent.
Not sure what and/or how this fixes anything.
> Signed-off-by: Soham Biswas
> ---
> drivers/pwm/core
On 11/17/20 5:55 PM, Borislav Petkov wrote:
On Tue, Nov 17, 2020 at 08:56:23AM +0100, Alexandre Chartre wrote:
The main goal of ASI is to provide KVM address space isolation to
mitigate guest-to-host speculative attacks like L1TF or MDS.
Because the current L1TF and MDS mitigations are lacki
On 11/17/20 11:57 AM, Eric Biggers wrote:
On Tue, Nov 17, 2020 at 08:47:08AM -0500, Thara Gopinath wrote:
Qualcomm crypto engine supports hardware accelerated algorithms for
encryption and authentication. Enable support for aes,des,3des encryption
algorithms and sha1,sha256, hmac(sha1),hmac(s
On Tue, 17 Nov 2020 08:34:38 -0800
Ben Widawsky wrote:
> On 20-11-17 15:31:22, Jonathan Cameron wrote:
> > On Tue, 10 Nov 2020 21:43:54 -0800
> > Ben Widawsky wrote:
> >
> > > Create a function to handle sending a command, optionally with a
> > > payload, to the memory device, polling on a re
On Tue, 17 Nov 2020 11:07:34 +0800 Zhang Changzhong wrote:
> Fix to return a negative error code from the error handling
> case instead of 0, as done elsewhere in this function.
>
> Fixes: 17ff2c794f39 ("rsi: reset device changes for 9116")
> Reported-by: Hulk Robot
> Signed-off-by: Zhang Changzh
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