On Tue, 17 Nov 2020 17:08:24 +0900 Bongsu Jeon wrote:
> max_payload is unused.
>
> Reviewed-by: Krzysztof Kozlowski
> Signed-off-by: Bongsu Jeon
Applied all 3 to net-next, thanks!
Rob Herring 於 2020年11月19日 週四 上午5:25寫道：
>
> On Wed, 18 Nov 2020 18:47:41 +0800, Gene Chen wrote:
> > From: Gene Chen
> >
> > Add bindings document for LED support on MT6360 PMIC
> >
> > Signed-off-by: Gene Chen
> > ---
> > .../devicetree/bindings/leds/leds-mt6360.yaml | 164
> >
Uladzislau Rezki writes:
> On Wed, Nov 18, 2020 at 10:44:13AM +0800, huang ying wrote:
>> On Tue, Nov 17, 2020 at 9:04 PM Uladzislau Rezki wrote:
>> >
>> > On Tue, Nov 17, 2020 at 10:37:34AM +0800, huang ying wrote:
>> > > On Tue, Nov 17, 2020 at 6:00 AM Uladzislau Rezki (Sony)
>> > > wrote:
Use the common INIT_DATA_SECTION rule for the linker script in an effort
to regularize the linker script.
Signed-off-by: Youling Tang
---
arch/microblaze/kernel/vmlinux.lds.S | 24 +---
1 file changed, 1 insertion(+), 23 deletions(-)
diff --git
On Wed, 18 Nov 2020 11:04:37 -0500
Steven Rostedt wrote:
> On Thu, 19 Nov 2020 00:35:35 +0900
> Masami Hiramatsu wrote:
>
> > Fix to check the write(2) failure including partial write
> > correctly and try to rollback the partial write, because
> > if there is no BOOTCONFIG_MAGIC string, we
On Mon, 16 Nov 2020 12:00:23 -0600, Dr. Greg wrote:
On Thu, Nov 12, 2020 at 02:41:00PM -0800, Andy Lutomirski wrote:
Good morning, I hope the week is starting well for everyone.
On Thu, Nov 12, 2020 at 1:31 PM Dave Hansen
wrote:
>
> On 11/12/20 12:58 PM, Dr. Greg wrote:
> > @@ -270,11
On Wed, 18 Nov 2020 16:33:10 +0100 Andrea Parri (Microsoft) wrote:
> Lack of validation could lead to out-of-bound reads and information
> leaks (cf. usage of nvdev->chan_table[]). Check that the number of
> allocated sub-channels fits into the expected range.
>
> Suggested-by: Saruhan Karademir
On 2020/11/19 2:07, Peter Zijlstra wrote:
On Thu, Nov 19, 2020 at 12:15:09AM +0800, Like Xu wrote:
ISTR there was lots of fail trying to virtualize it earlier. What's
changed? There's 0 clues here.
Ah, now we have EPT-friendly PEBS facilities supported since Ice Lake
which makes guest PEBS
Hi Vincent,
On 2020/11/18 21:36, Vincent Guittot wrote:
> On Wed, 18 Nov 2020 at 04:48, Aubrey Li wrote:
>>
>> From: Aubrey Li
>>
>> Add idle cpumask to track idle cpus in sched domain. When a CPU
>> enters idle, if the idle driver indicates to stop tick, this CPU
>> is set in the idle cpumask
On Wed, Nov 18, 2020 at 03:42:53PM -0800, Tao Ren wrote:
> On Thu, Nov 19, 2020 at 12:27:19AM +0100, Andrew Lunn wrote:
> > On Wed, Nov 18, 2020 at 03:09:27PM -0800, rentao.b...@gmail.com wrote:
> > > From: Tao Ren
> > >
> > > The patch series adds hardware monitoring driver for the Maxim MAX127
Extend the MAX10 BMC Secure Update driver to include
a function that returns 64 bits of additional HW specific
data for errors that require additional information.
This callback function enables the hw_errinfo sysfs
node in the Intel Security Manager class driver.
Signed-off-by: Russ Weight
---
Create a platform driver that can be invoked as a sub
driver for the Intel MAX10 BMC in order to support
secure updates. This sub-driver will invoke an
instance of the FPGA Security Manager class driver
in order to expose sysfs interfaces for managing and
monitoring secure updates to FPGA and BMC
Extend the MAX10 BMC Secure Update driver to provide a
sysfs file to expose the flash update count for the FPGA
user image.
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v6:
- Changed flash_count_show() parameter list to achieve
reverse-christmas tree format.
- Added WARN_ON()
Extend the MAX10 BMC Secure Update driver to provide sysfs
files to expose the canceled code signing key (CSK) bit
vectors. These use the standard bitmap list format
(e.g. 1,2-6,9).
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
---
v6:
- Added WARN_ON() call for (size / stride) to ensure
Extend the MAX10 BMC Secure Update driver to include
the functions that enable secure updates of BMC images,
FPGA images, etc.
Signed-off-by: Russ Weight
---
v6:
- Changed (size / stride) calculation to ((size + stride - 1) / stride)
to ensure that the proper count is passed to
Add macros and definitions required by the MAX10 BMC
Secure Update driver.
Signed-off-by: Russ Weight
Acked-by: Lee Jones
---
v6:
- No change
v5:
- Renamed USER_FLASH_COUNT to STAGING_FLASH_COUNT
v4:
- No change
v3:
- Changed "MAX10 BMC Secure Engine driver" to "MAX10 BMC Secure
The Intel MAX10 BMC Secure Update driver instantiates the FPGA
Security Manager class driver and provides the callback functions
required to support secure updates on Intel n3000 PAC devices.
This driver is implemented as a sub-driver of the Intel MAX10 BMC
mfd driver. Future instances of the
On Wed, Nov 18, 2020 at 09:26:34AM +0800, Boqun Feng wrote:
Hi Sasha,
I don't think this commit should be picked by stable, since the problem
it fixes is caused by commit f611e8cf98ec ("lockdep: Take read/write
status in consideration when generate chainkey"), which just got merged
in the merge
Hello, Hillf danton.
On Wed, Nov 18, 2020 at 05:00:13PM +0800, Hillf Danton wrote:
> On Tue, 17 Nov 2020 10:19:34 -0800 Minchan Kim wrote:
> +
> +static int chunk_heap_mmap(struct dma_buf *dmabuf, struct vm_area_struct
> *vma)
> +{
> + struct chunk_heap_buffer *buffer = dmabuf->priv;
> +
On Tue, Nov 17, 2020 at 07:00:54PM -0800, John Stultz wrote:
> On Tue, Nov 17, 2020 at 10:19 AM Minchan Kim wrote:
> >
> > From: Hyesoo Yu
> >
> > Document devicetree binding for chunk heap on dma heap framework
> >
> > Signed-off-by: Hyesoo Yu
> > Signed-off-by: Minchan Kim
> > ---
> >
On Thu, 19 Nov 2020 at 08:25, Dave Airlie wrote:
>
> On Thu, 19 Nov 2020 at 08:15, Daniel Vetter wrote:
> >
> > On Wed, Nov 18, 2020 at 11:01 PM David Laight
> > wrote:
> > >
> > > From: Thomas Zimmermann
> > > > Sent: 18 November 2020 19:37
> > > >
> > > > Hi
> > > >
> > > > Am 18.11.20 um
() for CONFIG_M68K
date: 3 months ago
config: m68k-randconfig-r013-20201118 (attached as .config)
compiler: m68k-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
On 11/18/20 4:38 PM, Atish Patra wrote:
> diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
> index 8d7001712062..c5956c8845cc 100644
> --- a/drivers/base/Kconfig
> +++ b/drivers/base/Kconfig
> @@ -210,4 +210,10 @@ config GENERIC_ARCH_TOPOLOGY
> appropriate scaling, sysfs interface
On 2020/11/18 20:06, Valentin Schneider wrote:
>
> On 16/11/20 20:04, Aubrey Li wrote:
>> From: Aubrey Li
>>
>> Add idle cpumask to track idle cpus in sched domain. When a CPU
>> enters idle, if the idle driver indicates to stop tick, this CPU
>> is set in the idle cpumask to be a wakeup target.
Use min_t to replace min, min_t is a bit fast because min use
twice typeof.
This patch also fix check_patch.pl warning:
WARNING: min() should probably be min_t(unsigned long, num_pages,
VMW_PPN_PER_REMAP)
+unsigned long nr = min(num_pages, (unsigned long)
VMW_PPN_PER_REMAP);
Signed-off-by:
if of_find_device_by_node() succeed, pinctrl_falcon_probe() doesn't have
a corresponding put_device(). Thus add put_device() to fix the exception
handling for this function implementation.
Fixes: e316cb2b16bb ("OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC")
Signed-off-by: Yu Kuai
---
The TI K3 J7200 SoCs have two dual-core Arm R5F clusters/subsystems,
with 2 R5F cores each, one in each of the MCU and MAIN voltage domains.
These clusters are a revised IP version compared to those present on
J721E SoCs. Update the K3 R5F remoteproc bindings with the compatible
info relevant to
Hi,
On 11/18/20 3:24 PM, Saeed Mirzamohammadi wrote:
> This adds crashkernel=auto feature to configure reserved memory for
> vmcore creation to both x86 and ARM platforms based on the total memory
> size.
>
> Cc: sta...@vger.kernel.org
why?
> Signed-off-by: John Donnelly
> Signed-off-by:
The J7200 SoCs have a revised R5FSS IP that adds a unique feature w.r.t
TCM sizing. Each R5F core in a cluster typically has 32 KB each of ATCM
and BTCM, with only the Core0 TCMs usable in LockStep mode. This revised
IP however doubles the total available TCM in LockStep mode by making the
Core1
The K3 J7200 SoC family has a revised R5F sub-system and contains a
subset of the R5F clusters present on J721E SoCs. The K3 J7200 SoCs
only have two dual-core Arm R5F clusters/subsystems with 2 R5F cores
each. One cluster is present within the MCU voltage domain (MCU_R5FSS0),
while the other is
Hi All,
The following series enhances the K3 R5F remoteproc driver to add support
for the R5F clusters on the newer TI K3 J7200 SoC family. The J7200 SoCs
have 2 R5FSS clusters, and both clusters are capable of supporting either
the LockStep or Split-modes like on the existing AM65x and J721E
On Wed, Nov 18, 2020 at 03:42:53PM -0800, Tao Ren wrote:
> On Thu, Nov 19, 2020 at 12:27:19AM +0100, Andrew Lunn wrote:
> > On Wed, Nov 18, 2020 at 03:09:27PM -0800, rentao.b...@gmail.com wrote:
> > > From: Tao Ren
> > >
> > > The patch series adds hardware monitoring driver for the Maxim MAX127
On Tue, Nov 17, 2020 at 06:40:22PM +0900, Kuniyuki Iwashima wrote:
> This patch makes it possible to select a new listener for socket migration
> by eBPF.
>
> The noteworthy point is that we select a listening socket in
> reuseport_detach_sock() and reuseport_select_sock(), but we do not have
>
When returning results to userspace, do_sys_poll repeatedly calls
put_user() - once per fd that it's watching.
This means that on architectures that support some form of
kernel-to-userspace access protection, we end up enabling and disabling
access once for each file descripter we're watching.
This is a preparatory patch for unifying numa implementation between
ARM64 & RISC-V. As the numa implementation will be moved to generic
code, rename the arm64 related functions to a generic one.
Signed-off-by: Atish Patra
Acked-by: Catalin Marinas
---
arch/arm64/include/asm/numa.h | 4 ++--
Currently, we perform some memory init functions in paging init. But,
that will be an issue for NUMA support where DT needs to be flattened
before numa initialization and memblock_present can only be called
after numa initialization.
Move memory initialization related functions to a separate
Use the generic numa implementation to add NUMA support for RISC-V.
This is based on Greentime's patch[1] but modified to use generic NUMA
implementation and few more fixes.
[1] https://lkml.org/lkml/2020/1/10/233
Co-developed-by: Greentime Hu
Signed-off-by: Greentime Hu
Signed-off-by: Atish
ARM64 numa implementation is generic enough that RISC-V can reuse that
implementation with very minor cosmetic changes. This will help both
ARM64 and RISC-V in terms of maintanace and feature improvement
Move the numa implementation code to common directory so that both ISAs
can reuse this. This
From: Greentime Hu
These two functions are used to distinguish between PROT_NONENUMA
protections and hinting fault protections.
Signed-off-by: Greentime Hu
Reviewed-by: Anup Patel
Reviewed-by: Palmer Dabbelt
---
arch/riscv/include/asm/pgtable.h | 20
1 file changed, 20
This series attempts to move the ARM64 numa implementation to common
code so that RISC-V can leverage that as well instead of reimplementing
it again.
RISC-V specific bits are based on initial work done by Greentime Hu [1] but
modified to reuse the common implementation to avoid duplication.
[1]
On Thu, Nov 19, 2020 at 07:50:15AM +0800, Tao Zhou wrote:
> On Wed, Nov 18, 2020 at 07:56:38PM -0300, Guilherme G. Piccoli wrote:
> > Hi Vincent (and all CCed), I'm sorry to ping about such "old" patch, but
> > we experienced a similar condition to what this patch addresses; it's an
> > older
The implementation expects `lscpu` to have a "CPU: " line, for example:
CPU(s): 8
But some local language settings may advocate for their own version:
Processeur(s) : 8
As a result the function may return an empty string and rcutorture would
dump the following
On Sun, 15 Nov 2020 11:13:52 +0100
Thorsten Leemhuis wrote:
> > So I've not had a chance to try to read through the whole thing again,
> > will try to do so in the near future.
>
> Great, thx, looking forward to it.
OK, I have made a *quick* pass through the whole thing and sent a small
Hi,
The patch LGTM there is small nit, though.
> +++ b/drivers/net/wireless/ath/ath10k/wmi.c
> @@ -5751,8 +5751,13 @@ void ath10k_wmi_event_service_available(struct ath10k
> *ar, struct sk_buff *skb)
> ret);
> }
>
> - ath10k_wmi_map_svc_ext(ar,
The PCI subsystem does not currently save and restore the configuration
space for the Precision Time Measurement (PTM) PCIe extended capability
leading to the feature returning disabled on S3 resume. This has been
observed on Intel Coffee Lake desktops. Add save/restore of the PTM control
On Intel client platforms that support suspend-to-idle, like Ice Lake,
root ports that have Precision Time Management (PTM) enabled can prevent
the port from being fully power gated, causing higher power consumption
while suspended. To prevent this, after saving the PTM control register,
disable
On Thu, 12 Nov 2020 18:58:58 +0100
Thorsten Leemhuis wrote:
> That's also why this commit removes scripts/ver_linux as well: the
> details it collects are only needed in some situations. And some (a
> lot?) distributions do not ship it anyway; a better, more modern script
> would likely resist
Hi Clemens, thank you so much for this contribution.
I no longer have access to this chip, so I cannot test
the changes.
Some friendly/constructive feedback below.
On Wed, Nov 18, 2020 at 12:44 PM Clemens Gruber
wrote:
>
> This switch to the atomic API goes hand in hand with a few fixes to
>
On Wed, Nov 18, 2020 at 11:55 AM Suren Baghdasaryan wrote:
>
> On Wed, Nov 18, 2020 at 11:51 AM Suren Baghdasaryan wrote:
> >
> > On Wed, Nov 18, 2020 at 11:32 AM Michal Hocko wrote:
> > >
> > > On Wed 18-11-20 11:22:21, Suren Baghdasaryan wrote:
> > > > On Wed, Nov 18, 2020 at 11:10 AM Michal
On Tue, Nov 17, 2020 at 06:40:21PM +0900, Kuniyuki Iwashima wrote:
> We will call sock_reuseport.prog for socket migration in the next commit,
> so the eBPF program has to know which listener is closing in order to
> select the new listener.
>
> Currently, we can get a unique ID for each listener
Hi Sia,
> Subject: [PATCH v4 08/15] dmaengine: dw-axi-dmac: Support
> of_dma_controller_register()
>
> Add support for of_dma_controller_register() so that DMA clients
> can pass in device handshake number to the AxiDMA driver.
>
> DMA clients shall code the device handshake number in the
Hi all,
After merging the pm tree, today's linux-next build (x86_64 allmodconfig)
produced this warning:
WARNING: modpost: missing MODULE_LICENSE() in kernel/resource_kunit.o
Introduced by commit
5df38ca6afec ("resource: Add test cases for new resource API")
--
Cheers,
Stephen Rothwell
On Thu, 12 Nov 2020 18:58:45 +0100
Thorsten Leemhuis wrote:
> +If your kernel is tainted, study
> +:ref:`Documentation/admin-guide/tainted-kernels.rst ` to find
> +out why. Try to eliminate the reason. Often it's caused by one these three
> +things:
One little detail that jumped at me just now:
Hi Sia,
> Subject: [PATCH v4 13/15] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA
> handshake
>
> Add support for Intel KeemBay AxiDMA device handshake programming.
> Device handshake number passed in to the AxiDMA shall be written to
> the Intel KeemBay AxiDMA hardware handshake registers
Hello:
This series was applied to netdev/net-next.git (refs/heads/master):
On Mon, 16 Nov 2020 17:37:54 -0600 you wrote:
> This series consists of cleanup patches, almost entirely related to
> the definitions for IPA registers. Some comments are updated or
> added to provide better information
Hi Sia,
> Subject: [PATCH v4 11/15] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA
> register fields
>
> Add support for Intel KeemBay DMA registers. These registers are required
> to run data transfer between device to memory and memory to device on Intel
> KeemBay SoC.
>
> Reviewed-by: Andy
> -Original Message-
> From: Ard Biesheuvel [mailto:a...@kernel.org]
> Sent: Thursday, November 19, 2020 11:38 AM
> To: Song Bao Hua (Barry Song)
> Cc: Will Deacon ; Mike Rapoport ;
> anshuman.khand...@arm.com; catalin.mari...@arm.com; Linuxarm
> ; linux-kernel@vger.kernel.org;
>
On Wed Nov 18, 2020 at 5:37 PM -03, Jonathan Corbet wrote:
>
> On Tue, 17 Nov 2020 02:12:01 +
> Nícolas F. R. A. Prado wrote:
>
> > Sphinx 3.1 introduced namespaces for C cross-references. With this,
> > each C domain type/function declaration is put inside the namespace that
> > was active
On Wed, Nov 18, 2020 at 07:56:38PM -0300, Guilherme G. Piccoli wrote:
> Hi Vincent (and all CCed), I'm sorry to ping about such "old" patch, but
> we experienced a similar condition to what this patch addresses; it's an
> older kernel (4.15.x) but when suggesting the users to move to an
> updated
On 11/13/20 2:59 AM, Muchun Song wrote:
> diff --git a/mm/hugetlb_vmemmap.c b/mm/hugetlb_vmemmap.c
> new file mode 100644
> index ..a6c9948302e2
> --- /dev/null
> +++ b/mm/hugetlb_vmemmap.c
> @@ -0,0 +1,108 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Free some vmemmap pages
On Tue, Nov 17, 2020 at 06:40:18PM +0900, Kuniyuki Iwashima wrote:
> This patch lets reuseport_detach_sock() return a pointer of struct sock,
> which is used only by inet_unhash(). If it is not NULL,
> inet_csk_reqsk_queue_migrate() migrates TCP_ESTABLISHED/TCP_SYN_RECV
> sockets from the closing
On Wed, Nov 18, 2020 at 2:07 PM Sami Tolvanen wrote:
>
> This change adds build system support for Clang's Link Time
> Optimization (LTO). With -flto, instead of ELF object files, Clang
> produces LLVM bitcode, which is compiled into native code at link
> time, allowing the final binary to be
Add request/release and related clock gating functions to AI engine
driver:
* scanning when the partition is being requested to know which tiles
are in use.
* check if a tile is gated or not
* tiles requesting and releasing ioctl so that user application can
enable/disable tiles at runtime.
Create AI engine device/partition hierarchical structure.
Each AI engine device can have multiple logical partitions(groups of AI
engine tiles). Each partition is column based and has its own node ID
in the system. AI engine device driver manages its partitions.
Applications can access AI engine
There is no concern to have userspace to directly access AI engine
program and data memories. It will be much faster to directly copy
data to and from these memories from userspace.
We choose to use DMA buf for the data and program memory because of the
DMA buf features. DMA buf can share the DMA
Add operation to set SHIM DMA buffer descriptor.
The following operations are added to set the buffer descriptors:
* attach DMA buffer which enables AI engine device to access the DMA
buffer memory
* detach DMA buffer which disables AI engine device to access the DMA
buffer memory
* set DMA
From: Izhar Ameer Shaikh
Latching of AIE NPI Interrupts is present in Versal ES1 Silicon Rev,
however it has been removed from ES2 rev.
As a result on ES1, in order to use the interrupt, a client needs to
request PMC to clear/ack the interrupt.
Provide an EEMI IOCTL to serve the same purpose.
From: Nishad Saraf
AI engine errors events can be routed to generate interrupt. The
errors events routing will be done during AI engine configuration.
At runtime, Linux kernel AI engine driver monitors the interrupt and
backtracks errors events.
As error events from 400 AIE tiles and 50 shim
When AI engine partition is released, that is if no one is using the AI
engine partition, by default, it will cleanup the partition by doing the
following:
* reset the columns
* reset the SHIMs
* clear data and program memory
* gate all the tiles
If user doesn't want the partition is reset when
From: Nishad Saraf
Platform management services like device control, resets, power
management, etc. are provided by Platform, Loader and Manager(PLM)
through firmware driver APIs. For requesting some of these services,
this change reads AI Engine platform management node ID from DT node.
Some
AI engine is the acceleration engine provided by Xilinx. These engines
provide high compute density for vector-based algorithms, and flexible
custom compute and data movement. It has core tiles for compute and
shim tiles to interface the FPGA fabric.
You can check the AI engine architecture
Xilinx AI engine array can be partitioned statically for different
applications. In the device tree, there will be device node for the AI
engine device, and device nodes for the statically configured AI engine
partitions. Each of the statically configured partition has a partition
ID in the
After seeing a large number of suspend failures due to -EBUSY, the most
common cause for failure seems to be the log snippet below:
[ 4764.773873] Bluetooth: hci_cmd_timeout() hci0 command 0x0c14 tx timeout
[ 4767.777897] Bluetooth: btmrvl_enable_hs() Host sleep enable command failed
[
Some older controllers fail to enter a quiescent state reliably when
supporting remote wake. For those cases, add a quirk that will power
down the controller when suspending and power it back up when resuming.
Signed-off-by: Abhishek Pandit-Subedi
Reviewed-by: Miao-chen Chou
---
Rename clean_up_hci_state and move to the core header so that we can
power down the controller from within the kernel rather than just via
mgmt commands.
Signed-off-by: Abhishek Pandit-Subedi
Reviewed-by: Daniel Winkler
Reviewed-by: Miao-chen Chou
---
include/net/bluetooth/hci_core.h | 2 ++
Hi Marcel and linux-bluetooth,
This patch series adds support for a quirk that will power down the
Bluetooth controller when suspending and power it back up when resuming.
On Marvell SDIO Bluetooth controllers (SD8897 and SD8997), we are seeing
a large number of suspend failures with the
On Thu, Nov 19, 2020 at 12:27:19AM +0100, Andrew Lunn wrote:
> On Wed, Nov 18, 2020 at 03:09:27PM -0800, rentao.b...@gmail.com wrote:
> > From: Tao Ren
> >
> > The patch series adds hardware monitoring driver for the Maxim MAX127
> > chip.
>
> Hi Tao
>
> Why are using sending a hwmon driver to
On Wed, Nov 18, 2020 at 2:07 PM Sami Tolvanen wrote:
>
> This patch series adds support for building the kernel with Clang's
> Link Time Optimization (LTO). In addition to performance, the primary
> motivation for LTO is to allow Clang's Control-Flow Integrity (CFI) to
> be used in the kernel.
Enable i2c-mux-gpio devices to be defined via ACPI. The idle-state
property translates directly to a fwnode_property_*() call. The child
reg property translates naturally into _ADR in ACPI.
The i2c-parent binding is a relic from the days when the bindings
dictated that all direct children of an
Factor out >dev into a local variable in preparation for
the ACPI enablement of this function, which will utilize the variable
more.
Signed-off-by: Evan Green
---
Changes in v3:
- Introduced minor >dev to dev refactor (Peter)
drivers/i2c/muxes/i2c-mux-gpio.c | 5 +++--
1 file changed, 3
On Mon, Sep 28, 2020 at 10:33:13AM -0700, Paul E. McKenney wrote:
> On Mon, Sep 28, 2020 at 09:57:29AM +0200, Peter Zijlstra wrote:
> > On Thu, Sep 17, 2020 at 11:00:05AM -0700, Paul E. McKenney wrote:
> > > On Thu, Sep 17, 2020 at 01:26:52PM +1000, Stephen Rothwell wrote:
> > > > Hi all,
> > > >
The i2c-mux-gpio driver is a handy driver to have in your bag of tricks,
but it currently only works with DT-based firmware. Enable this driver
on ACPI platforms as well.
The first patch is a little dinky. Peter, if it turns out you'd rather
just take this all as a single patch, feel free to
On Wed, Nov 18, 2020 at 09:30:01PM +0100, Christian Eggers wrote:
> This series adds support for PTP to the KSZ956x and KSZ9477 devices.
>
> There is only little documentation for PTP available on the data sheet
> [1] (more or less only the register reference). Questions to the
> Microchip
On Wed, Nov 18, 2020 at 11:56:21PM +0100, Marco Elver wrote:
> On Tue, Nov 17, 2020 at 10:29AM -0800, Paul E. McKenney wrote:
> [...]
> > But it would be good to get the kcompactd() people to look at this (not
> > immediately seeing who they are in MAINTAINERS). Perhaps preemption is
> >
On 11/10/2020 3:02 PM, Rikard Falkeborn wrote:
The only usage of the kf_ops field in the rftype struct is to pass it as
argument to __kernfs_create_file(), which accepts a pointer to const.
Make it a pointer to const. This makes it possible to make
rdtgroup_kf_single_ops and kf_mondata_ops
On Wed, Nov 18, 2020 at 04:25:37PM -0700, Jens Axboe wrote:
> On 11/18/20 4:18 PM, Michal Kubecek wrote:
> > On Wed, Nov 18, 2020 at 02:27:08PM -0700, Jens Axboe wrote:
> >> On 11/18/20 12:59 PM, Michal Kubecek wrote:
> >>> On Wed, Nov 18, 2020 at 03:18:06PM +, Christoph Hellwig wrote:
>
On Wed, Nov 18, 2020 at 04:43:35PM +0100, Christian Eggers wrote:
> If dsa_switch_ops::port_txtstamp() returns false, clone will be freed
> immediately. Storing the pointer in DSA_SKB_CB(skb)->clone anyway,
> supports annoying use-after-free bugs.
Like what?
> Signed-off-by: Christian Eggers
>
Hi Guilherme,
On Wed, Nov 18, 2020 at 07:56:38PM -0300, Guilherme G. Piccoli wrote:
> Hi Vincent (and all CCed), I'm sorry to ping about such "old" patch, but
> we experienced a similar condition to what this patch addresses; it's an
> older kernel (4.15.x) but when suggesting the users to move
allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a005-20201118
x86_64 randconfig-a003-20201118
x86_64 randconfig-a004-20201118
x86_64
On 11/18/20 6:49 PM, Bjorn Helgaas wrote:
On Sun, Nov 15, 2020 at 10:19:22PM +0100, Maximilian Luz wrote:
On 11/15/20 9:27 PM, Bjorn Helgaas wrote:
[...]
I think something read from sysfs is a snapshot with no guarantee
about how long it will remain valid, so I don't see a problem with the
This adds crashkernel=auto feature to configure reserved memory for
vmcore creation to both x86 and ARM platforms based on the total memory
size.
Cc: sta...@vger.kernel.org
Signed-off-by: John Donnelly
Signed-off-by: Saeed Mirzamohammadi
---
Documentation/admin-guide/kdump/kdump.rst | 5 +
On Wed, Nov 18, 2020 at 03:09:27PM -0800, rentao.b...@gmail.com wrote:
> From: Tao Ren
>
> The patch series adds hardware monitoring driver for the Maxim MAX127
> chip.
Hi Tao
Why are using sending a hwmon driver to the networking mailing list?
Andrew
On 11/18/20 4:18 PM, Michal Kubecek wrote:
> On Wed, Nov 18, 2020 at 02:27:08PM -0700, Jens Axboe wrote:
>> On 11/18/20 12:59 PM, Michal Kubecek wrote:
>>> On Wed, Nov 18, 2020 at 03:18:06PM +, Christoph Hellwig wrote:
On Wed, Nov 18, 2020 at 10:19:17AM +0100, Michal Kubecek wrote:
>
On Wed, Nov 18, 2020 at 3:07 PM Ard Biesheuvel wrote:
>
> On Thu, 19 Nov 2020 at 00:05, Nick Desaulniers
> wrote:
> >
> > > > > > > To avoid playing whack-a-mole with different architectures over
> > > > > > > time,
> > > > > > > hoist '-z norelro' into the main Makefile. This does not affect
On Wed, 18 Nov 2020 13:13:35 -0800 Andrew Morton wrote:
> On Wed, 18 Nov 2020 11:46:54 -0800 Jakub Kicinski wrote:
>
> > > 1. The kernel is under memory pressure and allocation of
> > > PAGE_FRAG_CACHE_MAX_ORDER in __page_frag_cache_refill() will fail.
> > > Instead,
> > > the pfmemalloc page
This patch removes a loose "i" character is present on the current
documentation.
Signed-off-by: Gustavo Pimentel
---
Documentation/devicetree/bindings/reset/snps,dw-reset.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Wed, Nov 18, 2020 at 02:27:08PM -0700, Jens Axboe wrote:
> On 11/18/20 12:59 PM, Michal Kubecek wrote:
> > On Wed, Nov 18, 2020 at 03:18:06PM +, Christoph Hellwig wrote:
> >> On Wed, Nov 18, 2020 at 10:19:17AM +0100, Michal Kubecek wrote:
> >>> While eventfd ->read() callback was replaced
On Wed, Nov 18, 2020 at 10:57:26PM +0100, Daniel Vetter wrote:
> On Wed, Nov 18, 2020 at 5:02 PM Bjorn Helgaas wrote:
> > On Fri, Nov 06, 2020 at 10:39:16AM +0100, Daniel Vetter wrote:
> > > On Thu, Nov 5, 2020 at 3:17 PM Bjorn Helgaas wrote:
> > > > On Thu, Nov 05, 2020 at 11:46:06AM +0200,
On Sat, Nov 7, 2020 at 5:58 AM Adam Ford wrote:
>
> The driver exists for the Enhanced Asynchronous Sample Rate Converter
> (EASRC) Controller, but there isn't a device tree entry for it.
>
> On the vendor kernel, they put this on a spba-bus for SDMA support.
>
> Add the node for the spba-bus
From: Tao Ren
Add documentation for the max127 hardware monitoring driver.
Signed-off-by: Tao Ren
---
Changes in v2:
- add more description for min/max sysfs nodes.
- convert values from volt to millivolt in the document.
Documentation/hwmon/index.rst | 1 +
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