Signed-off-by: Michael Klein
---
No changes in v2
.../devicetree/bindings/regulator/mcp16502-regulator.txt| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/regulator/mcp16502-regulator.txt
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch makes this
support generic across gpu families. This is in preparation to
extend speed-bin support to a6x family.
Signed-off-by: Akhil P Oommen
---
Changes from v1:
1. Added
On 11/16/2020 10:44 PM, Jordan Crouse wrote:
On Mon, Nov 16, 2020 at 07:40:03PM +0530, Akhil P Oommen wrote:
On 11/12/2020 10:05 PM, Jordan Crouse wrote:
On Thu, Nov 12, 2020 at 09:19:04PM +0530, Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a
Extend speed-bin support to a618 gpu.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index e0ff16c..21db7ae 100644
---
Add support for gpu fuse to help identify the supported opps.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index
On Fri, 2020-11-27 at 06:21 -0500, Paolo Bonzini wrote:
> This is my take on the split irqchip bug that David reported. It's a
> much more complicated patch, but I think it really gets to the bottom
> of the issue and the code is clearer.
Looks good to me; thanks. With the exception of the
On Fri, Nov 27, 2020 at 1:31 PM Swapnil Ingle wrote:
>
> Adding name to the Contributors List
>
> Signed-off-by: Swapnil Ingle
Hi, Swapnil,
Thanks for your past contributions, sorry for missing your name on the list.
Acked-by: Jack Wang
> ---
> drivers/block/rnbd/README | 1 +
> 1 file
On 2020-11-27 12:45, John Garry wrote:
On 27/11/2020 09:57, Marc Zyngier wrote:
If I understand the code correctly, MSI_ALLOC_FLAGS_SHARED_DEVICE is
supposed to be set in info->flags in platform_msi_set_desc(), but
this
is called per-msi after its_msi_prepare(), so we don't the flags set
at
On 27/11/2020 09:57, Marc Zyngier wrote:
If I understand the code correctly, MSI_ALLOC_FLAGS_SHARED_DEVICE is
supposed to be set in info->flags in platform_msi_set_desc(), but this
is called per-msi after its_msi_prepare(), so we don't the flags set
at the right time. That's how it looks to
On 18.11.20 11:01, Andy Shevchenko wrote:
>>> So a system without CONFIG_OF might still make use of .of_match_table?
>>
>> Yep!
>
> If you are curious:
> https://elixir.bootlin.com/linux/latest/source/drivers/acpi/bus.c#L615
Phuh, this changes everything ... sorry, didn't know that.
If ACPI
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi Linus,
Please pull some more powerpc fixes for 5.10.
Note this includes a merge of the powerpc-cve-2020-4788 tag, which you already
have, so that I could fix a build break it introduced. That merge should be a
nop from your POV.
cheers
The
The commit 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows") gets
the values of pci->num_ib_windows and pci->num_ob_windows from iATU
registers instead of DT properties.
However, before the values are set, the allocations in dw_pcie_ep_init()
refer them to determine the sizes of
On 19/11/2020 15:13, Enric Balletbo Serra wrote:
Hi Weiyi,
Missatge de Weiyi Lu del dia dj., 19 de nov.
2020 a les 14:10:
On Thu, 2020-11-19 at 13:13 +0100, Enric Balletbo Serra wrote:
Hi Weiyi,
Thank you for the patch
Missatge de Weiyi Lu del dia dj., 19 de nov.
2020 a les 11:48:
Hi Chun-Kuang,
On 20/11/2020 00:46, Chun-Kuang Hu wrote:
Hi, Matthias:
I've provided the example for why of this patch. How do you think
about this patch?
Patch looks good to me. If you want to take it through your tree you can add my
Acked-by: Matthias Brugger
Beware that you might need
Hi Linus,
Please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
tags/media/v5.10-3
For a series of fixes for the new the virtual digital TV driver (vidtv),
which is meant to help doing tests with the digital TV core and media
userspace apps and libraries.
They
On Thu 2020-11-26 20:32:18, Kefeng Wang wrote:
>
> On 2020/11/26 19:48, John Ogness wrote:
> > Any record with a trailing newline (LOG_NEWLINE flag) cannot
> > be continued because the newline has been stripped and will
> > not be visible if the message is appended. This was already
> > handled
On Fri, Nov 27, 2020 at 09:42:03AM +0530, Srinivasa Rao Mandadapu wrote:
> To support playback continuation after resume problem in chrome
> audio server:
> Prepare device in platform trigger callback.
> Make I2s and DMA control registers as non volatile.
What is the actual issue this is fixing?
After migration to the shared interrupt support, the KSZ8031 PHY with
enabled interrupt support was not able to notify about link status
change.
Fixes: 59ca4e58b917 ("net: phy: micrel: implement generic .handle_interrupt()
callback")
Signed-off-by: Oleksij Rempel
---
drivers/net/phy/micrel.c |
Hello,
syzbot found the following issue on:
HEAD commit:418baf2c Linux 5.10-rc5
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=171555b950
kernel config: https://syzkaller.appspot.com/x/.config?x=b81aff78c272da44
dashboard link:
Hi,
On 11/27/20 12:41 PM, Hans de Goede wrote:
> Hi,
>
> On 11/24/20 11:27 AM, Christoph Hellwig wrote:
>> On Mon, Nov 23, 2020 at 03:49:09PM +0100, Hans de Goede wrote:
>>> Hi,
>>>
>>> +Cc Christoph Hellwig
>>>
>>> Christoph, this is still an issue, so I've been looking around a bit and
>>>
From: Lars-Peter Clausen
Add support for the Analog Devices ADAU1372 audio CODEC.
[Alexandre Belloni: allow 32kHz for TDM4 in slave mode]
Signed-off-by: Lars-Peter Clausen
Signed-off-by: Alexandre Belloni
---
Changes in v2:
- Fix Microphone bias
sound/soc/codecs/Kconfig| 16 +
Add device tree binding documentation for Analog Devices ADAU1372.
Signed-off-by: Alexandre Belloni
Reviewed-by: Rob Herring
---
Changes in v2:
- Added Rob's reviewed-by
.../bindings/sound/adi,adau1372.yaml | 67 +++
1 file changed, 67 insertions(+)
create mode
On Thu, 26 Nov 2020 at 17:35, Willem de Bruijn
wrote:
> On Thu, Nov 26, 2020 at 3:19 AM Marco Elver wrote:
[...]
> > Will send v2.
>
> Does it make more sense to revert the patch that added the extensions
> and the follow-on fixes and add a separate new patch instead?
That doesn't work, because
On Fri 20-11-20 19:04:52, David Hildenbrand wrote:
> commit 6471384af2a6 ("mm: security: introduce init_on_alloc=1 and
> init_on_free=1 boot options") resulted with init_on_alloc=1 in all pages
> leaving the buddy via alloc_pages() and friends to be
> initialized/cleared/zeroed on allocation.
>
>
On Thu, Nov 26, 2020 at 05:23:59PM -0500, Peter Xu wrote:
> For missing mode uffds, fault around does not help because if the page cache
> existed, then the page should be there already. If the page cache is not
> there, nothing else we can do, either. If the fault-around code is destined
> to
> On Nov 26, 2020, at 22:45, Chen Yu wrote:
>
> On Thu, Nov 26, 2020 at 08:05:02PM +0800, Kai-Heng Feng wrote:
>>
>>
>>> On Nov 26, 2020, at 19:10, Chen Yu wrote:
>>>
>>> On Thu, Nov 26, 2020 at 02:36:42PM +0800, Kai-Heng Feng wrote:
>>
>> What about plugging ethernet cable and
On Mon, Nov 23, 2020 at 09:22:08PM +0800, Yunfeng Ye wrote:
> In realtime scenarios, the "nohz_full" parameter is configured. Tick
> interference is not expected when there is only one realtime thread.
> But when the idle thread is switched to the realtime thread, the tick
> timer is restarted
On Fri, Nov 13, 2020 at 10:26:54AM -0800, Sami Tolvanen wrote:
> e820__mapped_all is passed as a callback to is_mmconf_reserved, which
> expects a function of type:
>
> typedef bool (*check_reserved_t)(u64 start, u64 end, unsigned type);
>
> This trips indirect call checking with Clang's
Add support for Last Level Cache Controller (LLCC) in SM8250 SoC.
This LLCC is used to provide common cache memory pool for the cores in
the SM8250 SoC thereby minimizing the percore caches.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++
1 file
SM8250 SoC uses LLCC IP version 2. In this version, the WRSC_EN register
needs to be written to enable the Write Sub Cache for each SCID. Hence,
use a dedicated "write_scid_en" member with predefined values and write
them for SoCs enabling the "llcc_v2" flag.
Signed-off-by: Manivannan Sadhasivam
I have just noticed that the title of this cover letter is wrong.
It should have been:
"clk: at91: adapt for dvfs"
Please let me know if you want me to send a new version for this update.
Thank you,
Claudiu
On 19.11.2020 17:43, Claudiu Beznea wrote:
> Hi,
>
> SAMA7G5 is capable of DVFS. The
Add LLCC compatible for SM8250 SoC.
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
Hello,
This series adds Last Level Cache Controller (LLCC) support for SM8250
SoC from Qualcomm.
All 3 patches in this series are expected to go through arm-soc tree.
Thanks,
Mani
Manivannan Sadhasivam (3):
dt-bindings: msm: Add LLCC for SM8250
arm64: dts: qcom: sm8250: Add support for
On 27/11/2020 09:56, Srinivasa Rao Mandadapu wrote:
To support playback continuation after hard suspend(bypass powerd)
and resume:
Prepare device in platform trigger callback.
Make I2s and DMA control registers as non volatile.
Looks like there are two changes here, One is fixing the
On Fri, 20 Nov 2020 at 16:27, Marc Zyngier wrote:
>
> On 2020-11-05 15:29, Ard Biesheuvel wrote:
> > When reseeding the CRNG periodically, arch_get_random_seed_long() is
> > called to obtain entropy from an architecture specific source if one
> > is implemented. In most cases, these are special
On 20-11-26 19:09:37, Greg Kroah-Hartman wrote:
> From: Will McVicker
>
> Needed for SuperSpeed Plus support for f_midi. This allows the
> gadget to work properly without crashing at SuperSpeed rates.
>
> Cc: Felipe Balbi
> Cc: stable
> Signed-off-by: Will McVicker
> Signed-off-by: Greg
On 11/27/20 6:03 AM, Wei Li wrote:
Armv8.3 extends the SPE by adding:
- Alignment field in the Events packet, and filtering on this event
using PMSEVFR_EL1.
- Support for the Scalable Vector Extension (SVE).
The main additions for SVE are:
- Recording the vector length for SVE operations in
On Fri 27-11-20 15:53:14, Charan Teja Kalla wrote:
> Thanks Michal!!
>
> On 11/26/2020 2:48 PM, Michal Hocko wrote:
> > On Wed 25-11-20 16:18:06, Charan Teja Kalla wrote:
> >>
> >>
> >> On 11/24/2020 1:11 PM, Michal Hocko wrote:
> >>> On Mon 23-11-20 20:40:40, Charan Teja Kalla wrote:
>
>
On Sat, Nov 21, 2020 at 5:38 PM Jonathan Cameron wrote:
>
> On Thu, 19 Nov 2020 12:07:45 +0200
> Alexandru Ardelean wrote:
>
> > This change converts the configuration of the dual-channel mode from the
> > old platform-data, to the device_property_present() function, which
> > supports both
Hi Bjorn Lorenzo,
On 2020/11/25 19:23, Lorenzo Pieralisi wrote:
On Tue, Nov 24, 2020 at 05:20:37PM -0600, Bjorn Helgaas wrote:
On Wed, Oct 28, 2020 at 10:31:43AM +0900, Kunihiko Hayashi wrote:
This patch adds misc interrupt handler to detect and invoke PME/AER event.
In UniPhier PCIe
On Fri, 2020-11-27 at 06:21 -0500, Paolo Bonzini wrote:
> +* FIXME: interrupt.injected represents an interrupt that it's
You can drop the stray apostrophe from that "its" while you're moving
it...
smime.p7s
Description: S/MIME cryptographic signature
On Wed, Nov 25, 2020 at 12:20:48PM +0100, Oscar Salvador wrote:
> diff --git a/drivers/acpi/acpi_memhotplug.c b/drivers/acpi/acpi_memhotplug.c
> index b02fd51e5589..1fe645ef0b6c 100644
> --- a/drivers/acpi/acpi_memhotplug.c
> +++ b/drivers/acpi/acpi_memhotplug.c
> @@ -172,6 +172,7 @@ static int
On Fri, Nov 27, 2020 at 10:26:47AM +, Marc Zyngier wrote:
> On 2020-11-24 15:50, Will Deacon wrote:
> > If a vCPU is caught running 32-bit code on a system with mismatched
> > support at EL0, then we should kill it.
> >
> > Acked-by: Marc Zyngier
> > Signed-off-by: Will Deacon
> > ---
> >
On Fri, Nov 27, 2020 at 06:39:24PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the akpm-current tree got a conflict in:
>
> include/linux/kernel.h
>
> between commit:
>
> 74d862b682f5 ("sched: Make migrate_disable/enable() independent of RT")
>
> from the tip
On Fri, Nov 27, 2020 at 10:25:06AM +, Marc Zyngier wrote:
> On 2020-11-24 15:50, Will Deacon wrote:
> > When confronted with a mixture of CPUs, some of which support 32-bit
> > applications and others which don't, we quite sensibly treat the system
> > as 64-bit only for userspace and prevent
On 27/11/2020 01:17, Ivaylo Dimitrov wrote:
> Hi Tomi,
>
> On 26.11.20 г. 16:11 ч., Tomi Valkeinen wrote:
>> Hi Aaro, Ivaylo,
>>
>> On 24/11/2020 23:03, Ivaylo Dimitrov wrote:
>>
>>> Is there any progress on the issue? I tried 5.9.1 and still nothing
>>> displayed.
>>
>> Can you test the
Hi again, Linus,
Here's another round of IOMMU fixes for -rc6 consisting mainly of a
bunch of independent driver fixes. Thomas agreed for me to take the
x86 'tboot' fix here, as it fixes a regression introduced by a vt-d
change.
Please pull,
Will
--->8
The following changes since commit
On 2020/11/27 16:45, Chen Huang wrote:
When a function doesn't have a callee, then it will not push ra
into the stack, such as lkdtm_BUG() function:
addisp,sp,-16
sd s0,8(sp)
addis0,sp,16
ebreak
Then we use pt_regs as a parameter to walk_stackframe(), for the
struct stackframe
Hi,
On 11/24/20 11:27 AM, Christoph Hellwig wrote:
> On Mon, Nov 23, 2020 at 03:49:09PM +0100, Hans de Goede wrote:
>> Hi,
>>
>> +Cc Christoph Hellwig
>>
>> Christoph, this is still an issue, so I've been looking around a bit and
>> think this
>> might have something to do with the
Hi Linus,
Here are some arm64 fixes for -rc6. The main changes are relating to our
handling of access/dirty bits, where our low-level page-table helpers
could lead to stale young mappings and loss of the dirty bit in some
cases (the latter has not been observed in practice, but could happen
when
On Fri, Nov 27, 2020 at 10:21 AM Lee Jones wrote:
>
> It's a per-subsystem convention thing.
I think some allow both, too. For people that send tree-wide patches,
it would be if we agreed on the convention...
Cheers,
Miguel
On Fri, Nov 20, 2020 at 12:46:21PM +0100, Juergen Gross wrote:
> SWAPGS is used only for interrupts coming from user mode or for
> returning to user mode. So there is no reason to use the PARAVIRT
> framework, as it can easily be replaced by an ALTERNATIVE depending
> on X86_FEATURE_XENPV.
>
>
From: Andrew Cooper
> Sent: 26 November 2020 23:52
>
> On 26/11/2020 19:15, Andy Lutomirski wrote:
> > On Thu, Nov 26, 2020 at 11:07 AM Lukas Bulwahn
> > wrote:
> >> On Thu, Nov 26, 2020 at 6:16 PM Andrew Cooper
> >> wrote:
> >>> On 26/11/2020 11:54, Lukas Bulwahn wrote:
> Commit
On 27/11/2020 11:49, Enric Balletbo i Serra wrote:
Dear all,
The following patches add the required nodes to enable dsi and display
support for MT8183 based boards. The patches were tested on a Lenovo
Ideapad Duet with an out-of-tree patch that enables the display for that
board.
Applied
From: Bongsu Jeon
Extract the common phy blocks to reuse it.
The UART module will use the common blocks.
Signed-off-by: Bongsu Jeon
---
Changes in v2:
- remove the common function's definition in common header file.
- make the common phy_common.c file to define the common function.
- wrap
This is my take on the split irqchip bug that David reported. It's a
much more complicated patch, but I think it really gets to the bottom
of the issue and the code is clearer.
Paolo
Paolo Bonzini (2):
KVM: x86: handle !lapic_in_kernel case in kvm_cpu_*_extint
KVM: x86: Fix split-irqchip vs
Centralize handling of interrupts from the userspace APIC
in kvm_cpu_has_extint and kvm_cpu_get_extint, since
userspace APIC interrupts are handled more or less the
same as ExtINTs are with split irqchip. This removes
duplicated code from kvm_cpu_has_injectable_intr and
kvm_cpu_has_interrupt, and
kvm_cpu_accept_dm_intr and kvm_vcpu_ready_for_interrupt_injection are
a hodge-podge of conditions, hacked together to get something that
more or less works. But what is actually needed is much simpler;
in both cases the fundamental question is, do we have a place to stash
an interrupt if
On 25/11/2020 11:24, Enric Balletbo i Serra wrote:
Hi Hsin-Yi,
Thank you for your patch.
On 24/11/20 5:12, Hsin-Yi Wang wrote:
Add pwm to mt8183 and backlight to mt8183-kukui.
Signed-off-by: Hsin-Yi Wang
---
Picked the patch and checked that pwm for the backlight is working as expected
On Fri, Nov 27, 2020 at 8:35 AM Yonghong Song wrote:
>
>
>
> On 11/26/20 8:57 AM, Florent Revest wrote:
> > This helper exposes the kallsyms_lookup function to eBPF tracing
> > programs. This can be used to retrieve the name of the symbol at an
> > address. For example, when hooking into
On 30/10/2020 12:36, Enric Balletbo i Serra wrote:
Dear all,
This is a new driver with the aim to deprecate the mtk-scpsys driver.
The problem with that driver is that, in order to support more Mediatek
SoCs you need to add some logic to handle properly the power-up
sequence of newer
On Wed, Nov 25, 2020 at 06:11:02PM +0800, Jinyang He wrote:
> Reserve memory from &_text to &_end. Otherwise if kernel address
> was modified, the memory range of start_pfn to kernel_start_pfn
> would be reserved. Then we could not use this range.
>
> Signed-off-by: Jinyang He
> ---
>
From: Rafał Miłecki
It's a trivial reset controller. One register with bit per PCIe core.
Signed-off-by: Rafał Miłecki
---
drivers/reset/Kconfig| 2 +-
drivers/reset/reset-simple.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/reset/Kconfig
From: Rafał Miłecki
BCM4908 was built using older PCIe hardware block that requires using
external reset block controlling PERST# signals.
Signed-off-by: Rafał Miłecki
---
.../reset/brcm,bcm4908-misc-pcie-reset.yaml | 39 +++
1 file changed, 39 insertions(+)
create mode
This change wraps the devices supported by the adp5589 driver into a chip
info struct. With this, a device table can be created, and the probed
device can be selected based on the enum value provided by the i2c driver
data.
Signed-off-by: Alexandru Ardelean
---
From: Lars-Peter Clausen
Add very basic devicetree suppport to the adp5589 allowing the device to be
registered from devicetree and ACPI via PRP0001.
Signed-off-by: Lars-Peter Clausen
Signed-off-by: Alexandru Ardelean
---
drivers/input/keyboard/adp5589-keys.c | 30 ++-
This change adds the device-tree entries for the Analog Devices ADP5585 and
ADP5589 devices to the trivial devices list.
Signed-off-by: Alexandru Ardelean
---
Documentation/devicetree/bindings/trivial-devices.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git
From: Lars-Peter Clausen
If no platform data is supplied use a dummy platform data that configures
the device in GPIO only mode. This change adds a adp5589_kpad_pdata_get()
helper that returns the default platform-data. This can be later extended
to load configuration from device-trees or ACPI.
On Wed, 25 Nov 2020, Shihlun Lin wrote:
> AHC1EC0 is the embedded controller driver for Advantech industrial
> products. This provides sub-devices such as hwmon and watchdog, and also
> expose functions for sub-devices to read/write the value to embedded
> controller.
>
> Signed-off-by: Shihlun
Em Sat, 30 May 2020 10:41:17 +0800
Jia-Ju Bai escreveu:
> The value hdev->sfr.kva is stored in DMA memory, and it is assigned to
> sfr, so sfr->buf_size can be modified at anytime by malicious hardware.
> In this case, a buffer overflow may happen when the code
> "sfr->data[sfr->buf_size - 1]"
From: Alexander Sverdlin
Allocate the IRQ descriptors where necessary before configuring them via
irq_set_chip_and_handler(). Fixes the following soft lockup:
watchdog: BUG: soft lockup - CPU#5 stuck for 22s! [modprobe:72]
Modules linked in:
irq event stamp: 33288
hardirqs last enabled at
On Tue, Nov 24, 2020 at 08:09:19PM +0200, Julian Anastasov wrote:
>
> Hello,
>
> On Tue, 24 Nov 2020, Wang Hai wrote:
>
> > kmemleak report a memory leak as follows:
> >
> > BUG: memory leak
> > unreferenced object 0x8880759ea000 (size 256):
> > backtrace:
> > []
On Fri, Nov 27, 2020 at 08:11:05AM +0100, Uwe Kleine-König wrote:
> Hello Jonathan,
>
> On Fri, Nov 27, 2020 at 12:19:31AM +0100, Jonathan Neuschäfer wrote:
> > On Tue, Nov 24, 2020 at 09:20:19AM +0100, Uwe Kleine-König wrote:
> > > On Sun, Nov 22, 2020 at 11:27:36PM +0100, Jonathan Neuschäfer
Aliases property name must include only lowercase and '-', so fix this
in the driver, so we're not tempted to do "ovl_2l0 = _2l0" in the
device-tree instead of the right one which is "ovl-2l0 = _2l0".
Fixes: dd8feb2262d9 ("drm/mediatek: add component OVL_2L1")
Fixes: b17bdd0d7a73 ("drm/mediatek:
default to 1 message per transfer (requested by Helen)
- Move -EIO error reporting to transfer function to cleanup transfer() itself
and its R/W callers
- Remove magic value hardcodings and introduce enum force_release.
Applies on next-20201127, tested on Chromebook EVE.
---
drivers/cha
Hyvä asiakas
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asuntolainoja, henkilökohtaisia ??lainoja, autolainoja, opintolainoja,
konsolidointiosastoa, Business Start -lainoja. Onko sinulla
Hi Michael,
On 11/27/20 11:43 AM, Michael Kerrisk (man-pages) wrote:
> Hi ALex,
>
> On 11/26/20 7:32 PM, Alejandro Colomar wrote:
>> The current Linux kernel only provides a definition of 'spu_create()'.
>> It has 4 parameters, the last being 'int neighbor_fd'.
>>
>> Before Linux 2.6.23, there
On 2020/11/27 16:17, Zheng Zengkai wrote:
> Hello Tetsuo,
>> On 2020/11/26 15:33, Zheng Zengkai wrote:
>>> As your say, I found the function tomoyo_assign_namespace( )
>>>
>>> in security/tomoyo/domain.c has the similar situation,
>>>
>>> Can I add __GFP_NOWARN for both and remove the null check
On Thu, Nov 26, 2020 at 08:31:51PM +, Mel Gorman wrote:
> > > and it is reasonable behaviour but it should be tunable.
> >
> > Only if there is no way to cover all of the relevant use cases in a
> > generally acceptable way without adding more module params etc.
> >
> > In this particular
From: Jitao Shi
Add dsi and mipitx nodes to the MT8183.
Signed-off-by: Jitao Shi
Signed-off-by: Enric Balletbo i Serra
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 31
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
Add display subsystem device nodes to allow video output.
Signed-off-by: Enric Balletbo i Serra
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 114 +++
1 file changed, 114 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
Dear all,
The following patches add the required nodes to enable dsi and display
support for MT8183 based boards. The patches were tested on a Lenovo
Ideapad Duet with an out-of-tree patch that enables the display for that
board.
The patches depends on [1].
[1]
Add iommu and larb nodes to the MT8183.
Signed-off-by: Enric Balletbo i Serra
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index
From: Thierry Reding
These were just some minor typos that have crept in recently and are
easily fixed.
Signed-off-by: Thierry Reding
---
drivers/base/core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/base/core.c b/drivers/base/core.c
index
Hi ALex,
On 11/26/20 7:32 PM, Alejandro Colomar wrote:
> The current Linux kernel only provides a definition of 'spu_create()'.
> It has 4 parameters, the last being 'int neighbor_fd'.
>
> Before Linux 2.6.23, there was an older prototype,
> which didn't have this last parameter.
>
> Move that
On 11/10/20 12:45 PM, Anshuman Khandual wrote:
perf handle structure needs to be shared with the TRBE IRQ handler for
capturing trace data and restarting the handle. There is a probability
of an undefined reference based crash when etm event is being stopped
while a TRBE IRQ also getting
Hi Will
Thanks a lot for your detailed review of my v3 below and sorry for the delay of
my answer : those last months were rather focused on the pmu driver using
than its improvement.
I prepared a v4 on kernel 5.10, taking into account most of your remarks below
but I still have some open
From: Evan Green
Add SoC-specific compatible strings so that data can be attached
to it in the driver.
Signed-off-by: Evan Green
Reviewed-by: Rob Herring
Signed-off-by: Srinivas Kandagatla
---
.../devicetree/bindings/nvmem/qcom,qfprom.yaml | 17 ++---
1 file changed, 14
On Thu, Nov 26, 2020 at 7:00 PM Robert Foss wrote:
>
> On Wed, 25 Nov 2020 at 08:32, Tomasz Figa wrote:
> >
> > Hi Bingbu,
> >
> > On Wed, Nov 25, 2020 at 1:15 PM Bingbu Cao
> > wrote:
> > >
> > >
> > >
> > > On 11/24/20 6:20 PM, Robert Foss wrote:
> > > > On Tue, 24 Nov 2020 at 10:42, Bingbu
From: Peng Fan
When offset is not 4 bytes aligned, directly shift righty by 2 bits
will cause reading out wrong data. Since imx ocotp only supports
4 bytes reading once, we need handle offset is not 4 bytes aligned
and enlarge the bytes to 4 bytes aligned. After reading finished,
copy the needed
Hi Greg,
Here are some nvmem patches for 5.11 which includes
- adding support to keepout regions in nvmem core
- support for unaligned word count in imx provider
- imx and qfprom new compatible strings.
Can you please queue them up for 5.11.
thanks for you help,
srini
Evan Green (3):
nvmem:
From: Evan Green
Some fuse ranges are protected by the XPU such that the AP cannot
access them. Attempting to do so causes an SError. Use the newly
introduced per-soc compatible string, and the newly introduced
nvmem keepout support to attach the set of regions
we should not access.
From: Fabien Parent
Add binding documentation for MT8516 SoCs.
Signed-off-by: Fabien Parent
Acked-by: Rob Herring
Signed-off-by: Srinivas Kandagatla
---
Documentation/devicetree/bindings/nvmem/mtk-efuse.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Evan Green
Introduce support into the nvmem core for arrays of register ranges
that should not result in actual device access. For these regions a
constant byte (repeated) is returned instead on read, and writes are
quietly ignored and returned as successful.
This is useful for instance
On 2020-11-24 15:50, Will Deacon wrote:
If a vCPU is caught running 32-bit code on a system with mismatched
support at EL0, then we should kill it.
Acked-by: Marc Zyngier
Signed-off-by: Will Deacon
---
arch/arm64/kvm/arm.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
Failure of dma_alloc_coherent will already throw a error message,
so addition message is really redundant here. Remove it!
Signed-off-by: Srinivas Kandagatla
---
drivers/slimbus/qcom-ngd-ctrl.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/slimbus/qcom-ngd-ctrl.c
This patch adds SSR(SubSystem Restart) support which includes, synchronisation
between SSR and QMI server notifications. Also with this patch now NGD is taken
down by SSR instead of QMI server down notification.
NGD up path now relies on both SSR and QMI notifications and particularly
sequence of
From: Rikard Falkeborn
qcom_slim_qmi_msg_handlers[] and qcom_slim_ngd_qmi_svc_event_ops are
only used as input arguments to qmi_handle_init() which accepts const
pointers to both qmi_ops and qmi_msg_handler. Make them const to allow
the compiler to put them in read-only memory.
Signed-off-by:
Hi Greg,
Here are some slimbus patches for 5.11 which includes
- ngd controller has added PDR and SSR support along with a trival fixes.
- few doc and clang warning fixes in slimbus
Can you please queue them up for 5.11.
thanks for you help,
srini
Bjorn Andersson (1):
slimbus: qcom-ngd-ctrl:
From: Bjorn Andersson
Attempting to send a power request during PM operations, when the QMI
handle isn't initialized results in a NULL pointer dereference. So check
if the QMI handle has been initialized before attempting to post the
power requests.
Fixes: 917809e2280b ("slimbus: ngd: Add qcom
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