On Thu, 10 Dec 2020 10:24:36 -0600, Suravee Suthikulpanit wrote:
> Currently, macros related to the interrupt remapping table length are
> defined separately. This has resulted in an oversight in which one of
> the macros were missed when changing the length. To prevent this,
> redefine the macros
Why does your mailer thread emails?
Your reply is not detached from the remainder of the thread.
On Fri, 11 Dec 2020, David Laight wrote:
> From: Lee Jones
> > Sent: 11 December 2020 10:06
> >
> > On Fri, 11 Dec 2020, Zheng Yongjun wrote:
> >
> > > Replace a comma between expression statements
On Fri, Dec 11, 2020 at 5:35 PM Oscar Salvador wrote:
>
> On Thu, Dec 10, 2020 at 11:55:20AM +0800, Muchun Song wrote:
> > When we free a HugeTLB page to the buddy allocator, we should allocate the
> > vmemmap pages associated with it. We can do that in the __free_hugepage()
> "vmemmap pages that
On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote:
> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
> On platforms with Zhaoxin CPUs supporting this X86 feature, When
> crc32c-intel and crc32c-generic are both registered, system will
> use crc32c-intel because its .c
On Fri, Dec 11 2020 at 10:13, Tvrtko Ursulin wrote:
> On 10/12/2020 19:25, Thomas Gleixner wrote:
>>
>> Aside of that the count is per interrupt line and therefore takes
>> interrupts from other devices into account which share the interrupt line
>> and are not handled by the graphics driver.
>>
On Fri, 11 Dec 2020 03:48:40 +0200
Abanoub Sameh wrote:
> This gets rid of enum led_brightness in the main led files,
> because it is deprecated, and an int can be used instead,
> or maybe even a uint8_t since it only goes up to 255.
> Next we can also patch the other files to get rid of it compl
On Fri, 2020-12-11 at 20:27 +0900, Yoshihiro Shimoda wrote:
> Add support for BD9574MWF which is silimar chip with BD9571MWV.
> Note that BD9574MWF has an additional feature, but doesn't
> support it for now.
nit:
Perhaps mention which feature? And I think you mean the driver does not
support it
On Thu, Dec 10, 2020 at 04:38:28PM +, Valentin Schneider wrote:
> Valentin Schneider (2):
> stop_machine: Add caller debug info to queue_stop_cpus_work
> workqueue: Fix affinity of kworkers attached during late hotplug
>
> kernel/stop_machine.c | 1 +
> kernel/workqueue.c| 24 +++
Hi Vincent,
On 11/12/20 11:39, Vincent Donnefort wrote:
> Hi Valentin,
>
> On Thu, Dec 10, 2020 at 04:38:30PM +, Valentin Schneider wrote:
>> Fixes: 06249738a41a ("workqueue: Manually break affinity on hotplug")
>
> Isn't the problem introduced by 1cf12e0 ("sched/hotplug: Consolidate
> task
On Fri, Dec 11, 2020 at 11:39:21AM +, Vincent Donnefort wrote:
> On Thu, Dec 10, 2020 at 04:38:30PM +, Valentin Schneider wrote:
> > + if (pool->flags & POOL_DISASSOCIATED) {
> > worker->flags |= WORKER_UNBOUND;
> > + set_cpus_allowed_ptr(worker->task, cpu_active_mas
Am 11.12.2020 um 13:43 schrieb Sven Van Asbroeck:
> Hi Heiner,
>
> On Thu, Dec 10, 2020 at 2:32 AM Heiner Kallweit wrote:
>>
>>
>> In addition you could play with sysfs attributes
>> /sys/class/net//gro_flush_timeout
>> /sys/class/net//napi_defer_hard_irqs
>
> Interesting, I will look into that.
On Fri, Dec 11, 2020 at 07:56:54PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the akpm-current tree got a conflict in:
>
> mm/gup.c
>
> between commit:
>
> 2a4a06da8a4b ("mm/gup: Provide gup_get_pte() more generic")
>
> from the tip tree and commit:
>
> 1eb
Add 5gbase-r PHY interface mode.
Signed-off-by: Pavana Sharma
---
Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
b/Documentation/devicetree/bindings/net/ethernet-co
Updated patchset after rebasing and incorporating feedback.
Pavana Sharma (4):
dt-bindings: net: Add 5GBASER phy interface mode
net: phy: Add 5GBASER interface mode
net: dsa: mv88e6xxx: Change serdes lane parameter type from u8 type
to int
net: dsa: mv88e6xxx: Add support for mv88e639
On 12/11/2020 2:06 PM, Alexander Potapenko wrote:
> On Thu, Dec 10, 2020 at 6:01 AM wrote:
>>
>> From: Yogesh Lal
>>
>> Add a kernel parameter stack_hash_order to configure STACK_HASH_SIZE.
>>
>> Aim is to have configurable value for STACK_HASH_SIZE, so that one
>> can configure it depending o
"#address-cells" and "#size-cells" is required only when the I2C
controller has subnodes. Of the four examples given in this document, only
the third has a child node "eeprom@64".
Ohterwise, false positives similar to the following are reported:
/root/linux-next/arch/arm64/boot/dts/hisilicon/hi622
On Fri, 2020-12-11 at 20:27 +0900, Yoshihiro Shimoda wrote:
> To simplify this driver, use dev_get_regmap() and
> rid of using struct bd9571mwv.
>
> Signed-off-by: Yoshihiro Shimoda
FWIW:
Reviewed-By: Matti Vaittinen
> ---
> drivers/gpio/gpio-bd9571mwv.c | 19 +--
> 1 file ch
On Fri, Dec 11, 2020 at 11:39:21AM +, Vincent Donnefort wrote:
> Hi Valentin,
>
> On Thu, Dec 10, 2020 at 04:38:30PM +, Valentin Schneider wrote:
> > Per-CPU kworkers forcefully migrated away by hotplug via
> > workqueue_offline_cpu() can end up spawning more kworkers via
> >
> > manage
Hi Heiner,
On Thu, Dec 10, 2020 at 2:32 AM Heiner Kallweit wrote:
>
>
> In addition you could play with sysfs attributes
> /sys/class/net//gro_flush_timeout
> /sys/class/net//napi_defer_hard_irqs
Interesting, I will look into that.
> > @@ -2407,7 +2409,7 @@ static int lan743x_rx_open(struct lan
On Fri, Dec 11 2020 at 13:10, Jürgen Groß wrote:
> On 11.12.20 00:20, boris.ostrov...@oracle.com wrote:
>>
>> On 12/10/20 2:26 PM, Thomas Gleixner wrote:
>>> All event channel setups bind the interrupt on CPU0 or the target CPU for
>>> percpu interrupts and overwrite the affinity mask with the cor
On 11/12/2020 14:29, Wang Hai wrote:
> I got a warining report:
>
> br_sysfs_addbr: can't create group bridge4/bridge
> [ cut here ]
> sysfs group 'bridge' not found for kobject 'bridge4'
> WARNING: CPU: 2 PID: 9004 at fs/sysfs/group.c:279 sysfs_remove_group
> fs/sysfs/gro
Hello again Shimada-san,
On Fri, 2020-12-11 at 20:27 +0900, Yoshihiro Shimoda wrote:
> Add support for BD9574MWF which is silimar chip with BD9571MWV.
> Note that BD9574MWF doesn't support AVS and VID.
I'd like to understand what is VID?
>
> Signed-off-by: Yoshihiro Shimoda
> ---
> drivers/re
On 12/10/20 3:18 PM, Thomas Gleixner wrote:
> Prarit reported that depending on the affinity setting the
>
> ' irq $N: Affinity broken due to vector space exhaustion.'
>
> message is showing up in dmesg, but the vector space on the CPUs in the
> affinity mask is definitely not exhausted.
>
>
On Fri, Dec 11, 2020 at 01:09:35PM +0100, 'Greg Kroah-Hartman' wrote:
> On Fri, Dec 11, 2020 at 09:18:24AM +, József Horváth wrote:
> > On Fri, Dec 11, 2020 at 09:43:31AM +0100, 'Greg Kroah-Hartman' wrote:
> > > On Fri, Dec 11, 2020 at 08:16:34AM +, József Horváth wrote:
> > > > On Fri, Dec
I got a warining report:
br_sysfs_addbr: can't create group bridge4/bridge
[ cut here ]
sysfs group 'bridge' not found for kobject 'bridge4'
WARNING: CPU: 2 PID: 9004 at fs/sysfs/group.c:279 sysfs_remove_group
fs/sysfs/group.c:279 [inline]
WARNING: CPU: 2 PID: 9004 at fs/s
On Fri, 2020-12-11 at 16:40 +0800, Zheng Yongjun wrote:
> Replace a comma between expression statements by a semicolon.
>
> Signed-off-by: Zheng Yongjun
> ---
> fs/omfs/file.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/fs/omfs/file.c b/fs/omfs/file.c
> index 2c
On Thu 2020-12-10 16:08:05, Andy Shevchenko wrote:
> On Thu, Dec 10, 2020 at 03:55:27PM +0200, Sakari Ailus wrote:
> > On Thu, Dec 10, 2020 at 03:05:02PM +0200, Andy Shevchenko wrote:
> > > My concerns are:
> > > - not so standard format of representation (why not to use
> > > string_escape_mem() h
I have been chasing down a problem enumerating an NVMe drive on a
Honeycomb LX2K (NXP LX2160A). Specifically the drive can only enumerate
successfully if the we are emitting lots of console messages via a UART.
If the system is booted with `quiet` set then enumeration fails.
I guessed this would b
> -Original Message-
> From: Jonathan Cameron
> Sent: Monday 30 November 2020 8:21 PM
> To: Bartosz Golaszewski
> Cc: Lars-Peter Clausen ; Peter Meerwald-Stadler
> ; Michal Simek ; linux-
> i...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Bartos
On Fri, Dec 11, 2020 at 12:47 PM Jan Kara wrote:
>
> On Fri 11-12-20 10:42:16, Amir Goldstein wrote:
> > On Fri, Dec 11, 2020 at 1:45 AM Hugh Dickins wrote:
> > >
> > > Hi Jan, Amir,
> > >
> > > There's something wrong with linux-next commit ca7fbf0d29ab
> > > ("fsnotify: fix events reported to w
Hello,
syzbot found the following issue on:
HEAD commit:3cc2bd44 Add linux-next specific files for 20201211
git tree: linux-next
console output: https://syzkaller.appspot.com/x/log.txt?x=11627b1350
kernel config: https://syzkaller.appspot.com/x/.config?x=6dbe20fdaa5aaebe
dashboard
On Fri, Dec 11, 2020 at 12:58:00PM +0100, Alexandre Belloni wrote:
> On 11/12/2020 11:50:55+, Sudeep Holla wrote:
> > On Fri, Dec 11, 2020 at 12:45:15PM +0100, Alexandre Belloni wrote:
> > > Hello,
> > >
> > > On 11/12/2020 10:31:43+, Sudeep Holla wrote:
> > > > Since at91_soc_init is call
On Fri, Dec 11, 2020 at 11:33:02AM +, Kelly, Seamus wrote:
> This e-mail and any attachments may contain confidential material for the sole
> use of the intended recipient(s). Any review or distribution by others is
> strictly prohibited. If you are not the intended recipient, please contact th
On 11.12.20 00:20, boris.ostrov...@oracle.com wrote:
On 12/10/20 2:26 PM, Thomas Gleixner wrote:
All event channel setups bind the interrupt on CPU0 or the target CPU for
percpu interrupts and overwrite the affinity mask with the corresponding
cpumask. That does not make sense.
The XEN impleme
On Fri, Dec 11, 2020 at 09:18:24AM +, József Horváth wrote:
> On Fri, Dec 11, 2020 at 09:43:31AM +0100, 'Greg Kroah-Hartman' wrote:
> > On Fri, Dec 11, 2020 at 08:16:34AM +, József Horváth wrote:
> > > On Fri, Dec 11, 2020 at 08:33:17AM +0100, 'Greg Kroah-Hartman' wrote:
> > > > On Fri, Dec
On Thu, 10 Dec 2020 at 19:58, Greg Kroah-Hartman
wrote:
>
> This is the start of the stable review cycle for the 4.4.248 release.
> There are 39 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Res
Hi,
On 11/12/20 11:34 am, Aswath Govindraju wrote:
> Add compatible string in j721e-usb binding file as the same USB subsystem
> is present in AM64.
>
> Signed-off-by: Aswath Govindraju
> ---
>
> Changes since v3:
> - used enum instead of anyOf.
>
> Changes since v2:
> - added changes done over
On Thu, 10 Dec 2020 at 20:00, Greg Kroah-Hartman
wrote:
>
> This is the start of the stable review cycle for the 4.9.248 release.
> There are 45 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Res
On Fri, 2020-12-11 at 20:27 +0900, Yoshihiro Shimoda wrote:
> To simplify this driver, use dev_get_regmap() and
> rid of using struct bd9571mwv.
>
> Signed-off-by: Yoshihiro Shimoda
> ---
> drivers/regulator/bd9571mwv-regulator.c | 49 +
>
> 1 file changed, 26 i
The Hiedma Controller v310 Provides eight DMA channels, each
channel can be configured for one-way transfer. The data can
be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
documentation describes DT bindings of this controller.
Signed-off-by: Dongjiu Geng
---
.../bindings/dma/hisilic
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
---
.../clock/hisilicon,hi3559av100-clock.yaml| 59 +++
include/dt-bindings/clock/hi3559av100-clock.h | 165 ++
2 files changed, 224 insertions(+)
create mode 100644
Documentation/devicetr
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/clk-hi3559a.c | 865 ++
Hisilicon EDMA Controller(EDMAC) directly transfers data
between a memory and a peripheral, between peripherals, or
between memories. This avoids the CPU intervention and reduces
the interrupt handling overhead of the CPU, this driver enables
this controller.
Reported-by: kernel test robot
Signed
On 11/12/2020 11:50:55+, Sudeep Holla wrote:
> On Fri, Dec 11, 2020 at 12:45:15PM +0100, Alexandre Belloni wrote:
> > Hello,
> >
> > On 11/12/2020 10:31:43+, Sudeep Holla wrote:
> > > Since at91_soc_init is called unconditionally from atmel_soc_device_init,
> > > we get the following warni
v5->v6:
1. Drop #size-cells and #address-cell in the hisilicon,hi3559av100-clock.yaml
2. Add discription for #reset-cells in the hisilicon,hi3559av100-clock.yaml
3. Remove #clock-cells in hisilicon,hiedmacv310.yaml
4. Merge property misc_ctrl_base and misc_regmap together for hiedmacv310 driver
v
On 12/7/2020 4:12 PM, Akhil P Oommen wrote:
Add support for gpu fuse to help identify the supported opps.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b
v5->v6:
1. Drop #size-cells and #address-cell in the hisilicon,hi3559av100-clock.yaml
2. Add discription for #reset-cells in the hisilicon,hi3559av100-clock.yaml
3. Remove #clock-cells in hisilicon,hiedmacv310.yaml
4. Merge property misc_ctrl_base and misc_regmap together for hiedmacv310 driver
v
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
---
.../clock/hisilicon,hi3559av100-clock.yaml| 59 +++
include/dt-bindings/clock/hi3559av100-clock.h | 165 ++
2 files changed, 224 insertions(+)
create mode 100644
Documentation/devicetr
The Hiedma Controller v310 Provides eight DMA channels, each
channel can be configured for one-way transfer. The data can
be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
documentation describes DT bindings of this controller.
Signed-off-by: Dongjiu Geng
---
.../bindings/dma/hisilic
On 12/7/2020 4:12 PM, Akhil P Oommen wrote:
Some GPUs support different max frequencies depending on the platform.
To identify the correct variant, we should check the gpu speedbin
fuse value. Add support for this speedbin detection to a6xx family
along with the required fuse details for a618 gpu
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/clk-hi3559a.c | 865 ++
Hisilicon EDMA Controller(EDMAC) directly transfers data
between a memory and a peripheral, between peripherals, or
between memories. This avoids the CPU intervention and reduces
the interrupt handling overhead of the CPU, this driver enables
this controller.
Reported-by: kernel test robot
Signed
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
---
.../clock/hisilicon,hi3559av100-clock.yaml| 59 +++
include/dt-bindings/clock/hi3559av100-clock.h | 165 ++
2 files changed, 224 insertions(+)
create mode 100644
Documentation/devicetr
The Hiedma Controller v310 Provides eight DMA channels, each
channel can be configured for one-way transfer. The data can
be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
documentation describes DT bindings of this controller.
Signed-off-by: Dongjiu Geng
---
.../bindings/dma/hisilic
Hisilicon EDMA Controller(EDMAC) directly transfers data
between a memory and a peripheral, between peripherals, or
between memories. This avoids the CPU intervention and reduces
the interrupt handling overhead of the CPU, this driver enables
this controller.
Reported-by: kernel test robot
Signed
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/clk-hi3559a.c | 865 ++
From: g00384164
v5->v6:
1. Drop #size-cells and #address-cell in the hisilicon,hi3559av100-clock.yaml
2. Add discription for #reset-cells in the hisilicon,hi3559av100-clock.yaml
3. Remove #clock-cells in hisilicon,hiedmacv310.yaml
4. Merge property misc_ctrl_base and misc_regmap together for hie
On Fri, Dec 11, 2020 at 12:45:15PM +0100, Alexandre Belloni wrote:
> Hello,
>
> On 11/12/2020 10:31:43+, Sudeep Holla wrote:
> > Since at91_soc_init is called unconditionally from atmel_soc_device_init,
> > we get the following warning on all non AT91 SoCs:
> > " AT91: Could not find ident
Hello,
On 11/12/2020 10:31:43+, Sudeep Holla wrote:
> Since at91_soc_init is called unconditionally from atmel_soc_device_init,
> we get the following warning on all non AT91 SoCs:
> " AT91: Could not find identification node"
>
> Fix the same by filtering with allowed AT91 SoC list.
>
The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
On platforms with Zhaoxin CPUs supporting this X86 feature, When
crc32c-intel and crc32c-generic are both registered, system will
use crc32c-intel because its .cra_priority is greater than
crc32c-generic. This case expect to use crc3
On 11/12/20 02:27, Sean Christopherson wrote:
Michael, please reply to all so that everyone can read along and so that the
conversation gets recorded in the various mailing list archives.
If you are replying all, then I think something funky is going on with AMD's
mail servers, as I'm not gettin
Hi Valentin,
On Thu, Dec 10, 2020 at 04:38:30PM +, Valentin Schneider wrote:
> Per-CPU kworkers forcefully migrated away by hotplug via
> workqueue_offline_cpu() can end up spawning more kworkers via
>
> manage_workers() -> maybe_create_worker()
>
> Workers created at this point will be bo
On Thu, 10 Dec 2020 10:26:22 -0500
Matthew Rosato wrote:
> On 12/10/20 5:33 AM, Cornelia Huck wrote:
> > On Wed, 9 Dec 2020 15:27:47 -0500
> > Matthew Rosato wrote:
> >
> >> Some zpci device types (e.g., ISM) follow different rules for length
> >> and alignment of pci instructions. Recogniz
On Fri, 2020-12-11 at 20:27 +0900, Yoshihiro Shimoda wrote:
> Add chip IDs for BD9571MWV and BD9574MWF.
>
> Signed-off-by: Yoshihiro Shimoda
> ---
> include/linux/mfd/rohm-generic.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/linux/mfd/rohm-generic.h
> b/include/linux/mf
-Original Message-
From: Joe Perches
Sent: Wednesday, December 9, 2020 8:31 AM
To: mgr...@linux.intel.com; markgr...@kernel.org; a...@arndb.de; b...@suse.de;
damien.lem...@wdc.com; dragan.cve...@xilinx.com; gre...@linuxfoundation.org;
cor...@lwn.net; leonard.cres...@nxp.com; palmerda
Hi again,
> From: Yoshihiro Shimoda, Sent: Friday, December 11, 2020 9:49 AM
>
> > but as I said - these are only 'nit' comments and I am not insisting on
> > changing these. Especially since some of the comments are more related
> > to changing the original bd9571mwv than adding support for this
-Original Message-
From: Joe Perches
Sent: Monday, December 7, 2020 2:55 AM
To: mgr...@linux.intel.com; markgr...@kernel.org; a...@arndb.de; b...@suse.de;
damien.lem...@wdc.com; dragan.cve...@xilinx.com; gre...@linuxfoundation.org;
cor...@lwn.net; leonard.cres...@nxp.com; palmerdabb.
On 20-12-02 21:52:32, Minwoo Im wrote:
> Removed credential argument comment with no functional changes.
>
> Signed-off-by: Minwoo Im
> ---
> fs/open.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/fs/open.c b/fs/open.c
> index 9af548fb841b..85a532af0946 100644
> --- a/fs/open.c
> +++
From: Joe Perches
Sent: Monday, December 7, 2020 2:33 AM
To: mgr...@linux.intel.com; markgr...@kernel.org; a...@arndb.de; b...@suse.de;
damien.lem...@wdc.com; dragan.cve...@xilinx.com; gre...@linuxfoundation.org;
cor...@lwn.net; leonard.cres...@nxp.com; palmerdabb...@google.com;
paul.walms..
Each sgx_mmun_notifier_release() starts a grace period, which means that
one extra synchronize_rcu() in sgx_encl_release(). Add it there.
sgx_release() has the loop that drains the list but with bad luck the
entry is already gone from the list before that loop processes it.
Fixes: 1728ab54b4be ("
On 20-12-05 00:20:52, Minwoo Im wrote:
> Hello,
>
> This patch set contains:
> - Introduce a helper to allocate tagset tags for the first time
> without 'realloc' keyword that used to be taken.
> - Fixes for comments need to be updated.
>
> Please have a look.
>
> Thanks,
>
>
> Minwoo
+ Christoph
On Mon, 7 Dec 2020 at 12:58, Bhaskara Budiredla wrote:
>
> This patch introduces to mmcpstore. The functioning of mmcpstore
> is similar to mtdpstore. mmcpstore works on FTL based flash devices
> whereas mtdpstore works on raw flash devices. When the system crashes,
> mmcpstore stores
Hi Yan,
On 09/12/2020 11:44, Xuewen Yan wrote:
> when a task dequeued, it will update it's util, and cfs_rq_util_change
> would check rq's util, if the cfs_rq->avg.util_est.enqueued is bigger
> than cfs_rq->avg.util_avg, but because the cfs_rq->avg.util_est.enqueued
> didn't be decreased, this wo
Use the SPDX license identifier instead of a local description.
Signed-off-by: Yoshihiro Shimoda
---
drivers/mfd/bd9571mwv.c | 10 +-
include/linux/mfd/bd9571mwv.h | 10 +-
2 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/drivers/mfd/bd9571mwv.c b/drivers/mfd
To simplify this driver, use dev_get_regmap() and
rid of using struct bd9571mwv.
Signed-off-by: Yoshihiro Shimoda
---
drivers/regulator/bd9571mwv-regulator.c | 49 +
1 file changed, 26 insertions(+), 23 deletions(-)
diff --git a/drivers/regulator/bd9571mwv-regula
From: Khiem Nguyen
Since the driver supports BD9571MWV PMIC only,
this patch makes the functions and data structure become more generic
so that it can support other PMIC variants as well.
Signed-off-by: Khiem Nguyen
[shimoda: rebase and refactor]
Signed-off-by: Yoshihiro Shimoda
---
drivers/m
From: Khiem Nguyen
The new PMIC BD9574MWF inherits features from BD9571MWV.
Add the support of new PMIC to existing bd9571mwv driver.
Signed-off-by: Khiem Nguyen
[shimoda: rebase and refactor]
Signed-off-by: Yoshihiro Shimoda
---
drivers/mfd/bd9571mwv.c | 86
Add support for BD9574MWF which is silimar chip with BD9571MWV.
Note that BD9574MWF doesn't support AVS and VID.
Signed-off-by: Yoshihiro Shimoda
---
drivers/regulator/bd9571mwv-regulator.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/regulator/bd9571mwv
Use the SPDX license identifier instead of a local description.
Signed-off-by: Yoshihiro Shimoda
---
drivers/gpio/gpio-bd9571mwv.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpio/gpio-bd9571mwv.c b/drivers/gpio/gpio-bd9571mwv.c
index c0abc9c..abb622c 10
Add support for BD9574MWF which is silimar chip with BD9571MWV.
Note that BD9574MWF has an additional feature, but doesn't
support it for now.
Signed-off-by: Yoshihiro Shimoda
---
drivers/gpio/gpio-bd9571mwv.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio
Document other similar specification chip BD9574MWF.
Signed-off-by: Yoshihiro Shimoda
---
Documentation/devicetree/bindings/mfd/bd9571mwv.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/bd9571mwv.txt
b/Documentation/devicetree/bi
Add BD9574MWF support into bd9571mwv gpio, mfd and regulator drivers.
Latest Ebisu-4D boards has this chip instead of BD9571MWV so that
we need this patch series.
Changes from v1:
- Document BD9574MWF on the dt-binding.
- Add ROHM_CHIP_TYPE_BD957[14] into rohm-generic.h.
- To simplify gpio and
To simplify this driver, use dev_get_regmap() and
rid of using struct bd9571mwv.
Signed-off-by: Yoshihiro Shimoda
---
drivers/gpio/gpio-bd9571mwv.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpio/gpio-bd9571mwv.c b/drivers/gpio/gpio-bd9571mwv
Add chip IDs for BD9571MWV and BD9574MWF.
Signed-off-by: Yoshihiro Shimoda
---
include/linux/mfd/rohm-generic.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h
index 4283b5b..affacf8 100644
--- a/include/linux/mfd/rohm-gen
From: SeongJae Park
On a few of our systems, I found frequent 'unshare(CLONE_NEWNET)' calls
make the number of active slab objects including 'sock_inode_cache' type
rapidly and continuously increase. As a result, memory pressure occurs.
In more detail, I made an artificial reproducer that resem
On Tue, Dec 01, 2020 at 05:31:41PM +0800, Qinglang Miao wrote:
> In i2c_imx_xfer() and i2c_imx_remove(), the pm reference count
> is not expected to be incremented on return.
>
> However, pm_runtime_get_sync will increment pm reference count
> even failed. Forgetting to putting operation will resu
From: Lee Jones
> Sent: 11 December 2020 10:06
>
> On Fri, 11 Dec 2020, Zheng Yongjun wrote:
>
> > Replace a comma between expression statements by a semicolon.
> >
> > Signed-off-by: Zheng Yongjun
> > ---
> > drivers/mfd/rave-sp.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
>
On 2020-12-11 09:36, Can Guo wrote:
On 2020-12-11 01:34, Bean Huo wrote:
Hi Can
On Wed, 2020-12-09 at 05:35 -0800, Can Guo wrote:
@@ -1160,6 +1166,7 @@ static void
ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
{
up_write(&hba->clk_scaling_lock);
ufshcd_scsi_unblock_req
On 10-12-20, 10:38, Ionela Voinescu wrote:
> Basically, that's functions purpose is only to make sure that invariance
> at the level of the policy is consistent: either all CPUs in a policy
> support counters and counters will be used for the scale factor, or
> either none or only some support coun
With lockdep enabled, we will get following warning:
ar9331_switch ethernet.1:10 lan0 (uninitialized): PHY
[!ahb!ethernet@1a00!mdio!switch@10:00] driver [Qualcomm Atheros AR9331
built-in PHY] (irq=13)
BUG: sleeping function called from invalid context at
kernel/locking/mutex.c:935
in_ato
On Thu, 2020-12-10 at 21:10 -0600, Tyler Hicks wrote:
> On 2020-11-29 08:17:38, Mimi Zohar wrote:
> > Hi Sasha,
> >
> > On Wed, 2020-07-08 at 21:27 -0400, Sasha Levin wrote:
> > > On Wed, Jul 08, 2020 at 12:13:13PM -0400, Mimi Zohar wrote:
> > > >Hi Sasha,
> > > >
> > > >On Wed, 2020-07-08 at 11:4
Hi Joel,
On 2020/12/11, 6:55 PM, Joel Stanley wrote:
On Fri, 11 Dec 2020 at 03:18, Billy Tsai wrote:
>
> The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from
> SCU414 to SCU4B4.
> Besides that, When PWM8~15 of PWMG0 set it needs to clear SCU414 bits at
>
On Fri, Dec 11, 2020 at 12:51:46PM +0200, Jarkko Sakkinen wrote:
> On Wed, Dec 09, 2020 at 12:14:24PM +, David Howells wrote:
> >
> > Hi Jarkko,
> >
> > I've extended my collection of minor keyrings fixes for the next merge
> > window. Anything else I should add (or anything I should drop)?
On Fri, 11 Dec 2020 at 03:18, Billy Tsai wrote:
>
> The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from
> SCU414 to SCU4B4.
> Besides that, When PWM8~15 of PWMG0 set it needs to clear SCU414 bits at
> the same time.
>
> Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux sup
On Thu, Dec 10, 2020 at 09:55:15PM +0800, Zheng Yongjun wrote:
> Simplify the return expression.
>
> Signed-off-by: Zheng Yongjun
I don't see how this would be meaningful change as the existing
code is according to the coding style.
> ---
> drivers/char/tpm/tpm_tis_synquacer.c | 7 +--
> 1
Add stats support for the ar9331 switch.
Signed-off-by: Oleksij Rempel
---
drivers/net/dsa/qca/ar9331.c | 256 ++-
1 file changed, 255 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/qca/ar9331.c b/drivers/net/dsa/qca/ar9331.c
index 4d49c5f2b790..5baef0
> Am 11.12.2020 um 10:35 schrieb Oscar Salvador :
>
> On Thu, Dec 10, 2020 at 11:55:20AM +0800, Muchun Song wrote:
>> When we free a HugeTLB page to the buddy allocator, we should allocate the
>> vmemmap pages associated with it. We can do that in the __free_hugepage()
> "vmemmap pages that des
Allow DSA drivers to export stats64
Signed-off-by: Oleksij Rempel
Reviewed-by: Vladimir Oltean
---
include/net/dsa.h | 3 +++
net/dsa/slave.c | 14 +-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/include/net/dsa.h b/include/net/dsa.h
index 4e60d2610f20..457b8914
changes v5:
- read all stats in one regmap_bulk_read() request
- protect stats with u64_stats* helpers.
changes v4:
- do no read MIBs withing stats64 call
- change polling frequency to 0.3Hz
changes v3:
- fix wrong multiplication
- cancel port workers on remove
changes v2:
- use stats64 instead
On Wed, Dec 09, 2020 at 12:14:24PM +, David Howells wrote:
>
> Hi Jarkko,
>
> I've extended my collection of minor keyrings fixes for the next merge
> window. Anything else I should add (or anything I should drop)?
>
> The patches can be found on the following branch:
>
>
> https://
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